Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part II

Computer Architecture I: Digital Design

Dr. Robert D. Kent

Logic DesignMedium Scale Integration andProgrammable Logic Devices

Part II

Review

• At the outset of designing a complex system, such as a modern computer or network, it is clear that design is extraordinarily difficult and computationally challenging when performed at the level of fundamental Boolean logic gates.

• For these reasons modern design approaches are based on hierarchical, component based methods.– Leading to simplified, localized component design,

– lowering of design costs,

– shifting some aspects of design to the component interface (the compatibility problem).

• We now continue our study of MSI circuits to better understand this process of MSI design.

Goals

• We continue our study of simple, but functional Combinational circuits:

– we continue constructing a small library of useful components

– through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design

– we seek to identify these components for their re-use potential

– through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.

Circuit # 4 : Binary Subtractor


• Before proceeding to design a subtractor circuit, consider a few examples of the operation D = X - Y:

• Example 1 :

Example 1 :

X 0 0 1 1

-Y 0 0 0 1

=======

D 0 0 1 0

Considered “easy” because:

1-1 = 0 is easy

1-0 = 1 is easy

0-0 = 0 is easy

But .....

Circuit # 4 : Binary Subtractor• Example 2 :

– This is not straightforward – it requires the concept of “borrowing” from the column on the left.– Use a trick – add zero! Introduce a borrow constant, B. For an L-bit representation, B = 2L.

Example 2 :

B= 1 0 0 0 0

X 0 0 1 1

-Y 0 1 0 1

=======

D 1 1 1 0

This is not a mathematical zero.

Rather, it is a practical zero since we only use the low-order 4 bits.



Instead of XK – YK, we have recast this in the form BK + XK – YK.

NOTE: By borrowing from the left, each successive borrow digit becomes a 1 until the column which forces the first borrow. This specific borrow digit has the value 2 (binary 10).

B= 0 1 2 0 0



Now we note that we have already borrowed from this column (in the next-to-right column).

But we also had to borrow from the next-to-left column. Hence, we borrow a ‘2’ from the left, then borrow ‘1’ from this ‘2’ to the right, the net result is to add ‘1’ to the current column.

The rest of the subtraction (+2-1+0-0)=1 is easy.

B= 0 1 2 0 0


• We begin the design by constructing a 3-input/2-output truth table:

XK YK BK DK BK+1

XK and YK are the inputs for (XK-YK) and DK is the difference (within the K’th column)

BK refers to the amount of borrowing already performed (in order to carry out a subtraction in the next-to-right column)

BK+1 refers to the amount of borrowing that must be done from the next-to-left column (in order to carry out a subtraction in the current K’th column)

NOTE: It is understood that a ‘1’ denotes a borrow of ‘2’ in the current K’th column.



XK YK BK DK BK+1 0 0 0 0 0

0 XK minuend - 0 YK subtrahend

0 DK difference



XK YK BK DK BK+1 0 0 0 0 0

There is no need to

perform a “borrow” operation.


0 DK difference



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 0

0 XK minuend - 0 YK subtrahend - 1 BK prior borrow

1 DK difference 1 BK+1 next borrow



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 0



Assume that a “borrow” was required in a previous column

subtraction - then we must subtract 1 from the minuend in this column.



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 1



If the subtraction cannot be performed,

then we must “borrow” from the next column. We note this borrow as BK+1 , and then use the

value 2 (!) for the minuend, XK .

2



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1





XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1






2



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1





XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1






2



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0



There is no need to




XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0



There is no need to




XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0



There is no need to




XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1






2



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

• The circuit expressions for the outputs are derived:



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1


DK = XK’YK’BK + XK’YKBK’ + XKYK’BK’ + XKYKBK



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1


DK = XK’YK’BK + XK’YKBK’ + XKYK’BK’ + XKYKBK

= BK xor XK xor YK



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 DK = BK xor XK xor YK 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1






BK+1 = XK’YK’BK + XK’YKBK’ + XK’YKBK + XKYKBK






= XK’YK(BK + BK’) + XK’(YK + YK’)BK + (XK + XK’)YKBK



XK YK BK DK BK+1 0 0 0 0 0 0 0 1 1 10 1 0 1 1 DK = BK xor XK xor YK 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 BK+1 = XK’YK + XK’BK + YKBK 1 1 0 0 0 1 1 1 1 1



= XK’YK(BK + BK’) + XK’(YK + YK’)BK + (XK + XK’)YKBK


• This leads to the expressions:

DK = BK xor XK xor YK

BK+1 = XK’YK + XK’BK + YKBK

• These have the logic gate realizations:






BK

XK

YK

DK

BK+1

FS






BK

XK

YK

DK

BK+1

FS

Full Subtractor

Binary Full Subtractor

BK

XK

YK

DK

BK+1

FS


• We can now employ the 1-bit Full Subtractor to construct a multi-bit subtractor

– we use a FS with B0 = 0 for the first bit.

– this can be replaced with a specialized Half-Subtractor circuit.

BK

XK

YK

DK

BK+1

FS



– we use a FS with B0 = 0 for the first bit. (This can be replaced with a specialized Half-Subtractor circuit).

Y X Bin

Bout S

Y X Bin

Bout S

Y X Bin

Bout S

Y X Bin

Bout S

Y0 X0 Y1 X1 Y2 X2 Y3 X3

S0S1S3 S2

Bout

0

4-bit MSI: Ripple Subtractor



– we use a FS with B0 = 0 for the first bit. This can be replaced with a specialized Half-Subtractor circuit.

Y X Bin

Bout D

Y X Bin

Bout D

Y X Bin

Bout D

Y X Bin

Bout D

Y0 X0 Y1 X1 Y2 X2 Y3 X3

D0D1D3 D2

Bout

0

4-bit MSI: Ripple Subtractor

Y3 Y2 Y1 Y0 X3 X2 X1 X0

Bout Bin

D3 D2 D1 D0

4-bit MSI: Full Ripple Subtractor


• Note that the Full Adder and Full Subtractor are identical, except for a single inverter applied to the first input (A or X):

BK

XK

YK

DK

BK+1

FS

Full Subtractor

Binary Full Subtractor

BK

XK

YK

DK

BK+1

FS

Cin

AB

S

Cout

FA

Binary Full Adder

CK

XK

YK

DK

CK+1

FA


• There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations.



• Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to 1.



• Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to 1.

Y3 Y2 Y1 Y0 X3 X2 X1 X0

Cout Cin

S3 S2 S1 S0

4-bit MSIFull Ripple Adder 1

Circuit # 5 : Binary Adder/Subtractor


• Finally, we note the following facts about the xor gate:



A xor 1 = A’



A xor 1 = A’ Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’




A xor 0 = A




A xor 0 = A Proof: 0 xor 0 = 0 1 xor 0 = 1





• These properties of the xor gate allow us to construct a circuit that can perform either addition or subtraction:






S3 S2 S1 S0

4-bit MSIFull Ripple

Adder/Subtractor

Add(0)/

Sub(1)

Y3 Y2 Y1 Y0 X3 X2 X1 X0






S3 S2 S1 S0


Adder/Subtractor

Add(0)/

Sub(1)

Y3 Y2 Y1 Y0 X3 X2 X1 X0

The input carry bit is used as a

toggle to control the choice of

addition or subtraction.

+/- +/- +/- +/-


• Now that it has been demonstrated that subtraction can be carried out using addition circuits, we may henceforth treat only addition cases, without any loss of generality.

S3 S2 S1 S0


Adder/Subtractor

Add(0)/

Sub(1)

Y3 Y2 Y1 Y0 X3 X2 X1 X0

+/- +/- +/- +/-

Circuit # 6 : Carry Lookahead Adder


• The representation of the Carry-out circuit for the full adder is:

CK+1 = XK YK + CK XK + CK YK

= XK YK + CK (XK + YK)





• Define terms: gK = XK YK and, pK = (XK + YK)

• We may now write:

CK+1 = gK + CK pK





• Define terms: gK = XK YK and, pK = (XK + YK)

• We may now write:

CK+1 = gK + CK pK

• Also, recall that the sum bit is generated using the expression:

SK = CK xor AK xor BK


• Using the expressions:

CK+1 = gK + CK pK


We define the Sigma-block circuit:

XK YK CK

PK

GK

SK

Circuit # 6 : Carry Lookahead Adder• Using the expressions:

CK+1 = gK + CK pK



• This may be abbreviated as the MSI component:

XK YK CK

PK

GK

SK

PK

GKSK

XK YK CK

SIG

Circuit # 6 : Carry Lookahead Adder• Using the expressions:

CK+1 = gK + CK pK

SK = CK AK BK


• This may be abbreviated as the MSI component:

XK YK CK

PK

GK

SK

PK

GKSK

XK YK CK

Note that both P and G only

require evaluation of

one logic gate.

SIG


• These results suggest that the previous ripple-adder circuit may be replaced by the following circuit, using Sigma-blocks:

P0

G0S0

X0 Y0 C0

P1

G1S1

X1 Y1 C1

P3

G3S3

X3 Y3 C3

P2

G2S2

X2 Y2 C2

Carry lookahead network

C4

C0

SIG SIG SIGSIG


• Expanding the carry terms for a 4-bit adder:

C1 = g0 + C0 p0

C2 = g1 + C1 p1

= g1 + (g0 + C0 p0 )p1

= g1 + g0 p1 + C0 p0 p1

C3 = g2 + C2 p2

= g2 + g1 p2 + g0 p1 p2 + C0 p0 p1 p2

C4 = g3 + C3 p3

= g3 + g2 p3 + g1 p2 p3 + g0 p1 p2 p3 + C0 p0 p1 p2 p3


• Expanding the carry terms for a 4-bit adder:

C1 = g0 + C0 p0

C2 = g1 + C1 p1

= g1 + (g0 + C0 p0 )p1

= g1 + g0 p1 + C0 p0 p1

C3 = g2 + C2 p2

= g2 + g1 p2 + g0 p1 p2 + C0 p0 p1 p2

C4 = g3 + C3 p3

= g3 + g2 p3 + g1 p2 p3 + g0 p1 p2 p3 + C0 p0 p1 p2 p3

Note that all the carry expressions require only two

evaluation stages (one for the and, the other for the

or).


• These results can now be used to complete the Carry lookahead network portion of the 4-bit adder:

P0

G0S0

X0 Y0 C0

P1

G1S1

X1 Y1 C1

P3

G3S3

X3 Y3 C3

P2

G2S2

X2 Y2 C2


C4

C0

SIG SIG SIG SIG



P0

G0

P1

G1

P3

G3

P2

G2


C4

C0

C2C3 C1



P0

G0

P1

G1

P3

G3

P2

G2


C4

C0

C2C3 C1

Now it is clear that evaluation of each carry requires, at

most, 3 logic gates. Thus, each sum digit requires at most 4

logic gates.


• This brings us back to the basic, 4-bit MSI Adder/Subtractor, which may now be assumed to be optimized with carry lookahead circuits.

• These may be used, in turn, to develop more powerful multi-bit adder/subtractors.

Cout Cin

S3 S2 S1 S0

4-bit MSIFull

Adder/Subtractor

Add(0)/

Sub(1)

Y3 Y2 Y1 Y0 X3 X2 X1 X0

Circuit # 7 : Decimal Adder


• There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421).

– BCD: 0 1 2 7 8 9

0000, 0001, 0010, … , 0111, 1000, 1001

Remind yourself that BCD uses a 4-bit representation to store the values of digits 0..9, but this leaves wastage of some bit patterns (unused patterns).


• There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421).

– BCD: 0 1 2 7 8 9

0000, 0001, 0010, … , 0111, 1000, 1001

• To illustrate some of the issues we consider one example of decimal addition of single digits, leading to a full decimal adder.

– This design will be based on the use of the binary adder.


• Note that the problem of adding two decimal digits together, in general, also requires accounting for an input carry and an output carry.

Minimum Sum: Maximum Sum:

0 (No carry) 1 (Carry) 0 9+ 0 + 9 0 19

(No Carry out)DECIMAL ARITHMETIC (Carry out)

• Note also that the maximum number of distinct sums is 20.


• Note that the problem of adding two decimal digits together, in general, also requires accounting for an input carry and an output carry.

Minimum Sum: Maximum Sum:

0 (No carry) 1 (Carry) 0 9+ 0 + 9 0 19

DECIMAL ARITHMETIC (Carry out)

• Note that the maximum number of distinct sums is 20.

Consider the example:

Carry 1110

999 + 99 ==== Sum 1998


• We can obtain the sumsin two stages.

Circuit # 7 : Decimal Adder• We can obtain the sums

in two stages.

• First, list all possible outputs from the direct sum of the decimaldigits, then …..

K P3 P2 P1 P0

0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1

1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1

Direct sum of decimal digits,ranging from

0 to 1910, represented in 5-bit form with

high-order bit K.

Circuit # 7 : Decimal Adder• We can obtain the sums

in two stages.

• First, list all possible outputs from the direct sum of the decimaldigits, then …..

• Beside each sum placethe expected values ofthe sum bits and thecarry out bit.

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1

Expected outputs, with

sum bits SJ and carry-out bit C.

Circuit # 7 : Decimal Adder• The first-stage sums

divide into two groups:

– the first ten sumsproduce the correctfinal sum and carrybit patterns

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1




– the last ten sumsare all incorrect bythe same amount,they should have 6 added to them to produce the correctfinal bit patterns.

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1




– the last ten sumsare all incorrect bythe same amount,they should have 6 added to them to produce the correctfinal bit patterns.

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1

+ 6 =

+ 6 =


• The condition used to identify and control the correction process isexpressed in terms of the carry-out bit, C:

C = K + P3 P2 + P3 P1

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1



C = K + P3 P2 + P3 P1

• Thus, if C = 0 then nocorrection is applied.

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1



C = K + P3 P2 + P3 P1

• Thus, if C = 0 then nocorrection is applied.

• If C = 1, then 6 is addeddirectly to the initial sumbits PJ .

K P3 P2 P1 P0 C S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 10 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1

+ 6 =

+ 6 =

This is referred to as the “Excess-64” technique for BCD addition.



C = K + P3 P2 + P3 P1

• A decimal full-adder circuit follows usinga two-stage 4-bit binaryadder MSI circuit and

• Uses the carry bit valuedirectly to generate thevalue 610, or 01102.

S3 S2 S1 S0

x3 x2 x1 x0 y3 y2 y1 y0

C4 4-bit binary adder C0

s3 s2 s1 s0

P3 P2 P1 P0

A3 A2 A1 A0 B3 B2 B1 B0

CinK x3 x2 x1 x0 y3 y2 y1 y0


s3 s2 s1 s0

Cout

0

Add 6


• This MSI circuit is used to form the basis for a multi-decade decimal adder.

S3 S2 S1 S0

x3 x2 x1 x0 y3 y2 y1 y0


s3 s2 s1 s0

P3 P2 P1 P0

A3 A2 A1 A0 B3 B2 B1 B0



s3 s2 s1 s0

Cout

0

Add 6A3 A2 A1 A0 B3 B2 B1 B0

x3 x2 x1 x0 y3 y2 y1 y0

C4 BCD Decade adder C0

s3 s2 s1 s0

S3 S2 S1 S0

Time out for some Design Philosophy!

Time out for some Philosophy!

• In software design and construction the programmer/analyst becomes familiar with identifying different aspects of the problem in terms of abstract models.

• Some of these models are quite concrete (bottom-up design) while others are relatively more abstract and require gradual expression of their detail (top-down design).


• Increasingly, modern Software Design is expressed in terms of components (functions, classes/objects, templates, metaprogramming) and focuses on software component re-use.

• One critical problem of software re-use lies in the proper, robust, flexible and standards-based design of the component interfaces.

• Other issues arise in the contexts of software complexity, performance, cost and other factors.


• Differential layering of abstraction in design also has its place in hardware design.

SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components

• These differences have been demonstrated in each of the circuits/components that we have considered so far.


• Differential layering of abstraction in design also has its place in hardware design.

SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components

• These differences have been demonstrated in each of the circuits/components that we have considered so far.

S3 S2 S1 S0

x3 x2 x1 x0 y3 y2 y1 y0


s3 s2 s1 s0

P3 P2 P1 P0

A3 A2 A1 A0 B3 B2 B1 B0



s3 s2 s1 s0

Cout

0

Add 6

Cin

AB

S

Cout

FA

Binary Full Adder

Circuit # 8 : Comparator


• The comparison of two (binary) numbers is of considerable importance.

– if ( A < B ) then …

– while ( A > B ) do ...



– if ( A < B ) then …

– while ( A > B ) do ...

• It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions:

A = B A > B A < B



– if ( A < B ) then …

– while ( A > B ) do ...

• It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions:

A = B A > B A < B

These conditions may be encoded using 3 flag bits:

E = 1 G = 1 L = 1


• One strategy is to perform the comparison bit-wise and from right to left.



• Express the two bit strings to be compared, A and B:

AN … AK AK-1 … A1 A0 and BN … BK BK-1 … B1 B0



• Express the two bit strings to be compared, A and B:

AN … AK AK-1 … A1 A0 and BN … BK BK-1 … B1 B0

• Now, restrict attention to the substrings:

AK AK-1 … A1 A0 and BK BK-1 … B1 B0


• We begin with three distinct, possible assumptions:



AK-1 … A1 A0 = BK-1 … B1 B0 EK-1 = 1 , GK-1 = 0 , LK-1 = 0



AK-1 … A1 A0 = BK-1 … B1 B0 EK-1 = 1 , GK-1 = 0 , LK-1 = 0

AK-1 … A1 A0 > BK-1 … B1 B0 EK-1 = 0 , GK-1 = 1 , LK-1 = 0



AK-1 … A1 A0 = BK-1 … B1 B0 EK-1 = 1 , GK-1 = 0 , LK-1 = 0

AK-1 … A1 A0 > BK-1 … B1 B0 EK-1 = 0 , GK-1 = 1 , LK-1 = 0

AK-1 … A1 A0 < BK-1 … B1 B0 EK-1 = 0 , GK-1 = 0 , LK-1 = 1



AK-1 … A1 A0 = BK-1 … B1 B0 EK-1 = 1 , GK-1 = 0 , LK-1 = 0

AK-1 … A1 A0 > BK-1 … B1 B0 EK-1 = 0 , GK-1 = 1 , LK-1 = 0

AK-1 … A1 A0 < BK-1 … B1 B0 EK-1 = 0 , GK-1 = 0 , LK-1 = 1

• Note that only one of EK-1, GK-1 or LK-1 may have value 1 at a time.



AK-1 … A1 A0 = BK-1 … B1 B0 EK-1 = 1 , GK-1 = 0 , LK-1 = 0

AK-1 … A1 A0 > BK-1 … B1 B0 EK-1 = 0 , GK-1 = 1 , LK-1 = 0

AK-1 … A1 A0 < BK-1 … B1 B0 EK-1 = 0 , GK-1 = 0 , LK-1 = 1

• Note that only one of EK-1, GK-1 or LK-1 may have value 1 at a time.

• Our goal is to derive expressions for outputs EK, GK and LK based on the inputs AK , BK , EK-1 , GK-1 and LK-1 .


• Construct an abbreviated truth-table:

AK BK EK-1 GK-1 LK-1 EK GK LK 0 0 0 0 1 0 0 10 0 0 1 0 0 1 00 0 1 0 0 1 0 00 1 0 0 1 0 0 10 1 0 1 0 0 0 10 1 1 0 0 0 0 11 0 0 0 1 0 1 01 0 0 1 0 0 1 01 0 1 0 0 0 1 01 1 0 0 1 0 0 11 1 0 1 0 0 1 01 1 1 0 0 1 0 0

• Note that all other (missing) rows are represented using don’t care output values.





Condition is not altered when

AK = BK

Condition is not altered when

AK = BK





Condition LK = 1 always applies

when AK < BK





Condition GK = 1 always applies

when AK > BK


• This leads to Boolean expressions for the outputs (using don’t cares):


GK = AK BK + AK GK-1 + BK GK-1

EK = AK BK EK-1 + AK BK EK-1

LK = AK BK + AK LK-1 + BK LK-1


• The 1-bit comparator circuit is expressed:

AK BK

GK

EK

LK

GK-1

EK-1

LK-1


• The 1- bit comparator circuit is expressed in MSI form:

AK BK

GK GK-1

EK EK-1

LK LK-1

1-bitComparator


• The 1- bit comparator circuit is expressed in MSI form:As with previous circuits, the 1-bit

comparator circuit can be extended to

form multi-bit, MSI ripple comparators.

AK BK

GK GK-1

EK EK-1

LK LK-1

1-bitComparator

AK-1 BK-1

GK-2

EK-2

LK-2

1-bitComparator

Summary - Part II

• We continue to study logic design in the contexts of Small Scale Integration (SSI) and Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD).

• We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design.

Adders Subtractors Comparator

• We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.)

SSI: Boolean algebra / Simplification / Logic gates

MSI: Interconnection networks / Iterative re-use / Components

Documents

Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part II