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– 1 –! CS:APP!
Alvin R. Lebeck!
Computer Science 104:!Y86 & Single Cycle Processor Design!
Slides based on those from Randy Bryant
– 2 –! CS:APP!
Administrative!Homework #4!My office hours today 11:30-12:30!Reading: text 4.3!
– 3 –! CS:APP!
Bit Equality!
n Generate 1 if a and b are equal!
Hardware Control Language (HCL)!n Very simple hardware description language!
l Boolean operations have syntax similar to C logical operations!n We’ll use it to describe control logic for processors!
Bit equal!a!
b!
eq!bool eq = (a&&b)||(!a&&!b)
HCL Expression!
– 4 –! CS:APP!
Word Equality!
n 32-bit word size!n HCL representation!
l Equality operation!l Generates Boolean value!
b31!Bit equal!
a31!
eq31!
b30!Bit equal!
a30!
eq30!
b1!Bit equal!
a1!
eq1!
b0!Bit equal!
a0!
eq0!
Eq!
=!B!
A!
Eq!
Word-Level Representation!
bool Eq = (A == B)
HCL Representation!
– 5 –! CS:APP!
Bit-Level Multiplexor!
n Control signal s!n Data signals a and b!n Output a when s=1, b when s=0!
Bit MUX!
b!
s!
a!
out!
bool out = (s&&a)||(!s&&b)
HCL Expression!
– 6 –! CS:APP!
Word Multiplexor!
n Select input word A or B depending on control signal s!
n HCL representation!l Case expression!l Series of test : value pairs!l Output value for first
successful test!
Word-Level Representation!
HCL Representation!
b31!
s!
a31!
out31!
b30!
a30!
out30!
b0!
a0!
out0!
int Out = [ s : A; 1 : B; ];
s!
B!
A!Out!MUX!
– 7 –! CS:APP!
HCL Word-Level Examples!
n Find minimum of three input words!
n HCL case expression!n Final case guarantees
match!A!
Min3!MIN3!B!C!
int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ];
D0!
D3!
Out4!
s0!s1!
MUX4!D2!D1!
n Select one of 4 inputs based on two control
bits!n HCL case expression!
n Simplify tests by assuming sequential
matching!
int Out4 = [ !s1&&!s0: D0; !s1 : D1; !s0 : D2; 1 : D3; ];
Minimum of 3 Words!
4-Way Multiplexor!
– 8 –! CS:APP!
Random-Access Memory!
n Stores multiple words of memory!l Address input specifies which word to read or write!
n Register file!l Holds values of program registers!l %eax, %esp, etc.!l Register identifier serves as address!
» ID 8 implies no read or write performed!n Multiple Ports!
l Can read and/or write multiple words in one cycle!» Each has separate address and data input/output!
Register!file!
A!
B!
W! dstW!
srcA!
valA!
srcB!
valB!
valW!
Read ports! Write port!
Clock!
– 9 –! CS:APP!
Register File Timing!Reading!
n Like combinational logic!n Output data generated based on
input address!l After some delay!
Writing!n Like register!n Update only as clock rises!
Register!file!
A!
B!
srcA!
valA!
srcB!
valB!
y!2!
Register!file!
W! dstW!
valW!
Clock!
x!2!Rising!clock!_ _ Register!
file!W! dstW!
valW!
Clock!
y!2!
x!2!
x!
2!
– 10 –! CS:APP!
Instruction Set Architecture!Assembly Language View!
n Processor state!l Registers, memory, …!
n Instructions!l addl, movl, leal, …!l How instructions are encoded
as bytes!
Layer of Abstraction!n Above: how to program machine!
l Processor executes instructions in a sequence!
n Below: what needs to be built!l Use variety of tricks to make it
run fast!l E.g., execute multiple
instructions simultaneously!
ISA!
Compiler! OS!
CPU!Design!
Circuit!Design!
Chip!Layout!
Application!Program!
– 11 –! CS:APP!
Y86: A simpler Instruction Set!IA32 has too many instructions!IA32 has too many quirks!Y86 subset of IA32 instructions!Y86 simpler enconding than IA32!Y86 easier to reason about!-> better for understanding hardware!
– 12 –! CS:APP!
%eax %ecx %edx %ebx
%esi %edi %esp %ebp
Y86 Processor State!
n Program Registers!l Same 8 as with IA32. Each 32 bits!
n Condition Codes!l Single-bit flags set by arithmetic or logical instructions!
» OF: Overflow !ZF: Zero !SF:Negative!n Program Counter!
l Indicates address of instruction!n Memory!
l Byte-addressable storage array!l Words stored in little-endian byte order!
Program registers! Condition
codes!
PC!
Memory!
OF ZF SF
– 13 –! CS:APP!
Y86 Instructions!Recall Memory is a Bunch of Bits!!How do we know if it is an instruction or not?!How do we know which instruction, which operands,
etc.!Format!
n 1--6 bytes of information read from memory!l Can determine instruction length from first byte!l Not as many instruction types, and simpler encoding than with
IA32!n Each accesses and modifies some part(s) of the program
state!
– 14 –! CS:APP!
Encoding Registers!Each register has 4-bit ID!
!!
n Same encoding as in IA32!
Register ID 8 indicates “no register”!n Will use this in our hardware design in multiple places!
%eax %ecx %edx %ebx
%esi %edi %esp %ebp
0 1 2 3
6 7 4 5
– 15 –! CS:APP!
Instruction Example!Addition Instruction!!!!
n Add value in register rA to that in register rB!l Store result in register rB!l Note that Y86 only allows addition to be applied to register data!
n Set condition codes based on result!n e.g., addl %eax,%esi Encoding: 60 06 n Two-byte encoding!
l First byte indicates instruction type!l Second byte gives source and destination registers!
addl rA, rB! 6 0 rA!rB!
Encoded Representation!
Generic Form!
– 16 –! CS:APP!
Arithmetic and Logical Operations!n Refer to generically as
“OPl”!n Encodings differ only by
“function code”!l Low-order 4 bytes in first
instruction word!n Set condition codes as
side effect!
addl rA, rB! 6 0 rA!rB!
subl rA, rB! 6 1 rA!rB!
andl rA, rB! 6 2 rA!rB!
xorl rA, rB! 6 3 rA!rB!
Add!
Subtract (rA from rB)!
And!
Exclusive-Or!
Instruction Code! Function Code!
– 17 –! CS:APP!
Move Operations!
n Like the IA32 movl instruction!n Simpler format for memory addresses!n Give different names to keep them distinct!
rrmovl rA, rB! 2 0 rA!rB! Register --> Register!
Immediate --> Register!irmovl V, rB! 3 0 8 rB! V!
Register --> Memory!rmmovl rA, D(rB)! 4 0 rA!rB! D!
Memory --> Register!mrmovl D(rB), rA 5 0 rA!rB! D!
– 18 –! CS:APP!
Move Instruction Examples!
irmovl $0xabcd, %edx !movl $0xabcd, %edx! 30 82 cd ab 00 00!IA32! Y86! Encoding!
rrmovl %esp, %ebx !movl %esp, %ebx! 20 43!
mrmovl -12(%ebp),%ecx movl -12(%ebp),%ecx! 50 15 f4 ff ff ff!
rmmovl %esi,0x41c(%esp) movl %esi,0x41c(%esp)!
!—!movl $0xabcd, (%eax)!
!—!movl %eax, 12(%eax,%edx)!
!—!movl (%ebp,%eax,4),%ecx!
40 64 1c 04 00 00!
– 19 –! CS:APP!
Jump Instructions!n Refer to generically as
“jXX”!n Encodings differ only by
“function code”!n Based on values of
condition codes!n Same as IA32 counterparts!n Encode full destination
address!l Unlike PC-relative
addressing seen in IA32!
jmp Dest! 7 0
Jump Unconditionally!
Dest!
jle Dest! 7 1
Jump When Less or Equal!
Dest!
jl Dest! 7 2
Jump When Less!
Dest!
je Dest! 7 3
Jump When Equal!
Dest!
jne Dest! 7 4
Jump When Not Equal!
Dest!
jge Dest! 7 5
Jump When Greater or Equal!
Dest!
jg Dest! 7 6
Jump When Greater!
Dest!
– 20 –! CS:APP!
Y86 Program Stack!n Region of memory holding
program data!n Used in Y86 (and IA32) for
supporting procedure calls!n Stack top indicated by %esp
l Address of top stack element!n Stack grows toward lower
addresses!l Top element is at highest
address in the stack!l When pushing, must first
decrement stack pointer!l When popping, increment stack
pointer!%esp
•
•
•
Increasing!Addresses!
Stack “Top”!
Stack “Bottom”!
– 21 –! CS:APP!
Stack Operations!
n Decrement %esp by 4!n Store word from rA to memory at %esp n Like IA32!
n Read word from memory at %esp n Save in rA!n Increment %esp by 4!n Like IA32!
pushl rA! a 0 rA! 8
popl rA! b 0 rA! 8
– 22 –! CS:APP!
Subroutine Call and Return!
n Push address of next instruction onto stack!n Start executing instructions at Dest!n Like IA32!
n Pop value from stack!n Use as address for next instruction!n Like IA32!
call Dest! 8 0 Dest!
ret! 9 0
– 23 –! CS:APP!
Miscellaneous Instructions!
n Don’t do anything!
n Stop executing instructions!n IA32 has comparable instruction, but can’t execute it in
user mode!
nop! 0 0
halt! 1 0
– 24 –! CS:APP!
Y86 Instruction Set!Byte! 0 1 2 3 4 5
pushl rA! A 0 rA! 8
jXX Dest! 7 fn! Dest!
popl rA! B 0 rA! 8
call Dest! 8 0 Dest!
rrmovl rA, rB! 2 0 rA! rB!
irmovl V, rB! 3 0 8 rB! V!
rmmovl rA, D(rB) 4 0 rA! rB! D!
mrmovl D(rB), rA! 5 0 rA! rB! D!
OPl rA, rB! 6 fn! rA! rB!
ret 9 0
nop 0 0
halt 1 0
addl 6 0
subl 6 1
andl 6 2
xorl 6 3
jmp 7 0
jle 7 1
jl 7 2
je 7 3
jne 7 4
jge 7 5
jg 7 6
– 25 –! CS:APP!
Building Blocks!Combinational Logic!
n Compute Boolean functions of inputs!
n Continuously respond to input changes!
n Operate on data and implement control!
!Storage Elements!
n Store bits!n Addressable memories!n Non-addressable registers!n Loaded only as clock rises!
Register!file!
A!
B!
W! dstW!
srcA!
valA!
srcB!
valB!
valW!
Clock!
A!L!U!
fun!
A!
B!
MUX!0!
1!
=!
Clock!
– 26 –! CS:APP!
SEQ Hardware Structure (Abstract)!State!
n Program counter register (PC)!n Condition code register (CC)!n Register File!n Memories!
l Access same memory space!l Data: for reading/writing program
data!l Instruction: for reading
instructions!
Instruction Flow!n Read instruction at address
specified by PC!n Process through stages!n Update program counter!
Instruction!memory!Instruction!memory! PC!
increment!PC!increment!
CC!CC!ALU!ALU!
Data!memory!Data!memory!
Fetch!
Decode!
Execute!
Memory!
Write back!
icode!, !ifun!rA! , !rB!
valC!
Register!file!Register!file!
A! B!M!E!
Register!file!Register!file!
A! B!M!E!
PC!
valP!
srcA!, !srcB!dstA!, !dstB!
valA!, !valB!
aluA!, !aluB!Bch!
valE!
Addr!, Data!
valM!
PC!valE!, !valM!
newPC!
– 27 –! CS:APP!
SEQ Stages!Fetch!
n Read instruction from instruction memory!
n If PC points to it, we view it as instruction!
Decode!n Read program registers!
Execute!n Compute value or address!
Memory!n Read or write data!
Write Back!n Write program registers!
PC!n Update program counter!
Instruction!memory!Instruction!memory! PC!
increment!PC!increment!
CC!CC!ALU!ALU!
Data!memory!Data!memory!
Fetch!
Decode!
Execute!
Memory!
Write back!
icode!, !ifun!rA! , !rB!
valC!
Register!file!Register!file!
A! B!M!E!
Register!file!Register!file!
A! B!M!E!
PC!
valP!
srcA!, !srcB!dstA!, !dstB!
valA!, !valB!
aluA!, !aluB!Bch!
valE!
Addr!, Data!
valM!
PC!valE!, !valM!
newPC!
– 28 –! CS:APP!
Instruction Decoding!
Instruction Format!n Instruction byte !icode:ifun!n Optional register byte !rA:rB!n Optional constant word !valC!
5 0 rA! rB! D!
icode!ifun!
rA!rB!
valC!
Optional! Optional!
– 29 –! CS:APP!
Executing Arith./Logical Operation!
Fetch!n Read 2 bytes!
Decode!n Read operand registers!
Execute!n Perform operation!n Set condition codes!
Memory!n Do nothing!
Write back!n Update register!
PC Update!n Increment PC by 2!
OPl rA, rB! 6 fn! rA!rB!
– 30 –! CS:APP!
Stage Computation: Arith/Log. Ops!
n Formulate instruction execution as sequence of simple steps!
n Use same general form for all instructions; often called Register Transfer Language (RTL)!
OPl rA, rB!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]! !valP ← PC+2!
Fetch!
Read instruction byte!Read register byte! !Compute next PC!
valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB OP valA!Set CC!
Execute!Perform ALU operation!Set condition code register!
!Memory! !R[rB] ← valE! !
Write!back!
Write back result! !
PC ← valP!PC update! Update PC!
– 31 –! CS:APP!
Executing rmmovl
Fetch!n Read 6 bytes!
Decode!n Read operand registers!
Execute!n Compute effective address!
Memory!n Write to memory!
Write back!n Do nothing!
PC Update!n Increment PC by 6!
rmmovl rA, D(rB)! 4 0 rA!rB! D!
– 32 –! CS:APP!
Stage Computation: rmmovl
n Use ALU for address computation!
rmmovl rA, D(rB)!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]!valC ← M4[PC+2]!valP ← PC+6!
Fetch!
Read instruction byte!Read register byte!Read displacement D!Compute next PC!
valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB + valC!Execute!
Compute effective address!
M4[valE] ← valA!Memory! Write value to memory !
!Write!back! !
PC ← valP!PC update! Update PC!
– 33 –! CS:APP!
Executing popl
Fetch!n Read 2 bytes!
Decode!n Read stack pointer!
Execute!n Increment stack pointer by 4!
Memory!n Read from old stack pointer!
Write back!n Update stack pointer!n Write result to register!
PC Update!n Increment PC by 2!
popl rA! b 0 rA! 8
– 34 –! CS:APP!
Stage Computation: popl
n Use ALU to increment stack pointer!n Must update two registers!
l Popped value!l New stack pointer!
popl rA!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]! !valP ← PC+2!
Fetch!
Read instruction byte!Read register byte! !Compute next PC!
valA ← R[%esp]!valB ← R [%esp]!
Decode!Read stack pointer!Read stack pointer!
valE ← valB + 4!Execute!
Increment stack pointer!
valM ← M4[valA]!Memory! Read from stack !R[%esp] ← valE!R[rA] ← valM!
Write!back!
Update stack pointer!Write back result!
PC ← valP!PC update! Update PC!
– 35 –! CS:APP!
Executing Jumps!
Fetch!n Read 5 bytes!n Increment PC by 5!
Decode!n Do nothing!
Execute!n Determine whether to take
branch based on jump condition and condition codes!
Memory!n Do nothing!
Write back!n Do nothing!
PC Update!n Set PC to Dest if branch
taken or to incremented PC if not branch!
jXX Dest! 7 fn! Dest!
XX XX fall thru:!
XX XX target:!
Not taken!
Taken!
– 36 –! CS:APP!
Stage Computation: Jumps!
n Compute both addresses!n Choose based on setting of condition codes and branch
condition!
jXX Dest!icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
Fetch!
Read instruction byte!
Read destination address!Fall through address!
Decode!
Bch ← Cond(CC,ifun)!Execute!
Take branch?! !Memory! !
!Write!back! !
PC ← Bch ? valC : valP!PC update! Update PC!
– 37 –! CS:APP!
Executing call
Fetch!n Read 5 bytes!n Increment PC by 5!
Decode!n Read stack pointer!
Execute!n Decrement stack pointer by
4!
Memory!n Write incremented PC to
new value of stack pointer!
Write back!n Update stack pointer!
PC Update!n Set PC to Dest!
call Dest! 8 0 Dest!
XX XX return:!
XX XX target:!
– 38 –! CS:APP!
Stage Computation: call
n Use ALU to decrement stack pointer!n Store incremented PC!
call Dest!icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
Fetch!
Read instruction byte!
Read destination address !Compute return point!
valB ← R[%esp]!Decode!
Read stack pointer!valE ← valB + –4!
Execute!Decrement stack pointer!
M4[valE] ← valP !Memory! Write return value on stack !R[%esp] ← valE! !
Write!back!
Update stack pointer! !
PC ← valC!PC update! Set PC to destination!
– 39 –! CS:APP!
Executing ret
Fetch!n Read 1 byte!
Decode!n Read stack pointer!
Execute!n Increment stack pointer by 4!
Memory!n Read return address from
old stack pointer!
Write back!n Update stack pointer!
PC Update!n Set PC to return address!
ret! 9 0
XX XX return:!
– 40 –! CS:APP!
Stage Computation: ret
n Use ALU to increment stack pointer!n Read return address from memory!
ret
icode:ifun ← M1[PC]!
!Fetch!
Read instruction byte!
!
valA ← R[%esp]!valB ← R[%esp]!
Decode!Read operand stack pointer!Read operand stack pointer!
valE ← valB + 4!Execute!
Increment stack pointer!
valM ← M4[valA] !Memory! Read return address!R[%esp] ← valE! !
Write!back!
Update stack pointer! !
PC ← valM!PC update! Set PC to return address!
– 41 –! CS:APP!
Computation Steps!
n All instructions follow same general pattern!n Differ in what gets computed on each step!
OPl rA, rB!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]! !valP ← PC+2!
Fetch!
Read instruction byte!Read register byte![Read constant word]!Compute next PC!
valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB OP valA!Set CC!
Execute!Perform ALU operation!Set condition code register!
!Memory! [Memory read/write] !R[rB] ← valE! !
Write!back!
Write back ALU result![Write back memory result] !
PC ← valP!PC update! Update PC!
icode,ifun!rA,rB!valC!valP!valA, srcA!valB, srcB!valE!Cond code!valM!dstE!dstM!PC!
– 42 –! CS:APP!
Computation Steps!
n All instructions follow same general pattern!n Differ in what gets computed on each step!
call Dest!
Fetch!
Decode!
Execute!
Memory!Write!back!PC update!
icode,ifun!rA,rB!valC!valP!valA, srcA!valB, srcB!valE!Cond code!valM!dstE!dstM!PC!
icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
valB ← R[%esp]!valE ← valB + –4!
M4[valE] ← valP !R[%esp] ← valE! !PC ← valC!
Read instruction byte![Read register byte]!Read constant word!Compute next PC![Read operand A]!Read operand B!Perform ALU operation![Set condition code reg.]![Memory read/write] ![Write back ALU result]!Write back memory result!Update PC!
– 43 –! CS:APP!
Computed Values!Fetch!
icode !Instruction code!ifun !Instruction function!rA !Instr. Register A!rB !Instr. Register B!valC !Instruction constant!valP !Incremented PC!
Decode!srcA !Register ID A!srcB !Register ID B!dstE !Destination Register E!dstM !Destination Register M!valA !Register value A!valB !Register value B!!
Execute!n valE !ALU result!n Bch !Branch flag!
Memory !!n valM !Value from
memory!
– 44 –! CS:APP!
Summary!Y86: a simpler instruction set than IA32!Data path: the hardware structure (connections) of
components and flow of data between and through these components to implement the various instructions. Specifically the fetch/execute cycle.!
!Next Time:!!Control for the data path!
