ISRN KTH/IMIT/LECS/AVH-05/09-SE

Concurrent Chip and Package Design for Radio and Mixed-Signal Systems

Meigen Shen Stockholm 2005

Doctoral Thesis

KTH, Royal Institute of Technology Department of Microelectronics and Information Technology

Laboratory of Electronics and Computer Systems

Concurrent Chip and Package Design for Radio and Mixed-

Signal Systems A dissertation submitted to KTH, Royal Institute of Technology, Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Doctor of Technology. ISBN 91-7178-181-1 ISRN KTH/IMIT/LECS/AVH-05/09-SE ISSN 1651-4076 TRITA-IMIT-LECS AVH 05:09

2005 Meigen Shen KTH, Royal Institute of Technology Department of Microelectronics and Information Technology Laboratory of Electronics and Computer Systems Electrum 229 SE-16440 Kista, Stockholm Sweden

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Abstract The advances in VLSI and packaging technologies enable us to integrate a whole

system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

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ACKNOWLEDGEMENTS

First of all I would like to express my gratitude to my supervisors, Docent Li-Rong Zheng and professor Hannu Tenhunen, for providing me the opportunity of doing research in a very interesting and challenging area. Li-Rong provided excellent guidance, largely contributed to the ideas and warmly helped me during the course of this work so that I eventually finished my studies and doctoral thesis. Hannu provided me with his trust and constant support during the course of this work and the creative research environment the author appreciated very much.

Many thanks are to Duo Xinzhong, Wim Michielsen, Jian Liu, Roshan Weerasekera, Bingxin Li, Li Li, Dinesh Pamunuwa, Steffen Albrecht, Yutai Ma, Zhonghai Lu, Yiran Sun, Jinliang Huang, Saul Rodriguez Duenas, and all other colleagues in LECS, Wei Liu in SSD, for their collaborations, discussions, friendship, and/or all kinds of help. It’s really a great pleasure to work with all of you.

Also many thanks are to Hans Berggren, Julio Mercado, and Richard Andersson, for keeping the computers in good shapes, and Lena Beronius for their excellent administrative work done for the author in the beginning and later on, respectively.

The author would like to thank to nice persons Tero Koivisto, Teemu Peltonen, Esa Tjukanoff, and Jouni Isoaho in University of Turku, Finland. The discussions with them broaden my knowledge and stimulate new idea. Special thanks to Esa Tjukanoff for his helpful comments to the thesis draft.

Many thanks also to my friends in SoC International Master Program and in China, for their friendship, discussions and support.

Financial support from Swedish National Foundation for Strategic Research (SSF) through the EPROPER graduate school is gratefully acknowledged. Special thanks are given to Kåre Gustafsson (Ericsson), and Dag Andersson (IVF) for their excellent work in managing the EPROPER program and the graduate school. All partners and colleagues in EPROPER are acknowledged for their collaborations, discussions, or assistance.

Last but not least, I would like to express my deepest gratitude to my family. Without their understanding, love and constant support, this thesis cannot be completed.

Meigen Shen Stockholm, 2005

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LIST OF PUBLICATIONS Papers included in this thesis: 1. Meigen Shen, L. –R. Zheng, and H. Tenhunen, “Cost and Performance Analysis

for Mixed-Signal Implementation: System on Chip or System on Package?” IEEE Trans. on Electronics Packaging Manufacturing, pp. 262-272, Vol.25, No.4, Oct. 2002

2. L. –R. Zheng, Xinzhong Duo, Meigen Shen, Wim Michielsen, and H. Tenhunen, “Cost and Performance Trade-off Analysis in Radio and Mixed-Signal System-on-Package Design” IEEE Trans. on Advanced Packaging, pp.364-375, Vol.27, No.2, May 2004 (Invited Paper)

3. Meigen Shen, L. –R Zheng, and H. Tenhunen, “Cost-Performance Driven Mixed-Signal System Partitioning: A Case Study on SDH/SONET OAN Interface” In Proc. of the 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP-04), pp. 37-41, Shanghai, China, June 30 - July 3, 2004.

4. Meigen Shen, Jian Liu, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, “Robustness Enhancement through Chip-Package Co-design for High-Speed Electronics” Microelectronics Journal, pp.846-855, Vol.36, Issue 9, Sept. 2005

5. Meigen Shen, L. –R. Zheng, Esa Tjukanoff, Jouni Isoaho, and H. Tenhunen, “Concurrent Chip-Package Design for 10GHz Global Clock Distribution” The 55th Electronic Components and Technology Conference, (ECTC-05), pp.1554-1559, Lake Buena Vista, Florida, USA, May 31- June 3, 2005,

6. Meigen Shen, Tero Koivisto, Teemu Peltonen, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, “UWB Radio Module Design for Wireless Intelligent Systems- from Specification to Implementation” to appear in IEEE Trans. on Electronics Packaging Manufacturing, 2006

Other publications: 7. Meigen Shen, Tero Koivisto, Teemu Peltonen, L. -R. Zheng, Esa Tjukanoff, and

H. Tenhunen, “UWB Radio Module Design for Wireless Sensor Networks,” In Proc. the 23rd Norchip Conference (NORCHIP-05), Nov. 21-22, 2005, Oulu, Finland

8. Meigen Shen, Tero Koivisto, Teemu Peltonen, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, “UWB Transceiver Circuits Design for WPAN Applications,”

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International Symposium on Signals, Circuits & Systems (ISSCS-05), pp.255-258, July 14-15, 2005, Iasl, Romania

9. Meigen Shen, Tero Koivisto, Teemu Peltonen, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, “UWB Radio Module Design for Wireless Intelligent Systems-from Specifications to Implements,” In Proc. of the 7th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP-05), pp.353-359, June 30 - July 3, 2005, Shanghai, China

10. Teemu Peltonen, Meigen Shen, Tero Koivisto, Xinzhong Duo, Esa Tjukanoff, L. -R. Zheng, and H. Tenhunen, “A 0.18um CMOS Ultra Wideband Low-Noise Amplifier with High IIP3,” In Proc. of the 7th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP-05), pp.452-454, June 30 - July 3, 2005, Shanghai, China

11. Meigen Shen, L. -R. Zheng, Esa Tjukanoff, Jouni Isoaho, and H. Tenhunen, “Case Study of Interconnect Analysis for Standing Wave Oscillator Design,” The 2005 International Symposium on Circuits and Systems (ISCAS-05), pp.456-459, May 23-26, 2005, Kobe, Japan

12. Meigen Shen, L. -R. Zheng, Esa Tjukanoff, Jouni Isoaho, and H. Tenhunen, “Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach,” The 6th International Symposium on Quality Electronic Design, (ISQED-05), pp.573-578, March 21-23, 2005, San Jose, CA, USA

13. L. -R. Zheng, Meigen Shen, Xinzhong Duo, and H. Tenhunen, “Embedded Smart Systems for Intelligent Paper and Packaging,” The 55th Electronic Components and Technology Conference, (ECTC-05), pp.1776-1782, May 31- June 3, 2005, Lake Buena Vista, Florida, USA

14. Meigen Shen, Jian Liu, L. -R Zheng, and H. Tenhunen, “Chip-package co-design for high performance and reliability off-chip communications,” In Proc. of the 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP-04), pp. 31-36, June 30 - July 3, 2004, Shanghai, China

15. L. -R Zheng, Xingzhong Duo, Meigen Shen, T. Torrika, W. Michielsen, H. Tenhunen, Liu Chen, Gang Zou, and Johan Liu, “Design and Implementation of system-on-package for radio and mixed-signal applications,” In Proc. of the 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP-04), pp. 97-104, June 30 - July 3, 2004, Shanghai, China

16. W. Michielsen, Meigen Shen, L. -R Zheng, and H. Tenhunen, “Performance and Cost Estimations of Packaged Single Band Voltage Controlled Oscillators,” In

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Proc. of the 6th IEEE Circuit and System Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication,” pp.53-56, May 31 - June 2, 2004, Shanghai, China

17. Meigen Shen, L. -R. Zheng, and H. Tenhunen, “Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics,” The 5th International Symposium on Quality Electronic Design, (ISQED-04), pp.184-189, March 22-24, 2004, San Jose, USA (Best Paper Award)

18. L. R. Zheng, D. Xinzhong, W. Michielsen, M. Shen, and H. Tenhunen, “Radio and Mixed-Signal System-on-Package Platforms for Short-Range Wireless Communications”, invited paper to Asia Green Electronics Conference, January 2004, Hong-Kong, China

19. Meigen Shen, L. -R Zheng, and H. Tenhunen, “Interconnection-aware transmitter design for high-speed off-chip communications,” In Proc. the 21st Norchip Conference (NORCHIP-03), pp.121-124, Nov. 10-11, 2003, Riga, Latvia

20. Meigen Shen, Jian Liu, L. -R. Zheng, and H. Tenhunen, “Chip-Package Co-Design for High-Speed Transmitter in Serial Links Application,” In Proc. Electrical Performance of Electrical Package (EPEP-03), pp.217-220, October 27-29, 2003, Princeton, New Jersey, USA

21. Meigen Shen, L. -R. Zheng, and H. Tenhunen, “Case Study of Cost and Performance Trade-off Analysis for Mixed-Signal Integration in System-on-Chip,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS-03), pp.585-588, May 25-28, 2003, Bangkok, Thailand

22. J. Liu, Meigen Shen, L. -R. Zheng, and H. Tenhunen, “System Level Interconnect Design for Network-on-chip Using Interconnect IPs,” in Proc. IEEE System Level Interconnect Prediction (SLIP-03), pp.117-124, April 2003, Monterey, California, USA

23. Meigen Shen, R. Ashraf, L.-R. Zheng, and H. Tenhunen, “Chip-Package-System Co-Design of an Optical Access Network Interface in System-on-Package,” The 4th Pori Electronics Production and Packaging Technology Conference, pp. 94-100, May 22-23, 2003, Pori, Finland

24. L.-R. Zheng, Meigen Shen, and H. Tenhunen, “System-on-Chip or System-on-Package: Can We Make an Accurate Decision on System Implementation in an Early Design Phase?” In 2003 Southwest Symposium on Mixed-Signal Design (SSMSD-03), pp.1-4, Feb.23-25, 2003, Las Vegas, USA

25. Meigen Shen, L. -R. Zheng, and H. Tenhunen, “Cost and performance analysis for mixed signal implementations: System-on-chip or system-on-packaging?” In

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Proc. IEEE Conference on High Density Packaging and Component Failure Analysis (HDP-02), pp. 197-203, July 1-2, 2002, Shanghai, China

26. Meigen Shen, L. -R. Zheng, and H. Tenhunen, “Early Estimation of Cost and Performance for Mixed Signal Integration in System-on-chip,” In Proc. IEEE 20th Norchip Conference (NORCHIP-02), pp. 278-284, Nov. 11-12, 2002, Copenhagen, Denmark

27. Meigen Shen, L. -R. Zheng, and H. Tenhunen, “Design and implementation of a byte synchronous mapping device for optical SDH/SONET access network,” In Proc. IEEE 19th Norchip Conference (NORCHIP-01), pp. 131-136, Nov.12-13, 2001, Kista, Stockholm, Sweden

Non-Reviewed Presentations and Technical Reports:

28. Meigen Shen, “Concurrent Packaging and VLSI Design for High-Frequency Circuits and systems”, Eproper graduate school seminar, Stockholm, Sweden, Nov. 2001

29. Meigen Shen, “Signal Integrity Issues in High-Speed Digital Systems,” presentation in Mydata AB, Stockholm, Sweden, June 2002

30. Meigen Shen, “Trends and Frontiers: High-Speed Serial Links for Off-Chip Communications,” Eproper graduate school seminar, Berlin, Germany, May, 2003

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CONTENTS

Acknowledgements ............................................................................................................. iii List of Publications.............................................................................................................. iv Contents .............................................................................................................................. viii List of Abbreviations............................................................................................................ x

1. Introduction...................................................................... 1 1.Thesis Background .........................................................................................................1 2. Problem Description.....................................................................................................1

2.1. Radio and Mixed-Signal System Implementation: System-on-Chip versus System-on-Package?.........................................................................................2

2.2. Package - A Part of Chip Design.........................................................................2 3. Research Overview........................................................................................................3

2. System-on-Package: Challenges and Opportunities ......5 1. Microelectronic Technology Evolutions ...................................................................5

1.1. System-on-Chip ......................................................................................................5 1.2. System-on-Package.................................................................................................6

2. System-on-Package: A New Opportunity for Integrated Systems........................8 3. System-on-Package Design Challenges......................................................................9

3.1. Mixed-Hardware and Mixed-Signal Challenges ..............................................10 3.2. Mixed Design Tools Challenges ........................................................................11 3.3. Mixed Frequency Challenges: Digital Enters Microwave Spectrum............11

4. System-on-Package Technology Challenges ...........................................................12 4.1. Low Parasitic First-Level Interconnections.....................................................12 4.2. Power Dissipation and Thermal Removal .......................................................13 4.3. High Density Interconnect Substrates..............................................................14 4.4. Other Challenges ..................................................................................................15

3. Concurrent Chip and Package Design .......................... 17 1. Why Chip and Package Need Concurrent Design?...............................................17 2. Coherent Mixed-Signal System Partitioning ...........................................................18

2.1. New Issues for Mixed-Signal System Partitioning..........................................19 2.2. Cost-Performance Driven Mixed-Signal System Partitioning ......................20 2.3. On-Chip versus Off-chip Passive Components Trade-Offs Analysis ........20

3. Circuit and Physical Level Design Issues ................................................................21 3.1. Modeling, Analysis and Design of Power Distribution Systems..................21 3.2. Concurrent Chip and Package Design for Signal Distribution ....................23 3.3. Concurrent Chip and Package Design for Clock Distribution Networks..28 3.4. Design Platform for Concurrent Chip and Package Design.........................29

4. Concurrent Design of a UWB Radio Module............... 31 1. UWB Overview............................................................................................................31

1.1. Impulse-based UWB System Architecture.......................................................32 1.2. Multi-band OFDM-based UWB Architecture ................................................33 1.3. Physical Layer Design Challenges for UWB....................................................34

2. Optimal Pulse-shaper for Impulse-based UWB.....................................................37 3. UWB Link Budget for Wireless Intelligent Systems..............................................38

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4. Concurrent Design Considerations for a UWB Radio Module .........................41 5. Summary of Papers ........................................................ 44

1. Summary of Included Papers ....................................................................................44 2. Author’s Contribution................................................................................................46

6. Thesis Summary and Future Works.............................. 47 1. Thesis Summary ..........................................................................................................47 2. Future Works...............................................................................................................48

7. Bibliography.................................................................. 49

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LIST OF ABBREVIATIONS 2D, 2.5D, 3D two-dimensional, 2.5 dimensional, three dimensional ASIC application specific integrated circuits BGA ball grid array BPSK binary phase shift key CAD computer aided design CPU central processing unit CMOS complementary metal-oxide-semiconductor CSP chip scale package DIP dual in package DSM deep submicron DS-UWB direct sequence ultra wideband EM electromagnetic EMC/EMI electromagnetic compatibility/interference FCC Federal Communications Commission FIR finite impulse response HFSS high frequency structure simulator, a 3D FEM field solver

of Hewlett Packard (now Agilent Technologies) H.P., H.H. high performance, hand-hold products I/O input/output IC integrated circuits IEEE Institute of Electrical and Electronics Engineers IP intellectual property ISI Inter-symbol interference ITRS, NTRS International (National) Technology Roadmap for

Semiconductors KTH Royal Institute of Technology, Sweden LCP liquid-crystal-polymer LRC inductive-resistive-capacitive LNA low noise amplifier MCM multi-chip-module MEMS micro-electro-mechanical-system MTL multi-conductor transmission line MB-OFDM multi band orthogonal frequency division multiplexing PAM pulse amplitude modulation PCB, PWB printed circuit/wire board PGA pin grid array

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PLCC plastic leaded chip carrier QFP quarter flat package RC resistive-capacitive RF radio frequency RFID radio frequency identification SIA Semiconductor Industrial Association SiP, SoP system-in-package, system-on-package SNR signal noise ratio SoC, SOC system-on-chip SsoC subsystem-on-chip S-parameters scattering parameters SSN simultaneously switching noise TAB tape automated bonding UWB ultra wideband VLSI/ULSI very/ultra large scale integration µp microprocessor WLAN wireless local area networking WPAN wireless personal area network WSN wireless sensor network

1. Introduction

1.Thesis Background

Deep submicron (DSM) technology is rapidly leading to exceedingly complex, billion-transistor chips. This has resulted in system-on-chip (SoC) that integrates a variety of functions including logic, memory, and analog/RF on a single silicon chip. In parallel with this trend, new packaging technologies have emerged in response to the demand for portability, low cost, high speed, and mixed-signal applications, making system-on-package (SoP) feasible. SoC and SoP, which are integrated radio and mixed-signal systems, are recognized as two major circuit paradigms of future microelectronic systems. As now system designers face more options for their system implementations, it is important to make a correct decision, particular in early design phase, in which technology (SoC, SoP, or SoP with Subsystem-on-Chip (SSoC)) the system can be optimally implemented. This is because in a system design process, around 80% of product cost is committed by the decisions within the first 20% design cycle or in the conceptual-level design phase [Sandb94]. Accurate models, which address cost and performance issues earlier in a design process, are therefore vital in a system design. While performance of device further improves, the package starts to be the bottleneck of the overall system performance. A low interaction between integrated chip (IC) and package will more and more limit the system potentials. Hence, concurrent chip and package design approaches are attractive solutions for new challenges in high-speed digital system design such as clock distribution, power distribution, signal distribution, signal integrity control and radio systems design such as impedance matching, filter design, high quality factor inductor design. In this thesis, three major issues in radio and mixed-signal systems are presented:

• Cost and performance driven radio and mixed-signal partitioning for system-on-chip versus system-on-package

• Concurrent chip-package design methodology for high-speed off-chip signaling and global clock distribution in deep submicron (DSM) very large scale integration (VLSI) circuits

• Concurrent chip-package design methodology for ultra wideband (UWB) modules design in system-on-package

2. Problem Description

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2.1. Radio and Mixed-Signal System Implementation: System-on-Chip versus System-on-Package?

Owing to largely intellectual property (IP) core and inexpensive CMOS technology, SoC solutions are highly desirable not only in digital application, but also in mixed-signal system [Kolli03] and wireless applications especially in Bluetooth [Ishik03], IEEE802.11a [Shi02], IEEE 802.11b and HiperLAN. However, integrating a mixed-signal heterogeneous system on a single chip means extra cost for noise isolation and technology fusion. As a result, for many radio and mixed-signal systems, a single chip solution is not necessary better. Therefore, when a designer selects in which technology the system should be implemented, the costs of mixed-signal isolation as well as the cost for technology fusion must be estimated, and the resulting system performance must be accurately evaluated. These issues were addressed currently by generic and relatively crude estimations. As the system complexity rises, such crude analysis becomes inadequate, and better approach must be developed.

The key challenges of earlier cost and performance estimation for mixed-signal system implementation include: (1) lack of physical layout information since the design process just starts, and (2) lack of accurate and efficient models since most of the systems are inherently complex which may be extremely memory and CPU consuming in a full simulation.

In order to perform early estimation of cost and performance, it is clear that a new design flow, which can avoid the above difficulties, must be defined. New models and algorithms that will enable the new design flow must be developed.

2.2. Package - A Part of Chip Design As the technology advances towards ultra deep in submicron generations, density

and performance of individual chips are continually enhanced. Unfortunately, today, not all of these merits can be translated into system level due to the problem of electronic package, which has presented a bottleneck for increasing system speed, reducing power, and shrinking system size.

When chip speed is higher than several hundred MHz, the package exhibits very large parasitic effects. For example, in today's VLSI chips, the chip I/O pads are still quite large that requires very large buffers and off-chip drivers for off-chip communications. In addition, the package itself and on-board interconnects have much larger dimensions than that of the on-chips. They are hence large loads of off-chip drivers. Besides the higher power consumption and larger chip size for these off-chip drivers, system performance is severely degraded. This we can see for example from the fact that leading microprocessors, Intel Pentium 4 processor, the internal clock is 2.6 GHz in 0.18µm CMOS technology, whereas external bus speed is only 133MHz or 400MHz. Even worse, with operating frequencies further increase and signal rise time

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shorter than two and a half times the time-of-flight, transmission line effects become significant. Consequently, preservation of signal integrity and timing becomes a difficult challenge as signals move from chip to chip within the system. It is hence necessary to minimize impedance discontinuities at chip-to-package and package-to-board interconnection junctions and reduce cross-talk noise between adjacent lines.

In addition to high-speed digital systems, package also plays an important role in wireless communication systems. The main hurdles in using CMOS for RF applications are the absence of high quality on-chip passive. The advent of flip chip technology provides smaller parasitic inductance compared to traditional bond wire, which allows for integration of RF circuits at the package level using off-chip passive in the substrate, leading to a shift in design strategy resulting in a system on a package design approach.

Hence, the demand for better electrical performance at high frequency combined with higher integration density really need concurrent chip and package design. Hence, concurrent chip and package design methodology and CAD tools should be present for optimized system-level performance, better design accuracy, and a reduced number of design iterations. In addition to electrical co-design, thermal co-design and cost analysis should ideally also be included for co-optimization, which unfortunately does not exist so far.

3. Research Overview

Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first presented in this thesis. We develop a modeling technique for a prior cost and performance estimations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitries, using special substrate materials (e.g. silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in the second part of this thesis. First we explored interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitic are setup and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of the package. After that, bandwidth and noise of the signal channels are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. By using multi-level current mode differential signaling, and transmitter equalization, better performance and

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higher robustness are achieved under interconnect performance constraints. We also analyzed global power, signal, and clock distribution using concurrent design method in this part.

In third part, we developed a low cost, low power, and low complexity UWB radio module using concurrent design method and System-on-Package technologies. The UWB radio module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification and wireless sensor networks. The operation frequency of the UWB radio module is 3.1-5GHz and it is designed with 0.18um, 1.8V CMOS technology. The scalable and parameterized models of package, interconnect, and embedded passive elements are addressed and these models are used as the RFIC design parameters. The ultimate research goal is to implement the UWB radio module in a liquid-crystal-polymer-based SoP technology

2. System-on-Package: Challenges and Opportunities

1. Microelectronic Technology Evolutions

1.1. System-on-Chip

Figure 2-1 Evolution of microelectronic technology [ITRS03] that has so far followed Moore’s law very well. For the future, there are different extrapolations, depending upon assumptions on the development of the process technology. Also shown in the figure are the rapid development of process technologies and the size of the silicon wafers

In the beginning of the 1965’s, shortly after the invention of the IC, Gordon Moore, director of research and development at Fairchild Semiconductor, formulated an empirical law stating that the performance of an IC, including the number of components on it, doubles every 18-24 months with the same chip price. This was later called the Moore’s law. Remarkably enough, it is still holding up after nearly forty years, and this trend is likely continuing, as shown in Figure 2-1. It is projected that Moor’s law will continue for the next 10 years. According to this, in 2011, we will be able to integrate a chip with 3 Giga transistors on a chip (microprocessor). With exponentially increasing the number of transistors in a signal chip, rapidly increasing third party and internal intellectual property (IP) modules, where IP refers to a pre-designed behavioral or physical descriptions of a standard component and also by using advanced process technologies, the whole system can be integrated in a signal chip.

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SoC will be the final destination of IC integration. It can potentially encompass heterogeneous technologies through system integration. That means SoC can integrate analog/RF electronics, digital circuitries, and memories in a signal chip. Hence it is recognized as the new paradigms of future integrated electronic systems. Nowadays SoC solutions are highly desirable, particularly in low cost wireless applications. Figure 2-2 is an example of SoC for Buletooth application [Ishik03]. Individual chips such as microprocessor, memory, RF circuits that previously were integrated on a multi-chip module or printed circuit board (PCB), now can be integrated in one single chip.

Figure 2-2 A single-chip CMOS Bluetooth transceiver integrated full radio and baseband functions. The right is the die micrograph. The die size is 29.6 mm2 including I/O buffers and bonding pads. The digital baseband part and analog radio part occupy 16.6mm2 and 5.9mm2, respectively [Ishik03].

1.2. System-on-Package Packaging always plays an important role in electronic product manufacturing at

component and board levels. In the early days, however, the role of packaging was primarily structural. Now, packaging is increasingly important in the product’s function and performance. More and more advanced packaging technologies are used in electronic systems such as wafer-level packaging, chip scale packaging and multi chip packaging. System-on-package (SoP), a convergent microsystem integrated on an interconnect microboard. It is also a platform-based system, including hardware (digital, analogy/RF, MEMS) and embedded software, bases on advanced packaging and assembly technologies. SoP is also a multi-chip module (MCM), but it is a system-level integrated MCM, with increased system complexity. In addition, SoP may use more advanced packaging technologies than today’s MCM; For example, it may have

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integrated passive components in the package substrate, utilize fine pitch flip-chip instead of bonding wires or even use single-level integration [Zheng00], Therefore, the difference between MCM and SoP is somewhat like between VLSI and SoC.

A: The electronic packaging evolution

Figure 2-3 Evolution of electronic packaging technologies from early day’s DIP, PGA to today’s FCMCM, 3D package, MCM and SoP

According to the classic textbook [Brown99], electronic packaging must provide for signal distribution, heat dissipation, power distribution and circuit support and protection. The trends for electronic packaging have already been consistent with these ICs roadmap and it is higher density, higher reliability, and higher performance. As shown in Figure 2-3 packaging technologies have progressed considerably, from dual in line package (DIP), pin grid array (PGA) in the 1970s, plastic leaded chip carrier (PLCC), quarter flat package (QFP) in the 1980s, ball grid array (BGA) in the 1990s to the chip scale package (CSP) in the 2000s [Tumma99]. Nowadays, flip-chip BGA, flip-chip MCM and 3-dimension stack package are widely used in order to further increase integration level of system and decrease load of external signals. It also makes system smaller, thinner, lighter and with more functionality, higher performance, lower cost and low power consumption.

B: From MCM to SoP The simplest definition of a multi-chip module (MCM) is that of a single electronic

package containing more than one IC. Based on this simple definition, an MCM combines high performance ICs with a custom-designed common substrate structure,

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which provides mechanical support for the chips and multiple layers of conductors to interconnect them. A typical example is the core module in IBM S/390 servers [Ktata00]. It consists of 12 microprocessor chips, 12 level-2 cache chips, 2 DMA control chips and 8 bus-switching-network chips. The total package size is 127mm×127mm.

SoP relates to the objective of merging many or all of the electronic requirements of a functional system or subsystems into one package. It is microminiaturized system-level board with two or more embedded RF, digital, analog and optical functions. SoP optimizes IC and package integration for cost, performance, size and reliability. Some characteristics of SoP are [Scanl00]:

• Different die technologies such as GaAs, SiGe, or Si and functions such as logic, memory, RF, analog or digital can be assembled in the same package to achieve specific thermal, electrical and mechanical performance;

• SoP includes chip-level interconnect technology. In other words, flip chip, wirebond, TAB, or other interconnections can be used for connect directly to an IC chip;

• Quite often, it includes passive components. The passives can be either surface mounted discrete components or in more advanced technologies, can be embedded into or manufactured on the substrate material;

• It may include other components necessary to bring the SoP to a more complete functional system or subsystem level – such as housings, lids, RF shields, connectors, antennas, batteries, etc.

2. System-on-Package: A New Opportunity for Integrated Systems

System-on-chip integration and multi-chip modules are currently the main efforts for high performance integrated electronic systems [Brown99]. This approach offers a potential solution of system integration at very high performance and high density. Whereas, it is not necessary compatible with the requirements of heterogeneous system integration in which circuits other than in CMOS technology or on silicon substrate are used for mixed signal applications. In many cases, implementation of large system-on-chip is not preferred because of performance and cost reasons [Baliga00][Dejule00]. With regard to performance concerns, many studies revealed that dividing a large chip into several small chips might improve system performance [David98][Afons99], because very long on-chip wires usually exhibit longer circuit delay compared with their off-chip counterparts. As for cost, the combination of different technologies such as analog/RF, logic and memory on a single chip and necessity of mixed-signal isolation in SoC can effectively increase the cost of the less expensive individual technologies. Moreover, larger chips have poorer yields, which consequently will increase the total cost as well. In RF applications, SoP provides high-quality passive components. It has

9

been shown that moving low quality expensive on-chip passive components off the chip, can significantly improve RF performance [Duo03]. As a result, a multi-chip-module solution for system-on-package integration might be preferred [David98].

The above discussions are just a general analyses, which indicate SoP may have cost benefits over SoC. Accurate and quantitative trade-offs between SoC and SoP will need the model. this thesis. In [Shen02], we have demonstrated that for relatively simple and low performance system, SoC usually offers better performance/cost factor, whereas for high complexity and high performance heterogeneous systems, SoP offers much better performance/cost gains.

Figure 2-4 shows the transition from a conventional MCM to a future SoP technology, in which all passive components are integrated directly in the build-up SoP substrate.

Figure 2-4 The transition from today’s MCM to future SoP: MCM is defined as two or more bare chips interconnected onto a single substrate, while SoP can integrate analogy /RF circuitry, digital circuitry, and memory, also can integrate passive components.

3. System-on-Package Design Challenges

The SoP platform uses ICs designed and fabricated by their individually optimized technologies. Analog and digital circuits can be brought together to function as if they were integrated but without the noise issue of a single chip solution. Memory and logic can be integrated at lower cost and reduced size. High-frequency circuits can be integrated with high-Q passive components in an electrically friendly environment,

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resulting in predicable and improved performance. However SoP still face many design and technical challenges[Zheng03].

3.1. Mixed-Hardware and Mixed-Signal Challenges

Figure 2-5 An example of SoP integration, in which the components, either as a real chip or as virtual components (IP cores) will be integrated. The module consists of mixed hardware technologies (logic, memories, RF, passives) and contains mixed-signals (digital, analog/RF).

Future SoP products will be inherently heterogeneous and mixed signal, containing RF front-ends, high-speed analog-to-digital and digital-to-analog (AD/DA) conversions, high-speed digital signal processing (DSP), and complex control for protocol setup and mode control, demanded by consumers for personal communication and computing. Figure 2-5 illustrates a SoP integration example, in which the components, either as a real chip or as virtual component (IP modules) will be integrated. The mixed hardware consists of logic IC, DRAM, analog/RF ICs, and passive components such as balun. The mixed signal consists of large and noisy digital signals and low amplitude, sensitive analog signals at RF receiver. Typical switching current of DSM digital circuits is in GA/s while signals of analog/RF could be as small as in µV and µA. The electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems in such a compact system will hence be big issues. Even in pure digital systems, maintaining signal integrity has been a difficult challenge due to finer interconnect pitch and higher operating speeds. In addition, a seamless description of a system as shown in Figure 2-5 for mixed signal operation and the technology mapping onto an appropriate

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physical architecture with mixed hardware technologies is still a challenge in system design. These issues will have to be solved.

3.2. Mixed Design Tools Challenges For long term, SoP design must concurrently take electrical, thermal, mechanical,

and reliability issues in a consistent manner. For example, a compact SoP module is shown in Figure 2-6, where the compact and high-density integration shorten the interconnection lengths and hence are good for electrical performance. However in such a configuration, thermal dissipation is a big problem. Integrated heat pipes may solve the thermal problem, but it may change mechanical properties and increase costs. Therefore, in an integrated SoP module design, all these factors must be considered concurrently; Trade-offs and compromises must be made between these factors. Unfortunately, exiting CAD tools do not support this.

Figure 2-6 Example of a compact SoP module, in which many factor, thermal, electrical, mechanical and reliability issues, must be considered concurrently. Trade-offs and compromise must be made between these factors.

3.3. Mixed Frequency Challenges: Digital Enters Microwave Spectrum Higher frequency is the trend of today’s computer and communication systems.

Figure 2-7 shows the frequency spectrum of some standards in wireless and digital systems applications. We can see that, wireless applications have already explored the frequency spectrum from less than 1GHz to 60GHz. For example, the 3rd generation mobile networking (WCDMA) utilizes the frequency band 1.9-2.2 GHz; wireless local area networking (WLAN) utilizes the frequency band of 2.4, 5, and 60 GHz. In digital domain, a 2GHz clock of a microprocessor covers a frequency spectrum about 3-

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10GHz while 40Gbps (OC-768) signal wave in optical communication systems covers frequency spectrum around 30-100GHz. That is to say, in modern digital systems, digital signals have already entered into the microwave spectrum. Digital electronics is no longer the traditional digital electronics where the signal propagation and its wave characteristics are mostly negligible. Many design techniques and methods, which traditionally only be employed in microwave engineering (such as impedance control, termination), should also be deployed in state-of-the-art digital systems

Figure 2-7 Frequency spectrum of some standards in wireless and digital systems. Digital signal has broadband spectrum. Nowadays it has already entered into the microwave spectrum. This will need some design techniques that traditionally only be considered in microwave engineering [Gong04].

4. System-on-Package Technology Challenges

4.1. Low Parasitic First-Level Interconnections The SoP technologies are driven by the requirements of high performance, low

power, and low cost consumer electronic products. Currently, high performance digital chip runs at GHz internal clock whereas off-chip speed is generally at hundred MHz due to the large packaging parasitics. Therefore, system designers play around the design techniques mostly inside the silicon. However, if the benefits of SoP are to be harvest, the packaging bottleneck must be removed, which needs extremely low parasitics for the

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first-level interconnections or so called "seamless integration technologies" [Zheng01a]. The enabling technologies for seamless integration include fine-pitch flip-chip assembly, low parasitic single-level packaging integration, thin film substrates with integrated passive components. For some low performance systems, conventional interconnections may still be used if power consumption is not critical. In such a case, selecting SoP is mainly driven by product weight and size reductions.

4.2. Power Dissipation and Thermal Removal In general, due to the greatly reduced packaging parasitics (particularly the reduced

capacitance loads for off-chip drivers), the total power consumption of a SoP is expected to be lower than that of a multi-level packaged counterpart. We anticipate at least 20% of power saving by using low parasitic SoP. However, when all chips are closely packed, the heat flux of the whole module is very high. Power dissipation and thermal removal is therefore a great challenge.

It has been estimated that if the current technology scaling continues without particular low power design techniques, the power density of future microprocessors will be a main limiting factor, as in [Gelsi01]. With low power circuit and system architectures, it is projected that in 2008, power dissipation of a CMOS chip in high- performance products will be around 170W, and the maximum allowable junction temperature is about 85oC (as listed in Table 2-1). This will result in a thermal resistance budget at 0.24oC/W for the whole module, indicating a great challenge for heat removal in high performance SoP products even with power efficiency circuit and system architectures. Assuming a SoP with a surface heat-flux at the limitation of forced air-cooling (~20W/cm2), the system size may then be dominated by the size of heat sink. A critical challenge can be seen when a number of such chips are integrated in one SoP module [Zheng03].

Similar analysis will show a thermal resistance budget of 24oC/W for handhold products. In these products, forced air-cooling is usually not preferred, and the heat will be removed mostly through the interconnect substrate. Assuming chips in handhold products are interconnected to the SoP substrate by flip-chip technology with typical chip size and I/O density shown in Table 2-1 and a thermal resistance per bump at ~650oC/W, the total thermal resistance for the first-level interconnections will then be 0.9~2.5oC/W. This contribution is not so much compared to the total budget of 24oC/W. The remaining 21.5~23.1oC/W budget will mostly be allocated to SoP substrate. This figure looks very promise compared with that in high performance SoP products. However, we should notice that in handhold products, low-cost polymer-based interconnect substrates are widely used. Thermal conductivity of these materials is usually poor. As a result, these materials may be still prohibited for utilization in SoP products. For example, we assume a SoP module in which all chips are tightly assembled

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and again we use the figures given in Table 2-1. Two options for the substrate material and 1mm substrate thickness are assumed (one is alumina with a thermal conductivity of 21W/moC and another is a polymer-based material, with a thermal conductivity 0.2W/moC). This gives a thermal resistance of the alumina substrate (with the same size of the chip in Table 2-1) about 0.66oC/W. If one uses the polymer-based material with poor thermal conductivity, it will give a thermal resistance of 66oC/W, which is far beyond the budget of thermal design (i.e. 21.5~23.1oC/W) for this packaging.

Table 2-1 CMOS chip package project in 2008 [ITRS99]

High-Performance Hand Hold Chip size (mm2) 713 72

Power (W) 170 2.5 Junction T (oC) 85 115 Ambient T (oC) 45 55 I/O pin account 4437 256-736

Solder bump pitch 150 µm 70 µm

4.3. High Density Interconnect Substrates The third technology challenge is about the low cost high-density interconnect

substrate and assembly technologies. As complexity of chips rises, number of I/O pins rises exponentially according to the Rent’s rule. This consequently increases wiring demands for system-level interconnections. On the other hand, size of interconnect-substrate or system size shrinks when it moves to SoP. In order to provide enough wires for system interconnections at a reduced substrate size, interconnect pitch will thus have to be reduced.

As an example, Figure 2-8 shows a global wiring demand for interconnecting a 10x10 microprocessor array with various wiring topologies [zheng03]. The wiring demands are calculated based on [Davis98]. In the first case, all signal pins are connected through point-to-point (P2P) interconnections. As a result, the total wring demand will roughly be around 1.5 million of chip edge length, which translates to around 37.5 km in total wire length with today’s microprocessor size. In the second case, a multiple drop bus topology is used, and the resulting wiring demand is about 10~30 times lower. The least wiring demand will be in the third case where a communication-network based interconnect topology or NoP (network-on-package) is used. Assume we use a 64-bit network bus, the resulting wiring demand will be ~0.1km, several hundreds folds lower than in the first case. However, even with the last case, the estimated interconnect pitch (metal width plus separation between two adjacent wires)

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will be ~20 µm in a 10-layer interconnect substrate (where we assumed 35% of wring efficiency due to power distribution and via block).

Figure 2-8 Global wiring demands for interconnecting a 10 by 10 processor array with different connection approaches

4.4. Other Challenges In addition to the above-mentioned challenges, thermal mismatch between the

substrate material and the chip is also an important concern, particular for large and power hungry chips. Today, FR4 substrate is one of the most commonly used low-cost substrates in high volume manufacturing. This material is obviously not suited for high-speed application and as thermal dissipation increases. Better substrate materials with affordable cost and easy for processing are therefore highly desirable. In order to reduce the system cost, reparability of the interconnect substrate is also an important concern. Another important issue is embedded/integrated passive techniques with low fabrication cost, as having been addressed in many other discussion papers such as [Tai00][Lim02]. We need to create new design rules and new passive library for board and circuitry design. Further, we need to find out more about reliability of this embedded technique.

3. Concurrent Chip and Package Design

1. Why Chip and Package Need Concurrent Design?

Although today’s products have feature sizes of 130 nanometers, the ITRS (2003) calls for further downsizing; 65-nm technology by 2007 and 32-nm by 2013. This size reduction implies significantly higher device switching speeds and faster circuits. With anticipate gate delays of less than 5 picoseconds for 65-nm technologies and gate rise/fall time at approximately 10% of the clock period; Microprocessors with 9.28GHz on-chip clock frequency are within reach by 2007, and 40GHz clock speeds on chip will ultimately follow [ITRS03]. However, the resulting high-density circuits will be so complex that device interconnectivity will become the impeding factor in achieving the desired performance. So, we must develop new approaches for interconnect and architecture design. Even though the design challenge is rooted in on-chip interconnect complexity and the speed bottleneck, it extends to the package and system level. Table 3-1 shows trends in chip size, chip complexity, and performance. Distributed electromagnetic effects associated with multi-GHz signal transmission through the interconnect hierarchy of these complex systems are performance-limiting factors that must be addressed. These effects include interconnect delay, and signal distortion due to resistive loss, cross-talk noise, power- and ground-distribution disturbances, and package- and substrate induced noise.

Table 3-1 also shows that circuit designers face an unprecedented technical challenge: we must design and integrate giant microwave circuits in which massive arrays of transistors are combined into compact, multifunctional systems and subsequently packaged into low cost products. It is projected that the gap between high performance off-chip speed and high performance on-chip local clock should be decreased. But in fact, the off-chip bandwidth is still growing slower than on-chip bandwidth, as shown in Figure 3-1[Chian02]. In Figure 3-1, the total I/O bandwidth calculated from total I/O pins × bandwidth/pin and total on-chip bandwidth calculated from on-chip clock frequency × the number of wires/chip. Hence first and foremost we’ll need innovative, perhaps revolutionary, approaches to integrating these performance-driven, multifunctional systems to overcome the interconnect and package bottleneck. Chip-package co-design and co-optimization is one of such revolutionary approaches, which not only improve robustness and integrity, but also result in the optimal total solution in terms of cost and performance.

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Table 3-1 Overall technology roadmap: performance and package chips (ITRS’03) Year of Technology Node 2004 2007 2010 2013 2016

Technology 90nm 65nm 45nm 32nm 22nm DRAM /introduction 4G 16G 32G 64G 128G Transistors/chip (µP) (M) 553 1,106 2,212 4,424 8,848 Chip size (µP) (mm2) 310 310 310 310 310 Number of signal I/O (µP) 1,024 1,024 1,280 1,408 1,472 Power/Ground I/O (µP) 2,048 2,048 2,560 2,816 2,944 On-chip local clock (MHz) (high performance) 4,172 9,285 15,079 22,980 39,683

Off-chip speed (MHz) (high perf., peripheral buses) 2,500 4,883 9,536 18,626 36,379

Power (W) H.P./H.H. 158/2.2 189/2.5 218/2.8 251/3.0 288/3.0 Power supply (V) H.P./H.H. 1.2/0.9 1.1/0.8 1.0/0.7 0.9/0.6 0.8/0.5 Metal levels # (µP/SoC) 10/14 11/15 12/16 12/16 14/18

H.P. – high performance microprocessor, µP – microprocessors H.H. – hand-hold products, SoC – system-on-chip

Figure 3-1 Predicted off-chip bandwidth growing slower than on-chip. Total I/O bandwidth calculated from total I/O pins × I/O bandwidth/pin. Total on-chip bandwidth calculated from on-chip clock frequency × the number of wires/chip. The picture is from [Chian02].

2. Coherent Mixed-Signal System Partitioning

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2.1. New Issues for Mixed-Signal System Partitioning

System Specification

Initial Synthesis

System Partitioning

SoC SoP

PerformanceEstimation

Cost Analysis

???

Implementation:Interconnection and

Technology Mapping

Chip design Software DesignResource and Design Library

Prototyping

Figure 3-2 A coherent view of system design, which emphasizes co-design of chip/package/system and leads to optimal system implementation in terms of cost and performance of system end products.

System-level optimization is needed for chip-package-system co-design during early system design. A desirable design flow with a coherent global optimization of a heterogeneous system is shown in Figure 3-2 [Zheng03]. This design process starts from system specification using system description languages followed by initial synthesis. After then, the system will be partitioned into various functional blocks or subsystems. Due to the fact that the cost of interconnections in future DSM systems will be higher than that of logic circuits and hence interconnections become a dominating factor in system cost and performance; The system implementation issues and packaging/interconnect hierarchy will have to be decided or planned in the conceptual-level design phase. This can be done by assuming an appropriate implementation plan (e.g., SoC, SoP or a mix of them), mapping an appropriate interconnect hierarchy onto this implementation plan, and then evaluating cost-performance issues as well as the time-to-market. After several cycles of evaluation for different implementation plans, the designer can select the best implementation method. After this, the designer passes the design to the chip and software design phases, and finally to system prototyping.

However, such a design methodology faces many challenges. First, the conventional software/ hardware and functional partitioning of the system are inadequate. To evaluate which implementation method is better, system partitioning will have to

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consider new constraints and opportunities such as geographical limitation, component reuse and intellectual property (IP) modules integration. The IP modules, which are also called virtual components described by hardware description languages, are emerging terms in SoC. Nowadays, more and more IP modules are available commercially from different vendors. They can also be seamlessly integrated in SoP products as traditional hard components. In summary, SoP design leads to new system partitioning categories such as functional partitioning, geographical partitioning, resource partitioning, hardware and software partitioning; etc. More information on these different partitioning in SoP can be found in [Zheng03].

2.2. Cost-Performance Driven Mixed-Signal System Partitioning In mixed-signal systems, the mixed signal performance and cost for mixed signal

isolation and passive components integration will be a dominate factor. Integrating a mixed-signal heterogeneous system on a single chip means extra cost for noise isolation and technology fusion. As a result, for many mixed-signal systems, a single chip solution is not necessary better. Therefore, when a designer selects in which technology the system should be implemented, the costs of mixed-signal isolation as well as technology fusion must be estimated, and the resulting system performance must be accurately evaluated. These issues were addressed currently by generic and relatively crude estimations. As the system complexity rises, such crude analyses become inadequate, and better approach must be developed. Cost performance mixed-signal partitioning is one main contribution of this thesis. The methods and models are published in [shen02]. Case studies on wireless systems design was presented in [Shen03b]. Case studies on SONET/SDH interface circuits was presented in [Shen03a, Shen04].

2.3. On-Chip versus Off-chip Passive Components Trade-Offs Analysis Integration of passive elements in a package is the most important factor in chip-

package co-design’s success. With the ability to integrate resistors, inductors, capacitors, and distributed transmission-line elements, chip and package designs couple closely. Chip designers can then move critical passive elements that require high quality factors and large space off the chip. For off-chip design, the package and passive component model should be first setup; Trade-offs are then performed for on-chip versus off-chip passive components. Integrating passive components off the chip can improves circuit performance and potentially saves costs. So, in RF circuit design, decisions on off-chip versus on-chip passive components should be made accurately. The most important metrics for these decisions are probably the performance of the resulting systems and the cost of implementation. Figure 3-3 shows the layout of two versions of LNA: the

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first one consists of a small chip and an MCM-D board where all passive components are integrated; the second one integrates all passive component on the chip. Detailed methodology for on-chip versus off-chip trade-off analysis was presented by [Duo03].

On-chip part

(b)

(a) The off-chip solution(b) The on-chip solution

Off-chip inductor

Off-chip inductor

Off-chip capacitor

Outline of the chip

off-chip part

(a)

Figure 3-3 Layout of the chips and the MCM-D substrate for the LNA with (a) the off-chip passive solution and (b) the on-chip passive solution

3. Circuit and Physical Level Design Issues

3.1. Modeling, Analysis and Design of Power Distribution Systems In mixed-signal systems, design and synthesis of power distribution is essential to

manage the power integrity and suppress the noise levels. This is because the power supply noise: (1) couples to the system globally via the power distribution network; (2) injects into the substrate of IC that is very harmful to sensitive circuit nodes; and (3) degrades the driver capability of gates causing signal delay and clock jitter. Figure 3-4 illustrates the impedance of a power distribution system in frequency domain for a microprocessor mounted on a mother board. For different frequencies, there are many high impedance peaks due to LC resonances of the package parasitic circuits in the supply path. In order to control the impedance to be lower than the target impedance, it is important to design the whole power supply network in frequency domain. A basic method is to allocate different decoupling capacitor at appropriate locations (both on-chip and off-chip) in order to push these peaks at higher frequencies so that they are not

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in the frequency range of this system. Chip and package co-design for power distribution design therefore offers unique properties for power integrity.

High-speed operation in DSM circuits and mixed-signal environment have exposed the fact that power supply networks, comprising both on-chip and package-level components, are complex LRC circuits and must be accuracy modeled. [Zheng01b] has presented a unified power distribution model for DSM SoC which has included both on-chip and off-chip part. It was also pointed out that, on-chip power distribution analysis will not be accurate if without off-chip par

Figure 3-4 Typical impedance profile in frequency domain of a power distribution system exampled as a microprocessor mounted in a mother board. The high impedance peaks at different frequencies are from LC resonance of the different package parasitic circuits in the power supply path.

Application of self-decoupling in ULSI power distribution is a promising technique for noise reduction. This technique was well studied both theoretically and experimentally in [Zheng01b]. In addition to increasing the total metal volume to alleviate the excessive dc voltage drops, it was found that fat wires were sliced into small ones and closely place power-ground pairs can reduce supply noise [Zheng01]. This is because small coupled wires increase the total mutual capacitance and hence reduce the loop inductance in the overall power distribution network. Another noise reduction technique is the area array power/ground pin distribution, as shown in [Zheng01b]. This technique will be necessity for external power connection in larger chips and package modules. The optimal area array power pin/ground pin distribution and the required

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number of power/ground I/O pins were studied in that paper [Zheng01] with regard to different wiring topologies and cross sections.

3.2. Concurrent Chip and Package Design for Signal Distribution

3.2.1. Package and Interconnection Models Current methodologies for evaluating the impact of the interconnect network and the package on system electrical performance entail step-by-step development of an equivalent circuit that can be incorporated in a circuit simulator [Cange98]. Full-wave electromagnetic analysis appears to be the most desirable approach. But the geometric complexity of the structures of interest makes it unrealistic for today’s computing resources. Instead, designers partition the interconnect and the package structure into components or parts. They then develop the electrical model for these components using electromagnetic modeling techniques whose complexity is dictated by the electrical size of the component under investigation [Lei02]. Electrical size means the component’s length in wavelengths. More specifically, it is the minimum wavelength in the frequency range of interest that helps in determining the component’s electrical size. If the component is only a fraction of the minimum wavelength, local electromagnetic behavior can be captured using a lumped circuit of capacitors and inductors, with values calculated using two- and three-dimensional electrostatic and magneto static field solvers [Kim99][Lee03]. This is usually the case when dealing with bond wires, pads, balls, and pins in a package [Husse96]. The parasitic inductance and capacitance introduced by these short interconnects, as well as the capacitive and inductive coupling between them, need to be taken into account for reliable design of packaged RF ICs (mixers, amplifiers, oscillators, and so on). This is done in the same way that digital circuit designers account for parasitic inductance and capacitance in high-speed package design. Interconnects approximately as long as the minimum wavelength requires models based on transmission-line theory. These models accurately predict crosstalk, interconnect delay, and reflections resulting from any changes in characteristic impedance levels. Such changes occur as the signals propagate through a variety of discontinuities in the interconnect network. For such cases, electrostatic solvers extract the per-unit-length capacitance and inductance matrices, which quantify capacitive and inductive coupling between the interconnects and govern the propagation characteristics of the voltage and current waves on the traces. Figure 3-5 [Afons99] is an example of signal channel for high-speed digital communication. This equivalent circuit includes 0.2mm on-chip wire, solder bump and seamless high off-chip connectivity (SHOCC). The equivalent circuit of solder bump was modeled as lump R, L, C elements and the R, L, and C parameters were extracted from the MAXWELL Quick-3-D parameter extractor.

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Figure 3-5 The equivalent circuit for inter-chip communication. It starts from CMOS driver, then through 0.2mm on chip wire, solder bump, off-chip wire, back to solder bump, on-chip 0.2mm wire to the CMOS receiver. Solder bump is modeled as lumped R, L, and C elements. The picture is from [Afons99].

Researchers have proposed a variety of approaches for multiconductor transmission line (MTL) modeling of coupled interconnects [Tripa85] [Celik96]. The most successful of these approaches lead to models compatible with circuit simulators such as SPICE. Several approaches proposed for lossy interconnect modeling use circuit simulators such as SPICE. The complexity, versatility, and efficiency of these approaches depend strongly on the physical properties of the interconnects and the bandwidth of interest to the specific simulation. 3.2.2. Off-Chip Signaling Techniques for High-Speed Digital Electronics

Signaling, the method used to transmit digital information from one location to another, is central to the design of digital system [Dally98]. It determines the reliability, power consumption, performance, and cost in these digital systems. The connection between processors, caches, and main memory in computer systems; multiprocessor and multicomputer interconnection networks; and high-speed network switches are all critically dependent on signaling technology. Along with increasing bandwidth requirement of digital systems, at box-to-box, board-to-board, and chip-to-chip levels, communication architecture and signaling techniques are also greatly changed. Currently, off-chip communications in various applications are far beyond Gbps data rate. These applications include fiber channel, Ethernet, 3GIO, InfiniBand, RapidIO.

A: From bus based communication to serial link based communication Current implementations in digital systems use wide buses, which require a large

number of signal pins for off-chip signaling. There is a severe limitation on the number of available pins per given package size and the power distribution network requires an increasingly large number of pins. Hence any scheme, which reduces the demand on the number of pins used for signaling, is very desirable. Bus architecture has also

25

geometry-related bandwidth limitations because of stub. Serial links can reach at 5-10 times higher bandwidth than bus architecture. Because of its higher bandwidth and less pins, serial links are rapidly replacing buses in high-end system.

Figure 3-6 Electrical transceiver system. In the transmitter, a number of channels are multiplexed into a high-speed output data stream to the driver. In the receiver, a clock recovery circuit extracts the clock from the data with proper edge alignment and retimes the data by a “decision circuit.” The data stream is then demultiplexed to the individual channel.

Figure 3-6 shows a typical example of a serial link signaling system: transmitter, channel, and receiver. The transmitter converts digital information to a signal (waveform) on the transmission medium, or communication channel. This channel is commonly a board trace, coaxial cable, or twisted-pair wire. The receiver on the other end of the channel restores the signal, by sampling and quantizing it, to the original digital information. Clock generation and timing recovery are tightly coupled to signal transmission and reception. The timing recovery, often embedded in the receiving side, adjusts the phase of the clock that strobes the receiver.

B: Voltage vs. current signaling Voltage-mode and current-mode are two kinds of signaling conventions. The two signaling mode differ, however, in their output impedance and their coupling to the local power supply. Current-mode signaling acts as a high-impedance current source and has the advantages of isolate the signal from two major noise sources: signal return crosstalk and power-supply noise. So, current-mode signaling is always chosen in high-speed serial links.

C: Differential vs. single-ended signaling

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Differential signaling creates less noise and has better noise immunity compared to single-ended signaling. It can reduce noise from ground bounce, receiver reference error, and crosstalk. But it requires two wires and pins per channel, whereas single-ended signaling requires only one wire and pin per channel. Although differential signaling is less efficient in terms of pin utilization, it makes system more robust and better suited for high-speed serial link application.

D: Binary vs. multi-level signaling

Figure 3-7 PCB channel characteristics (48 inch trace). Channel losses are dominated by skin effect and dielectric loss. Channel noise is dominated by crosstalk in connectors, packages and PCB. The SNR near 1-2G deteriorates at 40 dB/decade [Johns02].

One method to increase the achievable bit rate is to encode multiple bits in a data symbol using multi-level signaling. Instead of two voltage levels, a digital-to-analog converter (DAC) can be used to encode multiple bits on multiple voltage levels. For example, one can encode 2 bits/symbol on 4 voltage levels, reducing the required bandwidth by half while achieving the same bit rate [Farja99] [Stoni03]. Multi-level is also suitable for limited-bandwidth signaling channel. It means the same data rate can be achieved by decreasing the operation frequency and hence less channel attenuation. The decrease in signal bandwidth can potentially reduce the amount of ISI. Figure 3-7 shows the relationship between signal channel gain and operation frequency. It consists of connectors, packages and 48-inch long PCB trace. The channel losses are dominated by skin effect and dielectric loss and the channel noise is dominated by crosstalk in connectors, packages and PCB trace. If the data rate is 5Gbps (2.5GHz), the SNR can be improved (about 4dB) with 4-PAM signaling. With increasing PAM level, a high signal-to-noise (SNR) is required. For example, the proportional signal noise cannot

27

exceed 50% for binary signaling and 17% for 4-level signaling. So, multi-level signaling only makes sense when the channel bandwidth is constrained or when the circuit speed is limited.

E: Equalization techniques

104

105

106

107

108

109

101 0

-8

-6

-4

-2

0

2

4

6

frequency (Hz)

Atte

nua

tion(

dB)

Figure 3-8 Illustration of the transfer function of the one tap pre-emphasis, α1= -0.3. The data rate is 5Gbps and the symbol period is 200ps. It boosts the high-frequency components of the signal; meanwhile attenuate the low-frequency components of the signal.

When the data rate approach Gbps, designer have to compensate for the problem of signal degradation over long traces. Higher-frequencies always tend to attenuate faster than lower frequency components and it acts like a low-pass filter as shown in Figure 3-7. This will lead to server inter-symbol interference (ISI) and make signal detection unreliable. The equalization techniques can be used to compensate the signal degradation [Dally97] [Horow98]. There are three equalization techniques (transmitter equalization, receiver equalization and passive equalization). The active receiver equalization requires analogy signal values at the receiver to work (either through analog sampling and analog signal processing, or analog-to-digital conversion and digital signal processing). The receiver equalization is more complicated than transmitter equalization, which also called pre-emphasis. The idea of transmitter equalization is to boost the higher frequency components of the signal, which is attenuated faster than lower frequency.

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A symbol-spaced finite-impulse-response (FIR) filter is often used as the pre-emphasis filter and it is described by the following equation ( ) ( ) ( ) ( ) ...21 21 +−⋅+−⋅+= nVnVnVnV iiio αα where ,...2,1αα are the filter tap coefficients. Figure 3-8 shows the transfer function of one tap pre-emphasis, 3.01 =α . The data rate is 5Gbps and the symbol period is 200ps.

3.3. Concurrent Chip and Package Design for Clock Distribution Networks Global clock distribution has become increasingly difficult for very high frequency microprocessor or application specific integrated circuits (ASIC). Timing uncertainty must reduce with clock period, skew and jitter should be also scaled with clock period. A method, called as standing-wave global clock distribution, can be used to decrease the skew and jitter for global on chip clock distribution [Mahony03]. In recent years, several ideas have also emerged for overcoming the interconnect bottleneck associated with long lossy lines on a chip. Various groups have proposed a very promising electrical solution: the use of low-loss, thin-film wiring to replace these lines [Zhu96][Zhu97][Afons99]. The concurrent design of chip and package will provide optimal design of a clock network by taking advantages of package layers because of less wire resistance and capacitance. Figure 3-9 shows the global part of the clock network routed on the package. It can reduce the clock skew, and power consumption.

Chip

Substrate

Global Clock Network

Local Clock NetworkClock

Figure 3-9 Global part of the clock network are routed on the high-density substrate. It can reduce the clock skew and power consumption

From the viewpoint of electrical performance, there remains the issue of moving high frequency clock off the chip, through the thin-film wiring, and back onto the chip. For such an interconnection scheme to succeed, there must be a smooth continuation of the return current path. This means there should be no abrupt changes in impedance levels as the interconnections move from the chip to the package and back. The implementation of such reflectionless interconnect transitions is as challenging as the

29

design of a high-performance connector, and therefore they will require very innovative approaches for cost-effective design with acceptable electrical performance.

3.4. Design Platform for Concurrent Chip and Package Design Today computer-aided-design (CAD) flows for integrated circuit design are very separated from CAD flows for package design. The tools behave differently, are often provided by different vendors, and are typically based on different user interface paradigms. This leads to a number of problems and difficulties in the design of complex systems, especially with today’s high performance design and tight design cycles. First, it leaves open the scope for simple errors to propagate through to the first design iteration. Second, timing closure becomes much more difficult. Third, lack of coordination prevents many optimizations to be discovered [Varma03]. So designers must combine chip and package designs into one circuit design platform. Depending on CAD tools and component models, co-design can extend from either the chip or the package design.

Figure 3-10 shows that multiple CAD tools are used to complete individual purpose. We can use dynamic link between different tools to simulate the whole system include chip and package. However, the interface among different CAD software slows the design process. Therefore, most designers prefer an integrated CAD environment for chip and package co-design. The software should have the following capabilities [Lin98]:

Chip-level circuit simulation, whether it is in the time domain or the frequency domain. This is the basic requirement for IC design. Standard passive element models like inductor and transmission line elements. This is the major hurdle that limit SPICE-type CAD software, even though the microwave community has used these models extensively in certain frequency-domain simulation.

Electromagnetic analysis of nonstandard passive elements. Frequently designers will encounter nonstandard structures that need to be analyzed by electromagnetic simulation to ensure design accuracy. Instead of building the models based on the measured data of actual fabricated devices, designers may use electromagnetic CAD software as virtual prototyping to save time and cost.

Interface of chip-package layout with the above functions is needed. Layout is actually a part of high-frequency circuit design. If designers are not careful about the layout, parasitics and crosstalk can turn into disaster.

30

Figure 3-10 CAD tools for concurrent chip and package design

4. Concurrent Design of a UWB Radio Module

1. UWB Overview

The Federal Communications Commission (FCC) has released a First Report and Order (R&O) permitting the manufacture of unlicensed ultra-wideband (UWB) devices (Feb. 2002) in the frequency band 3.1Ghz - 10.6Ghz [FCC02]. According to FCC definition, UWB is any signal within that band fulfilling a special spectrum mask and occupying a bandwidth more than 500MHz bandwidth. For example, the indoor systems the average output power spectral density is limited to -41.3 dBm/MHz, as shown in Figure 4-1. In Europe (ETSI TG31a) the spectrum is not allocated yet but the proposals follow the FCC spectrum mask. This is by far the largest spectrum allocation for unlicensed use the FCC has ever granted. Given the recent spectrum allocation and the new definition of UWB adopted by the FCC, UWB is not considered a technology anymore but, instead, it is an available spectrum for unlicensed use. This means that any transmission signal that meets the FCC requirements for UWB spectrum can be used [Aie03]. This, of course, is not just restricted to impulse radios or high-speed spread-spectrum radios, but it also applies to any technology that uses more than 500MHz of spectrum in the allowed mask.

0 2 4 6 8 10 12 14 16

x 109

-80

-75

-70

-65

-60

-55

-50

-45

-40

Frequency (Hz)

UW

B E

IRR

Em

issi

on L

eve

l in

dB

m/M

Hz

Indoor LimitPart 15 Limit

GPS Band

Figure 4-1 Spectral mask mandated by FCC 15.517 (b, c) for indoor UWB communication systems. The average output power spectral density is limited to -41.3 dBm/MHz

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Nowadays, UWB techniques are emerging as a solution for the IEEE 802.15.3a (TG3a) standard. The purpose of the standard is to provide a specification for low-complexity, low-cost, low power consumption, and high-data-rate wireless connectivity among devices within or entering the personal operating space. The data rate should be high enough (greater than 110Mb/s) to satisfy a set of consumer multimedia industry needs for wireless personal area networks (WPAN) communication. For example, digital television (DTV) wireless distribution, video/audio conferencing, wireless Internet connectivity and interactive gaming. IEEE 802.15.4a (TG4a) formed a study group (SG) whose goal is to deliver the standard specification for UWB-based networks such as radio frequency identification (RFID), wireless sensors networks (WSN), identification networks (personal tracking, collision avoidance systems, surveying and construction) ambient intelligence, or other low-power, low-cost wireless devices supporting low data rate in individual links while the access point should support high aggregated throughput. The standard is expected to complete in the year 2005. The major distinction with recently adopted “Zigbee” standard is that UWB-based systems will be able to deliver communications and high precision location and ranging features. To meet the size, cost, and power consumption demands of consumer applications, a single-chip UWB transceiver architecture with few external components is desirable. There are a number of different fabrication options for UWB. CMOS is particularly compelling due to its low cost and low power consumption. But poor passive component and lower operating voltages associated with processing scaling pose significant problems for the radio architecture and designer. On-chip noise or interference can also potentially be more difficult for UWB compared with other noise from narrow-band interference (NBI). Digital clocks can produce significant EM radiation which can be difficult to isolate and their fundamental or harmonic frequencies are likely to fall within the bandwidth of the RF and baseband circuits. System-on-Package can be an alternative solution method to meet the system requirements as well as speeding time-to-market.

1.1. Impulse-based UWB System Architecture There are various impulse UWB system architectures based on pulse position

modulation [Hel03], direct sequence spread spectrum [Fji03] and multiband architecture [Foe03]. There are also different receiver architectures for each UWB communication system. One of the architectures is a fully digital receiver. It includes a high-speed analog-to-digital converter (ADC)(sample frequency is 10GHz)[Ver004]. The major drawback when using this architecture is its large power consumption. The power consumption is mainly dominated by the ADC and the matched filter. Alternative architectures are: (1) Channelized ADC. These are parallel ADC architectures, with each ADC operating at a fraction of the effective sampling frequency (2) Down conversion

33

before ADC (3) Subsampling ADC and (4) Move match filter or correlator operation to analog domain. A simplified block diagram for impulse based UWB radio system based on type 4 is shown in Figure 4-2. This architecture shows less power consumption compared with other architectures. On the transmit side an impulse that is band limited and modulated is fed via an optional power amplifier directly to the antenna. Note that there is no up conversion step. Likewise, on the receiver side the signal from the antenna is amplified and passed through either a matched filter or a correlation-type receiver. The transmitter power can be lower for the same data rate using this architecture. The impulse radio architecture is simple than traditional Armstrong radio architecture. It is this potential simplicity and savings in power consumption due to the circuit implementation and the reduced RF power requirements that has gained so much attention for UWB systems.

Band-SelectFilter

LNA

PAImpulse

Generator

ADC

Baseband&

MACPulse

Shaping Filter

Match Filter/Correlator

Optional

Figure 4-2 Example of an impulse radio architecture with matched filter/correlator in analog domain

1.2. Multi-band OFDM-based UWB Architecture Orthogonal frequency division multiplexing (OFDM) is a mature technology and it was invented almost 50 years ago. Today, many products such as asymmetrical digital subscriber line (ADSL), IEEE 802.11a/g, 802.16, Europe DTV use OFDM technology and it is also being considered in the following technologies: 4G, 802.11n, 802.16a, 802.20. It has a high spectral efficiency and excellent robustness against multi-path and narrowband interferers. Batra et al [Bat03] proposed a time-frequency interleaved multi-band OFDM based UWB system architecture, as shown in Figure 4-3. The basic idea is to divide the whole spectrum into bands that are 528MHz wide, as shown in Figure 4-4. So transmitter and receiver process smaller bandwidth signals (528MHz). In Figure 4-3 transmitter architecture, there is an Add CP&GI (prefix and guard interval) block. Prefix provides robustness against multi-path even in the worst-case channel environments. A guard interval between OFDM symbols is inserted in order to allow sufficient time to switch between channels.

The MB-OFDM based UWB architecture is similar to that of a conventional and proven OFDM system. The major differences are:

34

• Time-frequency kernel specifies the frequency for next OFDM symbol • Constellation size is limited to quarter phase shift key (QPSK) • For rates less than 80Mb/s, the input to the IFFT is forced to be

conjugate symmetric. It needs only to implement the “I” portion of the TX analog chain. As a result, only half the analog die size of a full “I/Q” transmitter is needed

• Zero-padded prefix limits power back at the transmitter

Scrambler

InputData Convolutional

EncoderPuncturer

BitInterleaver

ConstellationMapping

IFFTInsert Pilot

Add CP&GIDAC

Time-FrequencyKernel

)2exp( tfj cπ

FEQ

Rem

ove

Pilo

tsPre-SelectFilter

CarrierPhase

andTime

Tracking

LPF

LNA

Time-FrequencyKernel

)2cos( tfcπ

)2sin( tfcπ

VGA ADC

LPF VGA ADC

Syn

chro

niza

tion

Rem

ove

CP

FFT De-

Inte

rlea

ver

Vit

erbi

Dec

oder

De-

Scra

mbe

r OutputData

(a) Multi-band OFDM Transmitter Architecture

(b) Multi-band OFDM Receiver Architecture

Figure 4-3 Multi-band OFDM UWB system architecture for wireless personal area networks

Band#1

Band#2

Band#3

Band Group #1

3432MHz

3960MHz

4488MHz

Band#4

Band#5

Band#6

Band Group #2

5016MHz

5544MHz

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6600MHz

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Band#10

Band#11

Band#12

Band Group #4

8184MHz

8712MHz

9240MHz

Band#13

Band#14

Band Group #5

9768MHz

10296MHz

Figure 4-4 Band plan of MB-OFDM UWB. 528MHz bands are grouped into 5 distinct groups. Band group #1 is intended for 1st generation devices (3.1-4.9GHz) and band groups #2 - #5 are reserved for future use.

1.3. Physical Layer Design Challenges for UWB UWB also brings new challenges. We must solve multipath propagations, multiple

access, efficient acquisition and time synchronization. It imposes very strict requirements for several electronic components. For instance, in impulse-based and MB-OFDM UWB architectures, wideband antenna as well as a wideband LNA and a wideband mixer etc. have to be designed. Table 4-1 shows the similar and different

35

characteristics of the analog components of MB-OFDM and direct sequence ultra wideband (DS-UWB) systems. New challenges must be solved using current CMOS technology. For example, the 1st generation devices such as LNA should have a bandwidth of 1.9GHz (3.1-5GHz) for DS-UWB and 528MHz for MB-OFDM UWB.

Table 4-1 Analog complexity for multi-band OFDM and DS-UWB

MB-OFDM Analog Components

DS-UWB Analog Components

Similar Characteristics - Antenna - Preselect filter - LNA

- Antenna - Preselect filter - LNA

Different Characteristics - Switchable UNII filter - Hopping Frequency Gen - Band filter to reject adjacent channels

- Static UNII filter - Static Frequency Gen - Band filter with no adjacent channels

1.3.1. Wideband Miniaturized Antenna Design for UWB

The challenges in developing a suitable antenna for UWB wireless systems mainly lies in achieving constant gain and linear phase over a wide bandwidth. In recent years, many kinds of broadband antennas have been developed for UWB applications, such as monocone antenna [Amm03], quasi-horn antenna [Ngu01], and slot line/bow-tie hybrid antenna [Lai92].

1.3.2. Wideband LNA Design for UWB

Various wideband LNA topologies can be used in UWB systems. Such an amplifier must feature wide-band input matching to the antenna, flat gain over the entire bandwidth, good linearity, minimum possible noise figure and low power consumption.

Distributed amplifier (DA) in principle overcomes the trade-off between gain and bandwidth [Gin48]. Figure 4-5 shows a simple DA incorporating two-transmission lines, one for the input and another for the output. With lossless transmission line, the DA of Figure 4-5 provides infinite gain with infinite bandwidth: each common-source (CS) stage along with an additional length of T line increases the gain. In the ideal case, the voltage gain is simplified to Av≈πfTl/v, where l/v signifies the end-to-end delay of the line. The performance of distributed amplifiers is constrained by some effects, such as resistive losses of the transmission line, miller effect of transistor’s gain-drain overlap capacitance [Rza02]. The main shortage of DA is its large power consumption [Liu03][Bal00][Ahn02].

36

Figure 4-5 Simple distributed amplifier in [Tommi04]. The number of stages is 4. The bandwidth is from 1 to 13GHz. The gain is better than 10dB and the noise figure is less than 3.5dB throughout the whole frequency band.

Figure 4-6 LNA topology a) Resistive termination b) 1/gm termination c) Shunt-serials feedback d) Inductive degeneration

For lumped mode LNA, their topologies can be distinguished according to the matching methods, as shown in Figure 4-6. For the resistive matched common source LNA, it has the broadband input match but poor noise figure and signal attenuation because of the 50Ω terminal resistor. For the common gate LNA, it has broadband input match (1/gm) and minimum NF about 2.2dB for the long channel transistor. Bandwidth is limited by the RC at input and RC at output. It does not need an inductor, so it is area efficient and easy to model. The main shortage of the common gate LNA is that it is difficult to achieve high voltage gain. The third architecture shown in Figure 4-6(c) uses shunt series feedback to set the input and output impedances of the system. With this shunt series architecture, the bias point of the input is fixed with the output voltage. Therefore the biasing point of this system is not set to the optimal bias point. This non-optimal biasing point means that this type of system consumes a lot of power to achieve the desired gain. In addition this shunt series feedback architecture has a

37

stability problem because it uses feedback. However this architecture gives good noise figure and wide-bandwidth characteristic for the UWB system [Lid05][Kim05]. Figure 4-6(d) shows the common-source inductive degeneration LNA topology. A typical example using this topology is shown in [Bev04]. The Pseudo-ladder filter was used as wideband input match network and the frequency range is from 3.1 to10.6GHz and the shunt peaked output is also adopted to increase the bandwidth. The power consumption is similar to standard narrowband LNA (9mw). Power gain is about 10dB and average NF is 5dB over the wideband. The main problem is that it has many inductors and hence it will lead to larger chip area.

1.3.3. Wideband Low-Power Mixer Design for UWB

To design a mixer for a wide-bandwidth signal, the mixer must have broadband input characteristics and high conversion gain to keep the signal level high because the LNA in a wide-bandwidth system cannot provide enough gain with low power consumption. In addition to this requirement, usually the mixer requires differential input to reduce the mixer's noise figure and to increase linearity. The Gilbert type mixer can give additional gain to the signal but still re-quires broadband characteristics and differential input. The easiest way to achieve the broadband characteristics is by using resistive termination at the input nodes [Kob00][Tsa94]. However with this method, the resistor attached to the input increases the noise figure of the system. In paper [Pha04], a wide band shunt resistor matching network was used. It has a 528MHz bandwidth matching at 50Ω. The voltage conversion gain is 20.5dB. The double sideband noise figure is 5.6dB and power consumption is 11.5mW.

2. Optimal Pulse-shaper for Impulse-based UWB

Due to the very large bandwidth of the impulse radio signal, the propagation phenomena are different in the lower band and the upper band of the signal spectrum. Nowadays, the additive white Gaussian noise (AWGN) or Saleh-Valenzuela (SV) channel model is usually used for system simulation. Hence, the UWB pulse shapes are chosen to satisfy the channel features in order to improve the system performance [Che02]. Various pulse shapes [Che02] can be used as the UWB signal. Some of their power spectrum densities are shown in Figure 4-7. The Gaussian pulse and its 1st and 2nd derivatives don’t optimally exploit the FCC mask and cannot avoid interference with co-existing RF systems. The possible alternatives are using analog or carrier-modulation of the Gaussian pulse. While these two methods lack the flexibility or suffer from the carrier frequency jitter. For the pulse shaper in [Luo03], as shown in Figure 4-7, it has the maximum output power.

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A&B:Gaussian monocycles

C:Pulse shaper in [Parr03]

D&E:Pulse shaper in [Luo03]

Figure 4-7 Comparison of maximum Tx power of different pulse shapers. For the pulse shaper in D&E, it has the maximum output power.

3. UWB Link Budget for Wireless Intelligent Systems

The wireless intelligent systems such as RFID or WSN require low data rate, low price, and very low power consumption. The data rate can be 250Kbps or even smaller than 10kbps for wireless sensors etc. The range should be long (0-30m) or even greater than 100m at very low data rate. The battery consumption should be very low so that the self-powered operation time should be from several months to several years. Impulse-based UWB may allow for very low power consumption and also allows for precision position determination (10cm-1m accuracy). It can be used as wireless transceiver of RFID and WSN [Opp04]. One example of wireless sensors networks using UWB links is shown in Figure 4-8. The sensor base station and sensor node uses UWB as the air interface to transmit and receive the data.

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n1

n2

n3 n4 n5 n6

BaseStation

BaseStation

SensorNetworkServer

Internet

Sensor nodes

UWB links

Figure 4-8 Generic environmental sensor networks architecture. Sensor nodes gather data autonomously, and the network passes this data to one or more base stations through UWB links, and then these data are forwarded to sensor network servers

The link budget delineates the critical top-level requirements for the system including transmit power, path loss, required receiver sensitivity, and link margin. For transmitter power, the equivalent isotropically radiated power (EIRP) limitation defined by emission masks determines the maximum allowed transmitted power. Given the allowed power, we now will evaluate, under rather simplified hypotheses, the maximum distance over which propagation can occur when a predetermined probability of error must be guaranteed at the receiver. We assume that the system requirement of bit error rate (pe) is 10-3 and the data rate is 250kbps. If we consider that the only noise source is additive white Gaussian noise and the modulation used is binary phase shift key (BPSK), the requirement of signal-to-noise (SNR, Eb/No) is about 7.5dB. The maximum output power is found to be

)(10log*10/3.41 MHzBWMHzdBmPt +−= (4-1) where BW is the signal bandwidth.

We assume that the signal bandwidth is about 1.75GHz, so the maximum output power is –8.87dBm, as shown in Table 4-2.

Furthermore, the free-space attenuation is frequency dependent. So the received power is

( )( ) ( )

( )df

f

fP

D

CGGdf

fA

fPP

H

L

H

L

f

f

sRT

f

f FS

sr ∫∫ ==

222

2

*2*4

2π

(4-2)

where Pr is the signal power at the receiver, AFS is the frequency depended attenuation in free-space, Ps(f) is the power spectrum of the transmitted signal, D is the distance

40

between transmitter and receiver, f is the operating frequency, C is the speed of the light, GT is the transmitter antenna gain and GR is the receiver antenna gain.

Table 4-2 Maximum output power of the transmitter

Bandwidth (GHz)

3.1-10.6 (7.5)

3.1-4.85 (1.75)

6.2-9.7 (3.5)

Tx Power (dBm)

-2.5 -8.87 -5.85

Tx power (mW) 0.56 0.13 0.26

Table 4-3 shows an example of the link budget of the UWB transceiver. The maximum distance is mainly determined by the loss of the channel, noise figure of the receiver and processing gain. Figure 4-9 shows the relationship between link margin, received power and distance. In Figure 4-9, the received power is about –96dBm when free space distance is 100m.

Table 4-3 Example of a UWB link budget for wireless intelligent systems Parameter Value Unit Data rate (Rb) 250 Kbps Average Transmitter Power -8.87 dBm Tx antenna gain (Gt) 0 dB Geometric center frequency Fc 4 GHz Path loss (L) at 100m 84 dB Rx antenna (Gr) -3 dB Rx power (Pr=Pt+Gt+Gr-L) -96 dBm Average noise power (N=-174+10*log BW (Hz)) -81 dBm

Rx Noise Figure (NF) 5 dB Average noise power (Pn=N+Nf) -76 dBm Minimum Eb/N0 (S) 7.5 dB Implementation Loss (I) 3.0 dB Chip rate (Chip) 500 MHz Processing gain (PG=10*log (Chip/Rb) 33 dB

Bits per symbol 1.0 Link Margin (M=Pr-Pn-S-I+PG) 2.5 dB

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0 50 100 150 200-10

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dB

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Lin

k-m

argi

n(d

B) Pr

250kbps100kbps50kbps

Figure 4-9 Relationship between link-margin and distance

4. Concurrent Design Considerations for a UWB Radio Module RF IC Baseband IC

Antenna

MEMS Sensor

L R C

Figure 4-10 Illustration of the LCP integration of a wireless intelligent systems where the passive elements like inductors, resistors and capacitors are embedded in the LCP substrate.

In order to achieve system-level optimal cost and performance, concurrent design of circuits, packaging and integrated passive components is vital. We aim to explore innovations from architecture, circuit, and physical layout levels to attain low cost and high performance RF-SoP building blocks for wireless intelligent systems such as RFID or WSN. For such kind of systems, single chip solution may not be an optimal solution because of substrate noise between digital and analog parts as well as power supply noise etc. System-on-package is chosen to decrease the cost and speed up the time-to-market. The concept of SoP implementation of WSN is shown in Figure 4-10. It includes one micro-electro-mechanical-system (MEMS) sensor, one RFIC and one

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baseband IC. The passive elements like inductors, resistors, capacitors and even the antenna are embedded in the liquid-crystal-polymer (LCP). LCP is gaining increasing interest as a choice technology in the packaging community due to its superior thermal and electrical properties including low loss, low dielectric constant over a wide frequency range and low coefficient of thermal expansion (CTE). It has superior loss properties: loss tangent equals to 0.002 and CTE=8-17 ppm/K, so it is suitable for high frequency circuit substrate and packaging material [Davis03]. System integration of the UWB technology for wireless intelligent networks is tested with thin foils of LCP. Two integration methods are investigated. In the first method, all passive components and wires are printed on the LCP using screen printing technique. Chips are directly attached on the substrate via flip-chip bonding. Due to technical limitation, feature size of conductors are at 100-400um. In the second method, we use the same approach as our in-house developed SoP technology with embedded chip in the LCP substrate [Zheng05][Duo03a][Duo03b]. This is a deposition and lithography-based technology in which photo-bisbenzocyclobutene (BCB) are coated via pin-off technique for inter-layer conductor isolation and vias are etched for interlayer interconnection. Feature size of conductors is at 30-80um. Figure 4-11 shows two examples of the integrated substrates.

(a) (b)

Figure 4-11 (a) Photography of a circuit printed on a thin foil of LCP. (b) SEM picture of an embedded chip in LCP on which the BCB/Cu interconnections are patterned by spin-coating/sputtering and lift-off process.

(a) (b)

0

10

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0 5 10 15

Frequency(GHz)

Qu

alit

y F

acto

r

0

5

10

15

20

25

30

Ind

uct

ance

(nH

)

Q21 Q23 Q24 L21

L23 L24

43

Figure 4-12 (a) SEM picture of coplanar spiral inductors on LCP substrate. (b) Quality factors (top three curves) and inductance values (bottom curves) of the first, third, and fourth inductors in the second row of the above picture.

It is found that, though the manufacturing cost is low, the first integration method is

unacceptable. The variation of conductor width and surface roughness of the conductor wires result in excessive frequency deviation and losses in frequency range of 1GHz-13GHz. The method needs to be improved, particularly the accuracy of printing, conductivity and surface smoothness of the printed wires. These are important issues for excellent performance of microwave circuits.

Figure 4-12 (a) shows an array of inductors patterned on LCP substrate using the second method. Figure 4-12(b) shows the quality factors and inductance value of the first, third and fourth columns of inductors in the second row. They have the same metal width of 50µm, while spiral turn numbers are varied at 2.5, 1.5, and 0.5. The maximum quality factors Qmax of 56, 44 and 46, respectively, were achieved. Self-resonant frequencies were 25GHz, 15GHz and 11GHz, respectively. The loss tangent and dielectric constant of LCP are 0.0045 and 3.0, respectively. The material shows excellent microwave performance and hence should be ideal for wireless intelligent networks operating at microwave frequency range.

The RF parts for which the chip and package co-design method are used include the filter, LNA for the matching network, multiplier (or mixer) and VCO. These passive components can be implemented as on-chip or off-chip or a combination of the two. For SoP implementation of the UWB radio module, scalable or parameterized package, interconnect and passive components library should be developed so that different packaging, interconnect and passive components could be quickly mapped into the circuit netlist and hence run the simulation quickly at a circuit level simulator. In the UWB radio module design, special focus will also be paid on robust performance and manufacturability.

5. Summary of Papers

1. Summary of Included Papers

Paper 1

“Cost and Performance Analysis for Mixed-Signal System Implementation: System-on-Chip or System-on-Pacakge?” Meigen Shen, L.-R. Zheng, and H. Tenhunen, IEEE Trans. on Electronics Packaging Manufacturing, pp. 262-272, Vol.25, No.4, Oct. 2002

In this paper, SoC and SoP are compared according to the cost and performance constraints. A quantitative analysis method for SoC versus SoP is developed. An equivalent circuit was developed to simulate the substrate noise coupling. Performance of particular analog/RF circuits such as Low-Noise Amplifier (LNA), is also measured by their specific Figure-of-Merit (FoM), which considered the effects of substrate coupling, the quality factor (Q) of RF components, and packaging parasitics.

Author’s contributions: The author came up with the idea of all the detailed technology issues, set up the cost and performance models, analyzed and simulated the noise coupling equivalent circuits, and wrote the manuscript. Paper 2

“Cost and Performance Trade-off Analysis in Radio and Mixed-signal System-on-Package Design,” Li-Rong Zheng, Xinzhong Duo, Meigen Shen, Wim Michielsen, and Hannu Tenhunen, IEEE Transactions on Advanced Packaging, pp.364-375, Vol.27, No.2, May 2004 (Invited Paper)

In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SoC) versus system-on-package (SoP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SoP versus SoC, is presented. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling technology explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passive are used.

Author’s contributions: The author sets up the cost and performance models for SoC versus SoP analysis. The cost model is also used for on-chip and off-chip passive tradeoffs analysis.

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Paper 3

“Cost-Performance Driven Mixed-Signal System Partitioning: A Case Study on SDH/SONET OAN Interface,” Meigen Shen, L.-R Zheng, and H. Tenhunen, in Proc. of the 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'04), pp. 37-41, June 30 - July 3 2004, Shanghai, China

For a complex electronic system, early estimation of what technology should be used is very important. In this paper, an optical network access interface is optimally designed according to cost-performance trade-off analysis. The results of the comparison show that for such a complex, mixed-signal system, single chip is not a cost-effective solution compared with single package, which has 6 small chips. Author’s contributions: The author came up the idea, set up the cost and performance model to analyze the mixed-signal system partitioning, took an optical access network for an example, and wrote the manuscript. Paper 4

“Robustness Enhancement through Chip-Package Co-design for High-Speed Electronics” Meigen Shen, Jian Liu, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, in the Microelectronics Journal, pp.846-855, Vol.36, Issue 9, Sept. 2005

In this paper, a chip-package co-design flow for high-speed digital design was presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimum package pin assignment and transmitter equalization. From high-speed transmitter design example, co-design can alleviate signal integrity problem, enhance its bandwidth, and improve high-speed robustness. Author’s contributions: The author came up the idea, set up package and interconnection electrical model, designed and simulated the digital controlled on-chip impedance and transmitter equalization, and wrote the manuscript.

Paper 5

“Concurrent Chip-Package Design for 10GHz Global Clock Distribution,” Meigen Shen, L. -R. Zheng, Esa Tjukanoff, Jouni Isoaho, and H.Tenhunen, The 55th Electronic Components and Technology Conference, (ECTC-05), pp.1554-1559, May 31- June 3, 2005, Lake Buena Vista, Florida, USA

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In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The different clock distribution shape such as spiral, serpentine, mesh and plane are analyzed. The parameters of interconnect are extracted by using 3D electromagnetic field solver.

Author’s contributions: The author came up the idea, set up the interconnect modeling and extraction, designed and simulated a 10GHz standing wave oscillator and 10GHz LC oscillator, and wrote the manuscript. Paper 6

“UWB Radio Module Design for Wireless Intelligent Systems- from Specification to Implementation,” Meigen Shen, Tero Koivisto, Teemu Peltonen, L. -R. Zheng, Esa Tjukanoff, and H. Tenhunen, to appear in IEEE Trans. on Electronics Packaging Manufacturing, 2006

In this paper, we designed an impulse-based ultra wideband (UWB) radio module for wireless intelligent system applications such as radio frequency identification (RFID) and wireless sensor networks (WSN). The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver circuits include Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18um, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For UWB transceiver, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based System-on-Package (SoP) technology will be used to implement the UWB radio module for low cost and small size.

Author’s contributions: The author came up the idea, performed system level

simulation, designed and simulated UWB transceiver circuits, and wrote the manuscript.

2. Author’s Contribution

The contributions of the author of this thesis have been essential to all papers included in this thesis. These have been listed after the summary of each paper in Chapter 5.1.

6. Thesis Summary and Future Works

1. Thesis Summary

Advances in deep submicron technology and system integration are rapidly leading to exceedingly complex electronic systems with new paradigms as System-on-Chip (SoC) and System-on-Package (SoP). The highly miniaturized size and mixed-signal integration of these compact systems bring difficult challenges such as process complexity, noise isolation, and signal integrity. This thesis first has addressed the mixed-signal system implementation for SoC or SoP. SoC have many advantages but still have a number of challenges. SoP technique can potentially improve memory bandwidth, transfer of interconnection functionality to a high-density substrate, high noise isolation and integrated passive components. But SoP also has many design and techniques challenges. These challenges have been described in chapter 2 in this thesis.

With the higher frequency and higher density package, the system, chip and package should be co-designed to improve the whole system performance. This issue has been addressed in chapter 3. According to cost and performance driven system partitioning, chip and package are assigned different functions to improve the performance. In this chapter, other issues such as power distribution, signal distribution, clock distribution and CAD tools for chip and package co-design were also discussed.

In Chapter 4, a co-design and seamless integration technique for electronic system integration in SoP is developed through a demonstration- low cost, low power and low complexity UWB communication system. The UWB technology is first reviewed. UWB radio module using co-design method and SoP technologies are also described. The scalable and parameterized models of package, interconnect and embedded passive elements are also addressed in this chapter. Finally, Chapter 5 summarized the author’s contribution of this thesis. The thesis has been focused on two key issues: global level system partitioning for SoC and SoP with cost-performance trade-off and chip-package co-design for high-speed off-chip signaling and UWB radio module.

• Cost-performance driven for mixed-signal system partitioning in early conceptual level design has been addressed first in this thesis. A modeling technique for a priori cost and performance estimations has been developed. The performance model evaluates various noise isolation technologies, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to

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mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints.

• System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. Chip and package co-design and co-optimization for high-speed off-chip signaling have been addressed. First, interconnect and package constraints to the circuit and system architecture have been explored. Proper equivalent circuit models for package parasitic are set up. After that, bandwidth and noise of the signal channels are estimated. The off-chip signaling is optimally designed according to these packages and interconnection constrains.

• Chip-package co-design for UWB radio modules in SoP has demonstrated. The impulse-based UWB radio was used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensor networks (WSN). The operating frequency of the UWB radio is 3.1-5 GHz and it is designed using 0.18um, 1.8V CMOS technology.

2. Future Works

High-performance and multifunction systems demand novel, and often revolutionary, practices in heterogeneous system integration and packaging; System-on-Chip integration is not necessary compatible with technologies other than CMOS or silicon substrate. While chip-package co-design improves robustness for high-speed electronics. The future works will further extend these thesis works and explore new issues, for example

• Case studies for optimal SoC versus SoP partitioning with focus on RF • Innovative on-chip clock distribution in SoP with chip-package co-design • High performance, noise aware off-chip signaling techniques and signal

equalization • Modeling and analysis of power distribution network in mixed-signal SoP • Wideband RF circuits design • Scalable and parameterized models of package, interconnect and embedded

passive elements design

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