Considerații preliminare

1

Considerații preliminareTip

instructiuneFaza de

fetchCitire

registriOperatie

ALUAcces la

dateScriere registru

Timp total

Load word (lw)

200ps 100ps 200ps 200ps 100ps 800ps

Stoare word (sw)

200ps 100ps 200ps 200ps 700ps

R-format (add, sub...)

200ps 100ps 200ps 100ps 600ps

Branch (beq) 200ps 100ps 200ps 500ps

2

t200 2200 24002000180016001400120010008004000

lw $1, 100($0)

lw $3, 300($0)

lw $2, 200($0)

600

3

Considerații preliminare

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

4


IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

IM Reg ALU DM Reg

5

t200 2200 24002000180016001400120010008004000

lw $1, 100($0)

lw $3, 300($0)

lw $2, 200($0)

600

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB


t200 120010008004000

lw $1, 100($0)

lw $3, 300($0)

lw $2, 200($0)

600

IF ID MEM WBEX

IF ID MEM WBEX

IF ID MEM WBEX

Etapele pipeline

6

PC

Memorie instructiuni

Registri

4S

S

Data memory

Write data

Mux

ALU

adresa

cod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

Instr[15:11]

Mux

0

1

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]

IF:Instruction fetch ID: Instruction decode/register file read

Ex: Execute/adress calculation

MEM:Memory access

WB: write back

Mux

01

16 32

Mux

Calea de date pentru pipeline

7

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

Instr[15:11]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]

Mux

0

1

EX/MEM MEM/WBID/EXIF/ID

Execuţia instrucţiunii lw – IF

8

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

01

Instr[20:16]

Execuţia instrucţiunii lw - ID

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Instr[20:16]

Execuţia instrucţiunii lw - EX

10

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Execuţia instrucţiunii lw - MEM

11

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Execuţia instrucţiunii lw - WB

12

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Execuţia instrucţiunii sw – MEM

13

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Execuţia instrucţiunii sw – WB

14

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

Instr[15:11]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]


M u x

0

1

Execuția pipline a unei secvențe de instrucțiuni independente

15

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

lw $10, 20($1)

sub $11, $2, $3

add $12, $3, $4

lw $13, 24($1)

add $14, $5, $6

Controlul ȋn execuția pipeline

16

IF/ID

ID/EX

EX/MEM

MEM/WB

control

EX

M

WB

M

WB

WB

inst

ruct

iun

e

17

Controlul ȋn execuția pipeline - detalii

PC


Registri

4S

S

Data memory

Mux

Write data

Mux

ALU

adresacod

Read register 1

Write register

Read register 2

Address

Write data

Read data 2

Read data 1

Read data

Instr[20:16]

Instr[25:21]

0

1

Zero

0

1

Shift left 2

Sign-extend

Instr[15:0]

EX/MEMMEM/WBID/EX

IF/ID

0

1

ALUcontrol

6

Instr[20:16]

Instr[15:11]Mux

0

1

RegDst

AluSrc

ALUOp

RegWrite

EX

M

WB

controlInstr[31:26]

RegDst

AluSrc

ALUOp

M

WB

4

WB

PCSrc

RegWrite

Mem

toR

eg

MemRead

MemWrite

MemRead

MemWrite

Mux

PCSrc

Hazardul ȋn execuția pipeline

18

Prin hazard ȋn funcționarea pipeline vom ȋnțelege acele situații când execuția unei noi instrucțiuni nu se poate realiza pe următorul ciclu.

Pot fi puse ȋn evidență trei tipuri de hazard:

Hazard structural (structural hazard) – atunci când hardware-ul nu suportă execuția unei anumite combinații de instrucțiuni ȋn acelaşi ciclu.

În cazul procesoarelor MIPS setul de instrucțiuni a fost astfel gandit ȋncât să evite acest tip de hazard atât timp cât există o memorie de instrucțiuni şi o memorie de date.

Hazard al datelor (data hazard) – atunci când execuția unei instrucțiuni este blocată deoarece instrucțiunile anterioare nu i-au furnizat ȋncă datele necesare.

Hazard la citirea din memorie (load-use data hazard) – o formă specifică de hazard al datelor ȋn care data care se ȋncarcă din memorie nu este ȋncă disponibilă pentru următoarea instrucțiune.

Hazard al controlului (control hazard, branch hazard) - atunci când instrucțiunea executată nu este instrucțiunea corectă (ȋn cazul instrucțiunilor de ramificare).

19

Hazardul datelor ȋn execuția pipeline

Se datorează dependenței execuției unei instrucțiuni de rezultatul execuției unei instrucțiuni anterioare ȋncă nefinalizată.

add $s0, $t0, $t1sub $t2, $s0, $t3

IM Reg DM Reg

IM Reg DM Regsub $t2, $s0, $t3

add $s0, $t0, $t1

t

IM Reg DM Reg

IM Reg DM Regsub $t2, $s0, $t3

add $s0, $t0, $t1

t

20


IM Reg DM Reg

IM Reg DM Reg

lw $s0, 20($t1)

sub $t2, $s0, $t3

t

bubble

lw $t1, 0($t0)lw $t2, 4($t0)add $t3, $t1, $t2sw $t3,12($t0)lw $t4, 8($t0)add $t5, $t1, $t4sw $t5, 16($t0)

lw $t1, 0($t0)lw $t2, 4($t0)lw $t4, 8($t0)add $t3, $t1, $t2sw $t3,12($t0)add $t5, $t1, $t4sw $5, 16($t0)

21


IM Reg DM Reg

IM Reg DM Reg

Reg DM Reg

IM Reg DM Reg

lw $t1,0($t0)

lw $t2, 4($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

add $t5, $t1, $t4

Reg DM Reg

Reg DM Reg

Reg DM Reg

t

lw $t4, 8($t0)

sw $t5 12($t0)

22

IM Reg DM Reg

IM Reg DM Reg

Reg DM Reg

IM Reg DM Reg

lw $t1,0($t0)

lw $t2, 4($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

add $14, $5, $6

Reg DM Reg

Reg DM Reg

Reg DM Reg

t

lw $t4, 8($t0)

sw $t3, 12($t0)


Modificarea procesorului pentru eliminarea hazardurilor

23

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

sub $2, $1,$3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($t2)

24

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

sub $2, $1,$3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($t2)


1a. EX/MEM.RegisterRd=ID/EX.RegisterRs

1b. EX/MEM.RegisterRd=ID/EX.RegisterRt

2a. MEM/WB.RegisterRd=ID/EX.RegisterRs

2b. MEM/WB.RegisterRd=ID/EX.RegisterRt

25


26


Mux

ALU

Instr[20:16]

Instr[25:21]

0

1

EX/MEM MEM/WB

ID/EX

Registri

Write data

Read register 1

Write register

Read register 2

Read data 1

Read data 2

Mux

Mux

Data memory

Address

Write dataRead data

Forwarding unit

ForwardA

Mux

ForwardB

Rs

Rt

Rt

RdEX/MEM.registerRd

MEM/WB.registerRd

EX hazard:

IF (EX/MEM.RegWrite

and (EX/MEM.registerRd0)

and (EX/MEM.RegisterRd=ID/EX.RegisterRs)) ForwardA=10

IF (EX/MEM.RegWrite

and (EX/MEM.registerRd0)

and (EX/MEM.RegisterRd=ID/EX.RegisterRt)) ForwardB=10

27


28

MEM hazard:

IF (MEM/WB.RegWrite

and (MEM/WB.registerRd0)

and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) ForwardA=01

IF (MEM/WB.RegWrite


and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) ForwardB=01


29

add $1, $1, $2

add $1, $1, $3

add $1, $1, $4


IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

add $1, $1,$2

add $1, $1, $3

add $1, $1, $4

30

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

add $1, $1,$2

add $1, $1, $3

add $1, $1, $4


31

IF (MEM/WB.RegWrite


and (EX/MEM.RegisterRdID/EX.RegisterRs)

and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) ForwardA=01

IF (MEM/WB.RegWrite


and (EX/MEM.RegisterRdID/EX.RegisterRt)

and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) ForwardB=01


32

Furtul de ciclu

IM Reg DM Reg

IM Reg DM Reg

lw $s0, 20($t1)

sub $t2, $s0, $t3

t

bubble

if (ID/EX.MemRead and((ID/EX.RegisterRt=IF/ID.RegisterRs) or (ID/EX.Register Rt=IF/ID.RegisterRt))) stall the pipeline

33

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

lw $2, 20($1)

and $4, $2, $5

or $8, $2, $6

add $9, $4, $2

Furtul de ciclu

34

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

lw $2, 20($1)

or $8, $2, $6

add $9, $4, $2IM Reg DM Reg

and $4, $2, $5

and devine nop

Furtul de ciclu

35

Furtul de ciclu

PC


adresacod

ID/EX

EX

M

WB

controlInstr[31:26]

RegDst

AluSrc

ALUOp

Unitate detectie hazard

Mux

0

ID/EX. RegisterRt

PCWrite

IF/I

DW

rite

IF/ID

Hazardul controlului

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

40 beq $1, $3, 28

52 add $14, $2, $2

72 lw $4, 50($7)

IM Reg DM Reg

48 or $13, $6, $2

44 and $12, $2, $5

Hazardul controlului

IM Reg DM Reg

IM Reg DM Reg

IM Reg DM Reg

40 beq $1, $3, 28

72 lw $4, 50($7)

44 and $12, $2, $5

Întrebări?

38

Documents

Considerații preliminare