1

Computer Architecture

CS 217

2

A Typical Computer

CPU

ChipsetMemory

CPU. . .

I/O bus

Network

ROM

3

General Computer Architecture

ControlUnit

L1 Cache

Registers

ALU

FPU

CPU

Memory(“RAM”)

Disk Net Display

MBus

I/O Bus

L2 Cache

4

Memory HierarchyCapacity Access time

Register: 1x102 bytes

L1 cache: 2-4x104 bytes

105 bytes L2 cache: ~10x

L3 cache: ~50x106 bytes

DRAM: ~200-500x109 bytes

Disks: ~30M x1011 bytes

CD-ROM Jukebox: >1000M x1012 bytes

5

ControlUnit

L1 Cache

Registers

FPU

CPU

Memory(“RAM”)

Disk Net Display

MBus

I/O Bus

L2 Cache

Fetch-decode-execute cycle

ALU

6

Memory

ControlUnit

L1 Cache FPU

CPU

Disk Net Display

MBus

I/O Bus

L2 Cache

ALURegisters

Memory

232-1

0

7

Byte-order in memory words

Memory

232-131 24 23 16 15 8 7 0

.

.

.

Byte 4Byte 0

Byte 5Byte 1Byte 2

Byte 6Byte 3Byte 7 0

Byte order is little endian

8

IA32 Architecture Registers

General-purpose registers

Segment registers

EFLAGS register

EIP (Instruction Pointer register)

EAXEBXECXEDXESIEDIEBPESP

31 0 015CSDSSSESFSGS

AXBXCXDX

16-bit 32-bit

BPDISI

SP

ALAHBLCLDL

BHCHDH

8 715

9

Why so complicated?

Intel 4004 (4-bit) 19718008 (8-bit) 19728080 19748086 (16-bit) 1978

80186 1982 (ENTER, LEAVE, etc.)80286 1982 (segment registers)80386 (32-bit) 1986 (virtual memory support)80486 1989 (much faster)Pentium 1993 (faster yet)Pentium Pro 1995Pentium II 1997 (MMX)Pentium III 1999

AMD64 (64-bit) 2004

10

Registers you care about

General-purpose registers

Segment registers

EFLAGS register

EIP (Instruction Pointer register)

EAXEBXECXEDXESIEDIEBPESP

31 0 015CSDSSSESFSGS

AXBXCXDX

16-bit 32-bit

BPDISI

SP

ALAHBLCLDL

BHCHDH

8 715

11

Registers you care about

31 0EAX “A”EBX “B”ECX “C”EDX “D”ESI “E?”EDI “F?”EBP “Frame pointer”ESP “Stack pointer”

EFLAGS

ALBLCLDL

6 general-purpose registers

“Condition codes”

EAX “Program counter”

12

Some registers you don’t care about• IA32 memory is divided into segments, pointed by segment registers

• Modern operating system and applications use the (unsegmented) memory mode: all the segment registers are loaded with the same segment selector so that all memory references a program makes are to a single linear address space.

4Gbytesaddressspace

232-1

15 0CS: code segment register

SS: stack segment register

DS: data segment register

ES: data segment register

FS: data segment register

GS: data segment register 0

13

Other Registers that you don’t much care about

• Floating Point Unit (FPU) (x87)o Eight 80-bit registers (ST0, …, ST7)o 16-bit control, status, tag registerso 11-bit opcode registero 48-bit FPU instruction pointer, data pointer registers

• MMXo Eight 64-bit registers

• SSE and SSE2 o Eight 128-bit registerso 32-bit MXCRS register

• Systemo I/O portso Control registers (CR0, …, CR4)o Memory management registers (GDTR, IDTR, LDTR)o Debug registers (DR0, …, DR7)o Machine specific registerso Machine check registerso Performance monitor registers

14

Enough registers, here come the instructions

Pentium instruction as

op source, dest “dest ← dest ⊕ source”

operation (move, add, subtract, etc.)

first operand (and destination)

second operand

15

Machine language, assembly language• Machine language encodes instructions as a sequence of

integers easily decodable (fast!) by the machine

• Instruction format:

n1 bits n2 bits n3 bits

opcode operand operandOperand

specifies what data on which to perform the

operation (register A, memory at

address B, etc.)

Opcodespecifies “what

operation to perform” (add, subtract, load,

jump, etc.)

16

CISC vs. RISCComplex Instruction Set Computer

(old fashioned, 1970s style)

Examples:

Vax (1978-90)

Motorola 68000 (1979-90)

8086/80x86/Pentium (1974-2025)

Instructions of various lengths, designed to economize on memory (size of instructions)

Reduced Instruction Set Computer

(“modern”, 1980s style)

Examples:

MIPS (1985-?)

Sparc (1986-2006)

IBM PowerPC (1990-?)

ARM

Instructions all the same size and all the same format, designed to economize on decoding complexity (and time, and power drain)

17

Instruction• Opcode

o What to do

• Source operandso Immediate (in the instruction itself)o Registero Memory locationo I/O port

• Destination operando Registero Memory locationo I/O port

• Assembly syntaxOpcode source1, [source2,] destination

18

Types of Instructions• Data transfer: move from source to destinatio• Arithmetic: arithmetic on integer• Floating point: x87 FPU move, arithmetic• Logic: bitwise logic operations• Control transfer: conditional and unconditional jumps, procedure calls• String: move, compare, input and output• Flag control: Control fields in EFLAGS• Segment register: Load far pointers for segment registers • SIMD

o MMX: integer SIMD instructionso SSE: 32-bit and 64-bit floating point SIMD instructionso SSE2: 128-bit integer and float point SIMD instructions

• Systemo Load special registers and set control registers (including halt)

19

Data Transfer Instructions•mov{b,w,l} source, dest

o General move instruction

•push{w,l} sourcepushl %ebx # equivalent instructions

subl $4, %espmovl %ebx (%esp)

•pop{w,l} destpopl %ebx # equivalent instructions

movl (%esp), %ebxaddl $4, %esp

• Many more in Intel manual (volume 2)o Type conversion, conditional move, exchange, compare and

exchange, I/O port, string move, etc.

20

Immediate Operands• All arithmetic instructions allow immediate as source

operands

• Example in gcc assemblymovl $10, %eax # move 10 to EAX registe

21

Register Operands (subset)• General-purpose:

o eax, ebx, ecx, edx, esi, edi, esp, ebpo ax, bx, cx, dx, si, di, sp, bpo ah, bh, ch, dh, al, bl, cl, dl

• Segment registerso cs, ds, ss, es, fs, gs

• Assembly syntaxaddl $12, %ebx

22

Memory Operands• Addressing memory

o 8-bit is the smallest unito 32-bit addresses (protected mode, will be extended to 64-bit later)o IA32 is little endian

• Examplesmovb $0x4a, %almovw $5, %axmovl $7, %eax

A byte7 0

A+1 A15

16-bit word

A+3 A+2 A+1 A 32-bit word31

23

Effective Address

• Displacement movl foo, %eax

• Base movl (%eax), %ebx

• Base + displacement movl foo(%eax), %ebxmovl 1(%eax), %ebx

• (Index * scale) + displacement movl (,%eax,4), %ebx

• Base + (index * scale) + displacement movl foo(,%eax,4), %ebx

eaxebxecxedxespebpesiedi

eaxebxecxedxespebpesiedi

1234

+ * +

None

8-bit

16-bit

32-bit

Offset =

Base Index scale displacement

24

Bitwise Logic Instructions• Simple instructions

and{b,w,l} source, dest dest = source & destor{b,w,l} source, dest dest = source | destxor{b,w,l} source, dest dest = source ^ destnot{b,w,l} dest dest = ^destsal{b,w,l} source, dest (arithmetic) dest = dest << sourcesar{b,w,l} source, dest (arithmetic) dest = dest >> source

• Many more in Intel Manual (volume 2)o Logic shifto rotation shifto Bit scan o Bit testo Byte set on conditions

25

Arithmetic Instructions• Simple instructions

o add{b,w,l} source, dest dest = source + desto sub{b,w,l} source, dest dest = dest – sourceo inc(b,w,l} dest dest = dest + 1o dec{b,w,l} dest dest = dest – 1o neg(b,w,l} dest dest = ^desto cmp{b,w,l} source1, source2 source2 – source1

• Multiplyo mul (unsigned) or imul (signed)mull %ebx # edx, eax = eax * ebx

• Divideo div (unsigned) or idiv (signed)idiv %ebx # edx = edx,eax / ebx

• Many more in Intel manual (volume 2)o adc, sbb, decimal arithmetic instructions

26

EFLAG Register & condition codes

CF1P

F0AF0Z

FSF

TF

IF

DF

OF

IOPL

NT0R

FVM

AC

VIF

VIP

IDReserved (set to 0)

012345678910111213141516171819202131 22

Carry flag

Identification flagVirtual interrupt pendingVirtual interrupt flagAlignment checkVirtual 8086 modeResume flagNested task flagI/O privilege levelOverflow flag

Interrupt enable flagDirection flag

Trap flagSign flagZero flagAuxiliary carry flag or adjust flagParity flag

27

Branch Instructions• Conditional jump

o j{l,g,e,ne,...} target if (condition) {eip = target}

• Unconditional jumpo jmp targeto jmp *register

Comparison Signed Unsigned= e e

neaaebbec

nc

“equal”≠ ne “not equal”> g “greater,above”

≥ ge “...-or-equal”< l “less,below”≤ le “...-or-equal”

overflow/carry ono ovf/carry no

28

A little programRecurrence relation:

f(n) = 3n+1 (if n is odd); n/2 (if n is even)

Example: 6 → 3 → 10 → 5 → 16 → 8 → 4 → 2 → 1

Question: for every integer n, will the sequence eventually reach 1?

Answer: nobody knows

Program:count=0;while (n>1) {count++;if (n&1)n = n*3+1;

elsen = n/2;

}

29

n %edxcount %ecxIn assembly language

movl %edx, %eaxandl $1, %eaxje .else

jmp .endif.else:

.endif:sarl $1, %edx

movl %edx, %eaxaddl %eax, %edxaddl %eax, %edxaddl $1, %edx

addl $1, %ecx

.loop:cmpl $1, %edxjle .endloop

jmp .loop.endloop:

movl $0, %ecx

count=0;while (n>1) {count++;if (n&1)n = n*3+1;

elsen = n/2;

}

30

Number Systems

31

Conversion

32

Addition

33

Multiplication

34

Machine Arithmetic

35

Signed Magnitude

36

One’s Complement

kk C ^1 =−

11)1(

1 ++=−+−−+=−

C

n

bababraba

37

Two’s Complement

1^2 +=− kk C

38

Two’s Complement (cont)

C

n

bababraba

2

1)1(+=−

+−−+=−

39

Sign Extension

40

Summary• IA32 is a complex machine

o Three memory models: flat, segmented, real-addresso Four operating modes: real, protected, system mgmt, virtual 8086o Many kinds of instructions

• Things to remembero Five types of memory operands (immediate, base,

base+displacement, index*scale + displacement, base+index*scale+displacement

o Two’s complement