1

COTS Approach to Military Microprocessor MCMs by

Tom TerlizziVice President

Aeroflex35 South Service Road

Plainview, L.I., N.Y. 11803Phone: 516.752.2418 FAX: 516.694.6715

email: T2@AEROFLEX.COM

ABSTRACTOne of the major problems in fielding state of the art Military electronic systems is the lack ofmilitarized electronic components and their swift obsolescence. This paper describes the

development of a line of 64 bit MIPS-BasedTM Microprocessor Multi-Chip Modules (MCMs).Solutions and obstacles encountered to support these products for over a decade and theapplicability of these solutions to other similar products are described.

KEY WORDS: MIPS-BasedTM 64 bit Microprocessor, Multi-Chip Modules (MCMs), Military, obsolescence.

IntroductionMilitary Original Equipment Manufacturers (OEMs) are facing a difficult situation in obtaininghigh performance semiconductor components. Figure 1 illustrates that the percentage ofmilitary value will decrease to 0.5% in 2005. This trend is the reason many semiconductorvendors are exiting the Military and Space product markets. The economics cannot supportthe infrastructure to deal with these products in low volume and low revenue content. Addedto this problem is the long life cycle of typical military products. This is not coincident withMoore’s law or the demand for new commercial products as shown in Figure 2.

Figure 1 - Percentage of U.S. Semiconductor Production Designated for Military Use by Value1

Typical designs and product life cycles for wireless cell phones are at a point where there aretwo designs per year. However, the volumes for cell phones are in the tens to hundreds of

1. Braun, Ernest and MacDonald, Stuart “Revolution in Miniature - The History and Impact of SemiconductorElectronics”, pp80 (1982). Update Walt Lahti of ICE*.

0%

5%

10%

15%

20%

25%

30%

35%

1955 1975 1995 *2005

2

millions per year. While military life cycles are in the order of tens of years and the volumesare in the hundreds to thousands.

Figure 2 - Typical Product Life Cycle

Multi Chip Modules Design ConsiderationsIn 1992 Aeroflex’s initial military microprocessor MCM was the 1608 a 64-bit MIPS TM RISCMicroprocessor with 256K secondary cache memory. It was packaged in a 280 lead ceramicquad flatpack (CQFP) as a custom design with a major military OEM. A photograph withphysical dimensions is shown in Figure 3 below.

Figure 3 - 64 Bit MIPs RISC Microprocessor MCM 1608

Table I lists the key components for the initial design and their attributes. Figure 4 is asimplified block diagram showing the 256K of Level 2 (L2) cache.

MIPS is a registered trademark in the United States and other countries, and MIPS32, 4KEc, 4Kp,SOC-it and MIPS-based are trademarks of MIPS Technologies, Inc.

Table I - MCM Thermal Device Data

DeviceDie Size

(inch)

PowerWatts(max)

Junction Temp. Rise

(°C)

θjc°C/W

(max)

R4400SC Microprocessor

0.498x

0.70714 5.78 0.413

3PC218 SRAM0.203

x

0.2320.5 1.08 2.16

CMOS Buffer0.065

x

0.0670.25 2.82 11.28

85 Spaces at 0.025

1.768 MAX

53 Spaces at 0.025

.010

Pin 226 Pin 141

Pin 227 Pin 140

Pin 87

Pin 86

Pin 280

Pin 1

.006 .175 MAX

.072 ±.01

2.525 MAX

Note: Outside ceramic tie bars not shown for clarity.

R4400 MIPS RISCMicroprocessor Die

11 each 16K x 16 SRAM Die

Contains 1,516Wire BondsNote: Ceramic Tie Bar

3

Figure 4 - Simplified Block Diagram of the 64 Bit MIPs RISC Microprocessor MCM 1608

General Registers

ALU/Multiply/Divide

Pipeline/Control

INTEGER EXECUTION UNIT

CACHE/MMU

FLOATING POINT

16K ByteInstruction

Cache

16K ByteData

Cache

48 EntryTLB

CacheControl

MMU

FPU ALU

Multiply/DivideSquare Root

FP Register

Pipeline Control

SCOESCDCS

SCData(127:0)SCDchk(15:0)

SCAddr0

SCAddr

SCAddr17

SCTag(24:0)SCTchk(6:0)

SCTCS SCWE

A0

A15

A14:A1

CE DQ0-DQ31

GND

BWLBWH

A15

A0

DQ143-DQ0CE

OE

WE

(9) 16Kby 16

SRAMs

SystemInterface

R4400SC/MC Microprocessor

CACHE

CACHE TAG

OE

WE

(14:1)

BWLBWH

DATA/INSTRUCTION

(2) 16Kby 16

SRAMs

A14:A1

Secondaryor Level 2(L2) Cacheor Level 2

Primaryor Level 1

(L1) Cache

4

Multichip Module Design Considerations

Electrical

Introduction

The electrical requirements for the initial MCMs specified a 66 Mhz clock rate with anestimated 3.0 nanoseconds minimum rise time. The signal path is modeled as a simple R-Cseries circuit as shown in Figure 5. The 3-db bandwidth can then be related to the pulse risetime of the digital signals of the MCM. Since the system pulse rise time is 3.0 nanoseconds,the required bandwidth is 116.6 MHz. As shown in Figure 6, to reproduce the rise time withminimal distortion (<2%) would require passing the 5th harmonic or 5 x 116.6 MHz or 583.3MHz.

Figure 5 - Simple RC Model of MCM Traces

1.00.95.90.85.80.75.70.65.60.55.50.45.40.35.30.25.20.15.10.050 0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.1 2.32.2 RC

PER

CEN

TAG

E O

F FU

LL V

OLT

AG

E

VOUT

CRV

R=RESISTANCE OF CONDUCTORSC=CAPACITANCE OF THE SIGNAL PATH

VOUT V 1 et RC( )⁄–

–( )=

CMAX1

2π 5f3db( )R-----------------------------=

trisetime 2.2RC 2.22πf3db----------------= =

f3db1

2πRC---------------= or

trisetime0.35f3db----------=

CMAX1

2π 583.3MHz 3.75Ω××------------------------------------------------------------=

CMAX 72.6pf=

TIME IN RC INCREMENTS

5

For example, the resistance of a circuit with an 8 mil line width which is two inches long canbe calculated as follows:

where:ρ = conductor sheet resistivityl = length of conductorw = width of conductor

If the sheet resistivity (ρ) is .015 ohms/, then R = 3.75 ohms. Solving for the maximumcapacitance from Figure 5 results in CMAX = 72.6 pf or 36.3 pf/inch or 14.28 pf/cm.

Figure 7 - Line Capacitance VS. Dielectric Thickness

Thus, the simplified model shows that high temperature alumina cofired ceramic (HTCC)can be used with a two inch conductor run since for a variety of dielectric thickness andconductor widths, the capacitance per unit length is less than 3.0 pf/cm, see Figure 7 (Pertypical manufacturer’s data sheet).

While other materials with lower dielectric constants are available (See Table II below), onlyaluminum nitride has better thermal conductivity. However, in 1992 we felt at that time thataluminum nitride had a higher technical risk and no extensive history of military qualification.Therefore, alumina ceramic represented the lowest risk at that time.

Table II - Ceramic Material Characteristics

Ceramic Technology Dielectric ConstantThermal Conductivity

W/m*k

Alumina 9.7 - 10.0 17

Aluminum Nitride (AlN) 8.5 150

Low temperature Cofired Ceramic 7.9 2

Mullite 6.8 5

Glass Ceramics (LEC) 5.0 2

R ρ lw----×=

h

εv

W

t

h

4 8 12 16 20

4

3

2

1

0

Dielectric Thickness h (mils)Lin

e C

ap

ac

itan

ce

Co

(P

F/c

m)

6

Figure 6 - Trace Rise Time vs Distortion

tINPUT 1 125------+=

tINPUT

5-------------- tSIGNALPATH=

tOUTPUT t2INPUT t2

SIGNALPATH+=

t risetime=

tOUTPUT t2INPUT

t2INPUT

52-----------------+=

re: if

tOUTPUT = tINPUT X 1.019 2% error

4030252015

109876

54

3

2

13 72 5 641

RISE TIME RATIO

% E

RR

OR

7

Propagation Delay and Line Length

Using the dielectric constant of alumina as 10 and the formula for propagation delay as:

if ε = 10 then Tpd = 0.1 nanoseconds/cm

Therefore, for a two inch conductor length, the maximum propagation delay would be:

2 inches x 2.54 cm/inch x .1nanoseconds/cm or 0.508 nanoseconds.

Since our signal lines are not terminated in the characteristic impedance of the transmissionline, there will be overshoot and ringing. However, if we restrict the line length to besufficiently short, then the signal will be still rising at time Td (see Figure 9) and thereflections will be part of the rising edge (and also falling edge). With longer lines, the rise ofthe signal will be completed and reflections will appear as overshoot and undershoot. The

maximum unterminated line length results in a maximum 15% ringing2, if the line length isheld to:

where

Tr = rise time

Tpd = propagation delay of line per unit length

This assumes that there is no capacitive loading on the line. If capacitive loading is presentthen the Tpd term must be replaced by T'pd which is calculated as follows.

2. Kaupp, H.R “Characteristics of Microstrip Transmission lines”, IEEE Transactions on Electronic Computers, Vol.EC-16, No.2, April 1967, pp.185-193

Tpd 0.0333 ε×= in nSec/cm

Lmax Tr2 Tpd×-------------------<

T′pd Tpd 1 CdCo-------+

×=

Co Capacitance Length⁄=

Cd Capacitive-loading Length⁄=

8

For example, if an 8 mil thick dielectric tape and an 8 mil conductor line width are used thenthe capacitance per unit length is approximately 2.5 pf/cm or 6.35 pf/inch (see Figure 7). Ifthe circuit has six 3 pf loads plus an output load of 10 pf at the receiving end 2 inches fromthe driver then:

This is a conservative requirement to meet for most of the MCM signals since the maximumelectrical signal length is 1.5" - 2". For those signals that are critical, a Spice analysis isperformed, as well as insuring that the signal is routed over ground planes to insuremicrostrip performance. Described below in Figure 8 are typical characteristic impedanceefor several dielectric thicknesses. Spice analysis waveforms are shown in Figure 9 for theR4400SC MCM for the SRAM data address lines.

Figure 8 - Typical Characteristic Impedances

T′pd 0.25nsecs 1

18 10+( )5.08

-----------------------

2.5-----------------------+

×=

0.25nsecs 1.79×=

0.447n ssec=

Lmax3nsecs

2 0.447nsecs×------------------------------------< 3.35in=

Zo 60

εγ

-------- ln⋅ 4 2h×0.67π 0.8w t+( )---------------------------------------=

70605040302010

0 4 8 12 16 20

41.6

Dielectric Thickness h (mils)

Ch

ara

cte

ristic

Imp

ed

an

ce

Zo

(Ω)

h

εv

W

th

Calculated Data

9

Figure 9 - Spice Analysis WaveformsCrosstalk

The crosstalk between two parallel lines 2 inches long on the same conductor layer isapproximated for a 3 nsec rise time as shown in Figure 10. The results indicateapproximately a 175mv crosstalk level for an 8 mil line and 8 mil space with an 8 mildielectric. The capacitance and inductive coupling are approximately 0.4 pf/cm and 1 nH /cmrespectively. The crosstalk levels are highly dependent on the driver chip output impedanceand loading at the far end. Therefore, the chips must be modeled using the specific deviceand characteristic output impedance with a Spice simulator.

The physical layout was also designed to ensure that adjacent layer signal lines areorthogonal. If there are layers that are not separated by power and ground, two levels away,then they will routed so they are not parallel to minimize coupling.

Figure 10 - Cross Talk vs Dielectric Thickness

Output of Micro

Shorter LengthsTo SRAMAddresses

Td

Longer LengthsTo SRAMAddresses

<< 15%

<< 15%

300

250

200

150

100

50

0

5 8 12 1810Dielectric Thickness h (mils)

CR

OSS

TALK

, mV

(FA

R E

ND

)

8 MIL LINE8 MIL SPACE

CALCULATED CROSS TALK

10

Decoupling Capacitors

The MCM’s circuits can cause significant switching current transients which can cause VCC

to drop. When 3.3 volt logic signal levels change 2.5 volts (from a high to a low), the outputbuffer circuit effectively sees a 40 ohm transmission line impedance. This change in voltagecauses an instantaneous output high current change of 62.5 mA. If sixty-four bufferschanged simultaneously, the current demand on the power supply would be 4 amps. If lessthan a 0.1V VCC drop is specified, then we can solve for the decoupling capacitor by using:

Twenty-three .01µF 0603 ceramic capacitors were used in the MCM for decoupling.

Power Distribution

The conductor material for high temperature cofired system is tungsten, with a sheetresistivity of 15 milliohms per square maximum. Due to the sheet resistivity of tungsten, theresistance of power and ground must be considered in the design layout stage to insure thatthere will not be excessive voltage drops within the MCM.

Since we provided for fault isolation, in the event that a die shorts out, we routed at least oneseparate power and ground pin to each row of SRAM die and to the microprocessor. Thisalso has the beneficial effect of reducing the inductance due to the paralleling of severalpower and ground pins. For the R4400SC, the D.C. current was approximately 3 Amperes.To obtain less than a 1% D.C voltage drop required the trace resistance to be R = V/I or33mV/3A = 11 milliohms. Evenly splitting the resistance between power and ground yields5.5 milliohms. Thus, the trace resistance between the power pin and the wirebond pad mustbe less than 5.5 milliohms to eliminate excessive voltage drops. To achieve this requirementmultiple power and ground traces were used on the R4400SC microprocessor die. There areapproximately 100 power and ground pins used to distribute the heavy currents within thechip.

Thermal ManagementUsing a simplified MCM layout for worst case thermal analysis the results are shown inFigures 11 through 13 and Table I. The simplified finite element model does not show thatthe die sits in a cavity. This reduces the ceramic thickness to 48mils and an extra “Phantom”die is modeled to make the analysis symmetric. Thus, our thermal resistance numbers arevery conservative.

I C dvdt------×=

C 4 3.0nsecs0.1V

--------------------× 0.12µF= =

C I dtdv------×=

C 0.12µF=

∴

11

Figure 11 - Simplified Module layout for Thermal Analysis

Figure 12 - R4400SC MCM, Finite Element Analysis, Thermal Gradients Top View

2.5”

1.5”

0.5 watts each (12x)

0.3 0.7 1.25 1.802.20

1.2

0.75

0.3

TYPICAL DIE INTERFACE

20 Mils Silicon

2 Mils Conductive

64 Mils Alumina

14 Watts

“Phantom Chip”

Silver Epoxy

12

Figure 13 - R4400SC MCM Finite Element Analysis Cross Sectional Thermal Gradients

Mechanical

Introduction

High temperature cofired ceramic (HTCC) technology offers the lowest risk solution to theR4400SC MCM and is by far the most mature of the emerging MCM technologies. Theanalysis of thermal constraints, routing density and electrical requirements includingmaximum signal frequency and minimum rise times reveals that all are within HTCCcapability. Additionally, the die rework was a major concern and “Know Good Die” were notavailable. HTCC is more forgiving to die rework than is organic or silicon substrates.

Package Construction

The packages is constructed with eight 8 mil thick tape layers resulting in a nominal basethickness of 64 mils. The Microprocessor is centrally located in a cavity approximately 16mils below the top surface. This improves wirebonding and die thermal conductivity. Anintegral substrate provides the interconnect between all die and I/O pins. A two tier wirebonding shelf enabled 1 mil aluminum wire bonding to the over 400 pads on a 4.3 mil pitch ofthe R4400 microprocessor die. A 60 mil high cover seal ring is brazed to the aluminaproviding the component cavity. All I/O pins are fabricated from Alloy 42 and brazed to thealumina utilizing “dog leg” form. The opposite end of the leads will be attached to anon-conductive alumina ceramic tie bar, to protect the leads from damage in assembly andtest. A 15 mil thick cover lid with a 6 mil step is seam welded to the kovar ring frame toprovide a hermetic seal.

.36°C .36°C

13

Seal Ring and Seal Ring Metallization

The package seal ring material is kovar in accordance with MIL-PRF-38534, Type A. Theseal ring dimensions will be 30 mils wide by 60 mils high with a +/- 2 mil tolerance. The sealring (Figure 14) has an internal corner radius of 30 mils and an external radius of 60 mils.The seal ring metallization will be 70 mils wide and internal and external radii of 60 mils toensure adequate braze fillets at the corners. This modified geometry has been qualified toaircraft vibration and shock levels with no failures.

Figure 14 - 1608 Package Construction

Package Leads

The lead frame material is Alloy 42 in accordance with MIL-PRF-38534, Type A. Due to thelead forming anticipated, changes are offered to ensure lead integrity during forming. Theleads are 10 mils wide by 6 mils thick and brazed to the alumina in a “dog leg” form on a 18mil by 45 mil braze pad. This configuration ensures adequate braze fillets around the entirelead.

Lid design and deflection

Detailed analysis and empirical testing was performed on the final lid design. The 1608MCM has a nickel plated kovar lid with dimensions 2.315” long by 1.315” wide . The etchedkovar lid has a base thickness of 20 mils . The perimeter has a 5 mil flange to provide forseam sealing the hermetic enclosure. Aeroflex uses Rome Air Development Center (RADC)technical report TR-81-382 – “Microcircuit Stress Analysis” as the basis for all lid deflectioncalculations . This is supplemented by finite element analysis and empirical testing. Usingspecial fixtures and gagues, the actual lid deflection is measured under helium leak test

SEAL RING

.015

.018 X .045 CONTACT PADS

.020 TYP.045

.060 R

.030 R

.175 MAX

.064

.135.030

.010

.050 TYP

.010

.006

LID ETCHED DOWN TO .005 FOR SEAM WELDING

Detail A

See Detail A

µPDie

Cavity

.048

14

pressures to validate the lid design and analysis. Table III below lists the deflectionresults versus bomb pressure encountered during fine and gross leak testing perMIL-STD-883. The worst case minimum internal headroom was 20 mils. Thus, a bombpressure of 15 PSIG was selected to allow a minimum two times safety margin. If thedeflection analysis did not meet a 2x safety factor, then ceramic or gold plated kovarspacers would be incorporated into the design. During die attach the spacers would beepoxied or brazed on the top layer of the MCM package.

Obstacles, Obsolescence, and Solutions

Introduction

After our first die supplier in early 1993 was having difficulty producing the R4400microprocessor die, Aeroflex was faced with developing multiple and other backup diesources. Fortunately for the project the MIPS R4400 computer architecture was widelyavailable from ten vendors and four were willing to sell die. This accelerated ourdevelopment of a COTS philosophy prior to Dr. Perry’s edicts in 1994 to use commercialtechnology in military systems.

Component Obsolescence – A Proactive Approach

Aeroflex Circuit Technology's (ACT) MIPS microprocessor product line includes a unique

Three-Pronged Approach3 to the component obsolescence issues plaguing the military

and high-reliability markets:

First is to provide cutting edge technology to their target markets Second is to increase product life span by continually enhancing performance

while retaining the footprint and pinout compatibility. Third is to provide for an orderly migration path to future products.

The GOAL: Take advantage of technological advances in the commercial and industrialcomponent environment.

Reduce costs at both the component and system level. Gain access to, “Cutting Edge Technology!” Reduce component and system lead times.

The REALITY: Accelerated exposure to component obsolescence for major OEM’s anda new acronym DMS (Diminished Manufacturing Sources).

Table III - Lid Deflection vs Leak Test Bomb Pressures

Bomb Pressure (PSIGCalculated deflection

(Inch)Actual Deflection

(Inch)

15 0.007 0.009

30 0.015 0.0155

3. Terlizzi, Tom and Ramos, Frank “Component Obsolescence-A Proactive Approach” COTS-CON 2000

15

COTS products Life Cycles prove to be incompatible with military program Life Cycles andfunding requirements; obsolescence increases.

As an example of this reality, at a recent DMS conference an OEM complained about theresults of a redesign effort to replace obsolete components. Within a year 50% of the newreplacement components had obsolescence problems before commencing production.

Aeroflex in 1993 developed a long-term plan for this MIPS processor MCM with thefollowing criteria:

Mechanical: Select a package style and footprint Electrical: Select a pinout with expansion capabilities and also upward

compatible Functional: Evolve the MCM from 256K to 1M of L2 cache

Controlling costs and lead-time by design re-use is always one of the primary concerns.

We attempt to leverage investments in by keeping the footprint identical:

Package Tooling Test Socket tooling Test Software Customer’s next level assembly experience, lead bend fixtures and tooling

Up screening of suitable commercially available product provides cutting edge technologyquickly to the military OEM:

Military Temperature Testing

Environmental Screening; including Burn in

IE. 4400 179 Pin CPGA 4700 179 Pin CPGA

Additionally, by providing the Military OEM product support by “evaluation adapters” whichprovide a means to evaluate performance increases in their system with real softwareinstead of vague benchmarks (see Figure 15 ).

In 1997 Aeroflex made a strategic decision to follow the MIPS Technologies Roadmaps ascommercial applications would dictate future MIPS availability.

MIPS architecture had 50% of the total RISC market share. Also, MIPS was the highestgrowth RISC architecture (1997,1998 & 1999) and the only true 64-bit architecture in volumeproduction at the time.

Even as we speak, Intel and AMD are now just shipping their first 64 bit machines (early2003).

16

Figure 15 - “Evaluation Adapters”

ObsolescenceIn 1997 we were faced with a major unannounced microprocessor die obsolescence due toa die shrink. The die vendor failed to notify us of their change. With many cofired packagesin our stockroom and critical customer delivery schedules at risk a solution was urgentlyneeded.

Our solution was to develop a unque interposer which did not degrade the thermalcharacteristics of the microprocessor die. Our sister division, MIC Technology came to therescue by developing, very quickly, a “picture frame” thin film multilayer on ceramicinterconnect as shown in Figure 16 and 17. This enabled us to get back in to production andwe are still shipping these parts today in 2003.

We have been fairly sucessful at die banking and last time MCM buys for our OEMs and thegovernment but it always a difficult last minute decsion for all of us.

Figure 16 - Magnified View of Aeroflex’s MIC Technologies Thin Film(“Picture Frame”) Interposer

ACT-5260PC-P10-POD

1 mil Aluminum wire from R4400 microprocessor die to interposer

1 mil gold wire

Two tieded wirebonding shelf and pads on MCM cofired package - top layer

17

Figure 17 - Thin Film “Picture Frame” Interposer

In 1999, to further extend the life of the MIPS microprocessor MCMs with L2 cache weintroduced the ACT-5271SC. This MCM was co-developed with one of our major OEMs,Quantum Effect Designs (QED), and MIPS Technologies. The 5271SC MCM is shown inFigure 18. QED was later acquired in 2000 by PMC-Sierra. We have continued our licensingagreement for military and high rel market which was started in 1997 with QED.

Spin-off products from the initial MCM products were ACT5260PC and ACT7000SC. Themicroprocessor die, phase lock loop components, decoupling capacitors are all packaged ina 208 CQFP as shown in Figure 19. All these products are footprint and pinout compatible.The only major difference is the core voltage and that the ACT7000SC has L2 cache onboard the microprocessor die. Figure 20 shows the ACT7000SC in a cavity down lead bendformat on a COTS VME Board.

Figure 18 - ACT5271SC MCM

Thin Film “Picture Frame” Interposer

2 MB SC: (Sync Burst Cache RAM)

CPU Cycle FIFO: 2 FPGACache TAGRAM

Control CPLD

ConfigurationSerial PROM: FPGA

MIPS uP: RM5261PLL CLK Driver

18

Figure 19 - ACT5260PC MCM

Figure 20 - Star 7 MVP Militarized COTS VME Bus Single Board Computer

ACT7000SC with cavity down commercial foot-print

19

ConclusionAeroflex has developed a COTS approach to Military Microprocessors MCMs for over adecade using a unique synergy of partners as shown in Figure 21. The long product lifecycles of Military systems, recently evidenced by the 50th anniversary of the Boeing B-52bomber, require a different strategy. While there have been many obstacles andobsolescence issues encountered over the last decade, solutions are generated by usingelectronic design, MCM packaging and business skills. Each of these aspects are importantbut must be combined for the total economic solution.

Figure 21 - Synergy of Partners

Summary

1. Robust MCM packaging platform HTCC provides many solutions to electrical, thermal and manufacturing requirements

for Military/Aerospace applications. MCM technology offers technology insertion in same footprint

2. Provide Cutting Edge Technology to our Customers Strategic arrangements and licensing agreements provides access to the latest

commercial technology Robust MIP Technologies RISC computer architecture provides cost, power savings,

and high performance. Hi-Rel Products available within months of the introduction of equivalent Commercial

product Provide technical support and software tools using widely available commercial

development packages Evaluation adapters allow software benchmarks early in program

20

3. Increase Product Life Span By: Maintaining IC Package Footprint and Pinout Compatibility to existing products while

providing Higher Performance in next generation products Protect large investments in software and application code and quality software testing

4. Provide an Orderly Migration Path to the Future CPU products at various points along the Price/Performance curve Redesign when you need to; Not because you’re forced to by component

AcknowlegementThe author would like to thank the following people for their valuable insight, help andpatience: Paul Carment and Joe LaFiandra.

In addition thanks are due to all at PMC-Sierra, MIPS Technologies, and Aeroflex CircuitTechnology since the accomplishments summarized in this paper could only result from ateam effort.