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Course Topics - Outline

Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 – Behavioral modeling B Lecture 7 – Behavioral modeling C Lecture 8 – Data flow modeling Lecture 9 – Gate Level modeling Lecture 10 – Tasks and Functions Lecture 11 – Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 - Switch Level modeling

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Lecture 9 - Gate Level modeling

● Gate types

● Gate Primitives Logic Symbols

● Primitives Functionality

● Primitives Truth Tables

● Gate Delays

● Gates Instantiation

● Array of Instances

● Exercise 9

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Introduction

Verilog models at the gate level consists of directly specifying the interconnections of fundamental logic elements (AND, OR, etc.).

Description of a module at the gate level consists of the declarations (header, ports, variables) and a series of instantiations of the base logic elements. Through the instantiations, the wiring of the module is specified.

The format of a Gate-Level Instantiation is:

<gate_type> <i_name> (<out_name>, <in_name_list) ;

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Gate Types

A logic circuit can be specified in terms of gates.

Verilog supports basic logic gates as predefined primitives. The available logic elements are:

and, nand, or, nor, xor, xnor, not, buf, notif, bufif

and, nand, or, nor, xor, xnor have multiple inputs and a single output

buf & not have a single input and a single output

notif, bufif have a single input, single output and a tri-state control input

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Gate Primitives Logic Symbols

i1

i2 out

and nand or nor

xor xnor buf not

in

ctrl

bufif0 notif0 notif1

i1

i2 out

i1

i2

i1

i2 out out

i1

i2 out

i1

i2 out in in out out

in out out

ctrl ctrl ctrl

in out in out

bufif1

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Primitives Functionality

The functionality of these basic logic gates are self-explanatory with the exception of buf, notif & bufif.

buf is simply a non-inverting buffer gate. It is transparent from a logical sense but may be required for implementation.

notif & bufif are tri-state versions of the not & buf gates. These gates have a extra control line which enables the gate when true and places the gate into the high-impedance Z state when false.

Inputs can take values 0, 1, X, Z ; output depends on truth table.

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Primitives Truth Tables

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Primitives Truth Tables - continue

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Primitives Truth Tables - continue

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Gate Delays

There are three Gate Delay types:

Rise delay is associated with a gate output transition to 1 from another value.

Fall delay is associated with a gate output transition to 0 from another value.

Turn-off delay is associated with a gate output transition to the high impedance value (Z) from another value.

t_rise

t_fall

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Gate Delay Specifications

If one delay value is specified – its value is used for all gate’s transitions

If two delay values are specified – they refer to gate’s rise and fall delay values respectively

If three delay values are specified – they refer to gate’s rise, fall and turn-off delay values respectively

Default gate delay value is zero

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Gate Delay Specifications cont.

// Delay is equal to trans_delay for all transitions nand #(trans_delay) g1 (out, in1, in2) ; // Rise and Fall delays are specified and #(rise_delay, fall_delay) g2 (out, in1, in2) ; // Rise, Fall and Turn-off delays are specified bufif0 #(rise_delay, fall_delay, turn-off_delay) b1(out, in, control) ;

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Primitive Instances Examples

Instances of primitives may include delays:

Gate Delays Examples:

Buf b1(a, b) ; // zero delay

buf #3 b2(c, d) ; // delay of 3 time units

buf #(4,5) b3(e, f) ; // rise=4, fall=5

Bufif1 #(3,4,5) b4(k, l, ctrl) ; // rise=3, fall=4, turn-off=5

buf #(3:4:5) b5(g, h) ; // min-typ-max

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Example - Half Adder

module half_adder(Sum, Carry, A, B) ;

input A, B ;

output wire Sum, Carry ;

xor #2 U1 (Sum, A, B) ;

and #1 U2 (Carry, A, B) ;

endmodule

Assuming: • XOR: 2 t.u. delay • AND: 1 t.u. delay

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min. / typ. / max. Delay Values

Verilog provides an additional level of control for each type of delay mentioned above.

For each type of gate delay – rise, fall and turn-off, three values, min, typ and max can be specified.

Any one value can be chosen at the start of the simulation.

min. typ. and max. values are used to model devices whose delays vary within minimum and maximum range due to IC fabrication process variations. Example: and #(1:2:3, 2:3:4) my_and(out, in1, in2) ; // rise: 1-min,2-typ,3-max. fall: 2-min,3-typ,4-max.

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Simulator support for min / typ / max delays

Simulator provides delay mode control through command-line options to alter the delay values.

You can control what type of delay use for specific simulation using following flags:

-maxdelays Select maximum delays for simulation

-mindelays Select minimum delays for simulation

● Typical delays is a default, you should not use any flag.

For example for maximum delays use:

% irun <file_name> -access rwc -maxdelays -gui

for maximum delays use:

% irun <file_name> -access rwc -mindelays -gui

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Gates Instantiations

Gate-Level Instantiation format:

<gate_type> <i_name> (<out_name>, <in_name_list) ;

wire out, in1, in2, in3 ;

and my_and (out, in1, in2) ; // 2-input AND Gate

nand gate1 (out, in1, in2) ; // 2-input NAND Gate

or gate2 (out, in1, in2) ; // 2-input OR Gate

nor gate3 (out, in1, in2) ; // 2-input NOR Gate

xor gate4 (out, in1, in2) ; // 2-input XOR Gate

xnor gate5 (out, in1, in2) ; // 2-input XNOR Gate

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Gates Instantiations cont.

// More than 2 inputs:

and U3 (out, in1, in2, in3) ; // 3 input AND Gate

or q2 (out, in1, in2, in3) ; // 3-input OR Gate

// Gate instantiation without instance name

nand (out, in1, in2) ; // This is also a legal instantiation

wire out, in, ctrl ; // output, input, 3’S control

not my_not(out, in) ; // Inverter

notif1 q4 (out, in, ctrl) ; // Tri-state Inverter

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XOR Gate Implementation

module my_xor(out, a, b) ;

input a, b ;

output wire out ; wire abar, bbar, t1, t2

not invA(abar, a) ; not invB(bbar, b) ;

and and1(t1, a, bbar) ;

and and2(t2, b, abar) ;

or or1(out, t1, t2) ;

endmodule

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Example - 2-to-1 Multiplexer

out

2-to-1

Mux

i0

i1

sel

module mux_2 (out, i0, i1, sel) ; input i0, i1, sel ; // input & output ports output out ; wire x1, x2, x3 ; // internal nets or (out, x2, x3) ; // form output and (x2, i0, x1) ; // i0 sel’ and (x3, i1, sel) ; // i1 sel not (x1, sel) ; // invert sel endmodule

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Array of Primitive Instances

For situations when repetitive instances are required, Verilog allows an array of primitive instances to be defined.

A smart and careful use of such array instantiations often leads to compact design descriptions.

A typical array instantiation has the form and gate [7:4] (a,b,c) ; where a, b, and c are 4 bit vectors.

● The above instantiation is equivalent to combining the following 4 instantiations:

and gate [7] (a[3], b[3], c[3]), gate [6] (a[2], b[2], c[2]), gate [5] (a[1], b[1], c[1]), gate [4] (a[0], b[0], c[0]) ;

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Array of Primitive Instances cont.

The assignment of different bits of input vectors to respective gates is implicit in the basic declaration itself.

A more general instantiation of array type has the form: and gate[M : N](a, b, c) ;

Where M and N can be expressions involving previously defined parameters, integers and algebra with them.

The range for the gate is 1+ (M-N) ;

M and N do not have restrictions of sign ; Either can be larger than the other.

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Array of instances cont.

The instances differ from each other only by the index of the vector to which they are connected. Example: wire [7:0] out, in1, in2 ; nand n_gate [7:0] (out, in1, in2) ; /*basic gate instantiations */

// This is equivalent to the following 8 instantiations:

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Array of instances cont.

nand n_gate [7:0] (out[0], in1[0], in2[0]) ;

nand n_gate [7:0] (out[1], in1[1], in2[1]) ;

nand n_gate [7:0] (out[2], in1[2], in2[2]) ;

nand n_gate [7:0] (out[3], in1[3], in2[3]) ;

nand n_gate [7:0] (out[4], in1[4], in2[4]) ;

nand n_gate [7:0] (out[5], in1[5], in2[5]) ;

nand n_gate [7:0] (out[6], in1[6], in2[6]) ;

nand n_gate [7:0] (out[7], in1[7], in2[7]) ;

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Exercise 9

Part 1 Design and test the Carry Look-ahead Adder, using Verilog Primitives xor, and, or. Utilize array of gates and use internal wire vectors in order to minimize code size. Buffer carry-in signal with buf gate.

Part 2 Implement 1-bit Full Adder, using Verilog Primitives xor, and, or having min/typ/max rise/fall delay times.

Part 3 Design a Byte Comparator, using Array of 2-input xor primitives, 8-input or primitive and notif1 buffer, enabled by en input signal.