CPU Design ProjectCPU Design ProjectChristopher BrownChristopher Brown

Fall 2010, ELEC 5200Fall 2010, ELEC 5200

OverviewOverview

Multi-cycle processorMulti-cycle processor

16-bit instructions16-bit instructions

16 registers16 registers

Intel-style instruction setIntel-style instruction set

RegistersRegisters

AT - Assembler TemporaryAT - Assembler Temporary

NULL - Readonly, always 0x0000NULL - Readonly, always 0x0000

FULL - Readonly, always 0xFFFFFULL - Readonly, always 0xFFFF

R0 to R6 - General purpose, maintained R0 to R6 - General purpose, maintained across subroutinesacross subroutines

T0 to T3 - General purpose, not T0 to T3 - General purpose, not maintained across subroutinesmaintained across subroutines

SP - Stack pointer, for use with pseudo-SP - Stack pointer, for use with pseudo-instructions such as push and popinstructions such as push and pop

IP - Instruction pointer, always points to IP - Instruction pointer, always points to the next instructionthe next instruction

DecDec HexHex NameName

00 0x00x0 ATAT

11 0x10x1 NULLNULL

22 0x20x2 FULLFULL

33 0x30x3 R0R0

44 0x40x4 R1R1

55 0x50x5 R2R2

66 0x60x6 R3R3

77 0x70x7 R4R4

88 0x80x8 R5R5

99 0x90x9 R6R6

1010 0xA0xA T0T0

1111 0xB0xB T1T1

1212 0xC0xC T2T2

1313 0xD0xD T3T3

1414 0xE0xE SPSP

1515 0xF0xF IPIP

Instruction SetInstruction Set

Jumps - JMP, JG, JNLE, JGE, JNL, JL, JNGE, JLE, Jumps - JMP, JG, JNLE, JGE, JNL, JL, JNGE, JLE, JNG, JE, JNEJNG, JE, JNE

Memory - MOVMemory - MOV

Arithmetic - ADD, SUBArithmetic - ADD, SUB

Bitwise - XOR, AND, ORBitwise - XOR, AND, OR

Other - NOP, HLTOther - NOP, HLT

JumpsJumps8-bit relative 8-bit relative operandoperand

Flow determined Flow determined by Sign, Ovrflw, by Sign, Ovrflw, and Zero control and Zero control flagsflags

11 varieties:11 varieties:

1 1 unconditionalunconditional

6 conditional6 conditional

4 pseudo4 pseudo

DescriptionDescription ConditionCondition

JMPJMP JumpJump TRUETRUE

JGJG Jump if greater (>)Jump if greater (>) Sign == Ovrflw && !ZeroSign == Ovrflw && !Zero

JNLEJNLE Jump if not less than or equal Jump if not less than or equal (not <=)(not <=) Sign == Ovrflw && !ZeroSign == Ovrflw && !Zero

JGEJGE Jump if greater than or equal Jump if greater than or equal (>=)(>=) Sign == OvrflwSign == Ovrflw

JNLJNL Jump if not less than (not <)Jump if not less than (not <) Sign == OvrflwSign == Ovrflw

JLJL Jump if less than (<)Jump if less than (<) Sign != OvrflwSign != Ovrflw

JNGEJNGE Jump if not greater or equal (not Jump if not greater or equal (not >=)>=) Sign != OvrflwSign != Ovrflw

JLEJLE Jump if less than or equal (<=)Jump if less than or equal (<=) Sign != Ovrflw || ZeroSign != Ovrflw || Zero

JNGJNG Jump if not greater than (not >)Jump if not greater than (not >) Sign != Ovrflw || ZeroSign != Ovrflw || Zero

JEJE Jump if equal (==)Jump if equal (==) ZeroZero

JNEJNE Jump if not equal (!=)Jump if not equal (!=) !Zero!Zero

MemoryMemory

Uses register indirect addressing onlyUses register indirect addressing only

MOV (srcR), destRMOV (srcR), destR

Loads the contents of memory at the Loads the contents of memory at the address stored in srcR to the register address stored in srcR to the register specified by destR.specified by destR.

MOV srcR, (destR)MOV srcR, (destR)

Stores the contents of srcR to the memory Stores the contents of srcR to the memory address stored in destR.address stored in destR.

ArithmeticArithmetic

ADD and SUBADD and SUB

2 variants of each2 variants of each

ADD/SUB regR, destRADD/SUB regR, destR

Add or subtract the contents of regR from destR, Add or subtract the contents of regR from destR, storing the result in destR.storing the result in destR.

ADD/SUB immed8, destRADD/SUB immed8, destR

Add or subtract immed8 from destR, storing the Add or subtract immed8 from destR, storing the result in destR.result in destR.

Updates Sign, Ovrflw, and Zero control flags.Updates Sign, Ovrflw, and Zero control flags.

BitwiseBitwise

XOR, AND, and ORXOR, AND, and OR

XOR/AND/OR regR, destRXOR/AND/OR regR, destR

Performs a binary operation between regR Performs a binary operation between regR and destR, storing the result in destR.and destR, storing the result in destR.

Updates Sign and Zero control flags.Updates Sign and Zero control flags.

OtherOther

NOPNOP

It does nothing.It does nothing.

HLTHLT

Puts the control unit into a halted statePuts the control unit into a halted state

The only way to continue execution is The only way to continue execution is through a resetthrough a reset

Pseudo-InstructionsPseudo-Instructions

PUSH regRPUSH regR

SUB 1, SPSUB 1, SP

MOV regR, (SP)MOV regR, (SP)

POP regRPOP regR

MOV (SP), regRMOV (SP), regR

ADD 1, SPADD 1, SP

RETRET

MOV (SP), IP ; POP IPMOV (SP), IP ; POP IP

ADD 1, SPADD 1, SP

CALL relM8CALL relM8XOR AT, XOR AT, ATADD IP, ATADD 4, ATADD IP, ATADD 4, ATSUB 1, SP ; ATSUB 1, SP ; PUSH ATMOV AT, PUSH ATMOV AT, (SP)JMP relM8(SP)JMP relM8

Data-PathData-Path

Control UnitControl Unit

Finite-state-machineFinite-state-machine

Moore machine - Outputs depend solely on the Moore machine - Outputs depend solely on the current statecurrent state

8 unique states8 unique states

Also maintains 3 internal flags: Sign, Ovrflw, Also maintains 3 internal flags: Sign, Ovrflw, and Zeroand Zero

Control UnitControl Unit

Questions?Questions?