cs1104-14

CS1104 Computer Organizationhttp://www.comp.nus.edu.sg/~cs1104Aaron Tan Tuck ChoySchool of ComputingNational University of Singapore

Lecture 14: Introduction to Algorithmic State Machines (ASM)Large Digital SystemsTop-Down ApproachController and Data ProcessorFlowchartsASM ChartsComponents of ASM ChartsASM Charts: An ExampleRegister OperationsTiming in ASM Charts

Lecture 14: Introduction to Algorithmic State Machines (ASM)

Lecture 14: Introduction to Algorithmic State Machines (ASM)ASM Charts => Digital SystemASM Charts => ControllerASM Charts => Architecture/Data ProcessorImplementing the ControllerWith JK Flip-flopsDecoder + D flip-flopsOne Flip-flop per StateMultiplexersPLA/ROM

Lecture 14: Introduction to Algorithmic State Machines (ASM)

Large Digital SystemsIn both combinational and sequential circuit design:small circuits via gate-level design (truth tables, K maps, etc)large circuits via block-level design (MSI components, etc.)However, larger digital systems need more abstract and systematic design techniques.One such systematic design method has the following characteristics:top-down approachseparation of controller from controlled hardwaredevelop an overall architecture (at block levels) before proceeding into the details of hardware.

Large Digital Systems

Top-Down ApproachTop-down approach is immensely important for large complex system (whether hardware, software, or manual systems).Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution.Steps for a top-down design procedure:Specify the problem clearly (at global/top level without unnecessary details).Break the problem into smaller sub-problems.Repeat the process until subproblems are small enough to be solved directly (implementable).

Top-Down Approach

Top-Down ApproachCorresponds to goal-directed approach.State goal, then find sub-goals to solve main goal.Repeat until sub-goals are directly solvable.

Top-Down Approach

Controller & Data ProcessorDigital systems are typically processors of information.They store data through flip-flops, registers and memory, and process them using combinational circuits like adders, multipliers, etc.These processing may pass through complicated sequences.

Controller & Data Processor

Controller & Data ProcessorA digital system consists of two componentsA control algorithm (controller) andAn architecture (data processor)


Controller & Data ProcessorSeparation of the controller operations from the data processing operationsControl operations give commands that direct the data processing operations to accomplish the desired tasks.Data processing operations manupulates the data according to requirements. A mechanical analogy: Automobile.Car (data processor): transports people from one location to another.Driver (controller): gives instructions to car to achieve objective.


FlowchartsFlowcharts: a tool for precise description of algorithms/procedures.Specify tasks to perform and their sequencing.Main symbols:Operation box: contains tasks/operations to perform.Decision box: alternative actions based on decisions to be taken.Arrows: indicate appropriate sequencing.

Flowcharts

FlowchartsAn operation box is rectangular in shape, and is used to specify one or more subtasks to be performed. It has at most one entry point and one exit point.

Flowcharts

FlowchartsA decision box is diamond-shaped. It has one entry point and multiple (but mutually exclusive) exit points.

Flowcharts

FlowchartsSequential flow: simplest type of sequencing; tasks are done in sequential order.An example: Eating a 3-course Western meal.Boxes are connected by lines with arrows. Lines without arrows are sometimes used. In the absence of arrows, the default flow direction is top-to-bottom and left-to-right.

Flowcharts

FlowchartsIteration: some tasks/operations may be repeatedly/iteratively done. This is achieved through the loop-back in the flowchart.Decision box is used to determine when to terminate the loop.

Flowcharts

FlowchartsAn example: Eating a Western meal in oriental style.

Flowcharts

FlowchartsFlowcharts can be used to implement complex decisions.

Flowcharts

ASM ChartsAlgorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems.Major differences from flowcharts are:uses 3 types of boxes: state box (similar to operation box), decision box and conditional boxcontains exact (or precise) timing information; flowcharts impose a relative timing order for the operations.From the ASM chart it is possible to obtainthe controlthe architecture (data processor)

ASM Charts

Components of ASM ChartsThe state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle.

Components of ASM Charts

Components of ASM ChartsThe decision box is diamond in shape. It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed.


Components of ASM ChartsThe conditional box is represented by a rectangle with rounded corners. It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box.


ASM Charts: An ExampleAn example:A is a register; Ai stands for ith bit of the A register.A = A4A3A2A1E and F are single-bit flip-flops.

ASM Charts: An Example

Register OperationsRegisters are present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers.The register operations are specified in either the state and/or conditional boxes, and are written in the form:destination register function(other registers)where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers.

Register Operations

Register OperationsExamples of register operations:A BTransfer contents of register B intoregister A.A 0Clear register A.A A 1Decrement register A by 1.

Register Operations

Timing in ASM ChartsPrecise timing is implicitly present in ASM charts.Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle.A group of boxes which occur within a single clock cycle is called an ASM block.

Timing in ASM Charts

Timing in ASM Charts3 ASM blocks


Timing in ASM ChartsOperations of ASM can be illustrated through a timing diagram.Two factors which must be considered areoperations in an ASM block occur at the same time in one clock cycledecision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block)


Timing in ASM ChartsA = A4A3A2A1


ASM Chart => Digital SystemASM chart describes a digital system. From ASM chart, we may obtain:Controller logic (via State Table/Diagram)Architecture/Data ProcessorDesign of controller is determined from the decision boxes and the required state transitions.Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes.

ASM Chart => Digital System

ASM Chart => ControllerProcedure:Step 1: Identify all states and assign suitable codes.Step 2: Draw state diagram.Step 3: Formulate state table usingState from state boxesInputs from decision boxesOutputs from operations of state/conditional boxes.Step 4: Obtain state/output equations and draw circuit.

ASM Chart => Controller

ASM Chart => Architecture/Data ProcessorArchitecture is more difficult to design than controller.Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine:What registers to useHow they can be connectedWhat operations to supportHow these operations are activated.Guidelines:always use high-level unitssimplest architecture possible.

ASM Chart => Architecture/Data Processor

ASM Chart => Architecture/Data ProcessorVarious operations are:Counter incremented (A A + 1) when state = T1.Counter cleared (A 0) when state = T0 and S = 1.E is set (E 1) when state = T1 and A2 = 1.E is cleared (E 0) when state = T1 and A2 = 0.F is set (F 1) when state = T2.Deduce:One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment).Two flip-flops needed for E and F (e.g.: JK flip-flops).


ASM Chart => Architecture/Data Processor(A A + 1) when state = T1.(A 0) when state = T0 and S = 1.(E 1) when state = T1 and A2 = 1.


Implementing the ControllerOnce the state table is obtained, the controller can be implemented using one of these techniques.1. Traditional method: With JK flip-flops.design done at gate level.suitable for small controllers.procedure: prepare state table, use K-maps to obtain next-state/output functions.2. Decoder + D flip-flopssuitable for moderately large controllers.procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection.

Implementing the Controller

Implementing the Controller3. Multiplexersa more structured approach to implement controller.suitable for moderately large controllers.three level structure: first level consists of multiplexers that determine the next state of the register; second level is a register that holds the present state; third level has a decoder to provide separate output for each controller state.


Implementing the Controller4. One flip-flop per statealso known as One-Hot Spot Method of ASM synthesis.procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialised.5. PLA/ROMhighly regular approach.ROM approach uses a very simple table lookup technique but suffers from large number of dont care states.PLA can handle dont care states well but design method is still at gate-level.


Implementing Controller:With JK Flip-flopsState table obtained from ASM chart:Corresponding state table using JK flip-flops:

Implementing Controller: With JK Flip-flops

Implementing Controller:Decoder + D Flip-flopsThe flip-flop input functions can be obtained directly from the state table by inspection.This is because for the D flip-flops, the next state = flip-flop D input.Decoder is then used to provide signals to represent different states.

Implementing Controller: Decoder + D Flip-flops

Implementing Controller:Decoder + D Flip-flopsGiven the state table: We can directly determine the inputs of the D flip-flops for G1 and G0. DG1 = T1.A2.A3 DG0 = T0.S + T1


Implementing Controller:Decoder + D Flip-flopsFlip-flop input functions: DG1 = T1.A2.A3 DG0 = T0.S + T1Circuit:


Implementing Controller:One Flip-flop per StateRequire n flip-flops for n states; each flip-flop represents one state. (Other methods: n flip-flops for up to 2n states.)

Implementing Controller: One Flip-flop per State

Implementing Controller:One Flip-flop per StateFormulae for next state can be obtained directly from state table:1.If there is only one line going into the state, then formula = input condition ANDed with the previous state.2.If there are more than one line, then formula = Ored of all the conditions found in (1).


Implementing Controller:One Flip-flop per StateState table:State diagram:Flip-flop input functions:DT0 = T2 + S'.T0DT1 = S.T0 + A2'.T1 + A2.A3'.T1 = S.T0 + (A2.A3)'.T1DT2 = A2.A3.T1


Implementing Controller:One Flip-flop per StateCircuit diagram below. To initialise to state T0, set flip-flop of T0 to 1 and clear the rest to zero.DT0 = T2 + S'.T0 DT1 = S.T0 + (A2.A3)'.T1 DT2 = A2.A3.T1


Implementing Controller:One Flip-flop per StateAlternative: Use Q' output for T0, and input function for T0 is complemented. To initialise, clear all flip-flops to zero.DT0 = (T2 + S'.T0)'DT1 = S.T0 + (A2.A3)'.T1 DT2 = A2.A3.T1


Implementing Controller:MultiplexersPurpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state.The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart.

Implementing Controller: Multiplexers

Implementing Controller:MultiplexersExample 1: Given the state table.Reformat the state table.


Implementing Controller:MultiplexersObtain multiplexer inputs:


Implementing Controller:MultiplexersDraw circuit:


Implementing Controller:MultiplexersExample 2:


Implementing Controller:Multiplexers


Implementing Controller: PLA/ROMSimilar to the design using D flip-flops and a decoder.The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flip-flops.

Implementing Controller: PLA/ROM

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cs1104-14