CSC 204 - Final Study Guide

8/10/2019 CSC 204 - Final Study Guide

1/12

CSC 204 FINAL - Ultimate Study Guidefvcproductions

> QUIZ 1

1. What is an interpreter?

a program that can analyze and execute a program line by line

2. Define translation as relates to virtual machines.

a program that translates a program written in one programming languageinto a functionally equivalent program in a different language without losingessence; binary translation is used with virtual machines so that the entireprogram is translated into a binary of another architecture

3. Define hardware.

the machines, wiring, and other physical, touchable components of acomputer or other electronic system.

4. Moore's law states that (use transistors to explain answer)

observation that over history of computing hardware the # of transistors inintegrated circuit doubles about every 2 years

5. MIPS stands for?

million instructions per second

> TEST 1

1. Explain in your own terms the following terms:

a. translator: converts program in 1 language to another oneb. interpreter: carries out a program instruction by instructionc. virtual machine: machine that does not actually exist

2. What is latency? a measure of the time delay experienced by a computer system

3. What is throughput? rate of production

4. Explain the idea behind RAID level 1 and how it is implemented. What is thedifference between RAID level 1 and RAID level 2?


2/12

RAID 1: An exact copy (or mirror) of a set of data on two disks. This is usefulwhen read performance or reliability is more important than data storagecapacity.

RAID 2: RAID2 stripes data at the bit (rather than block) level, and uses a

Hamming code for error correction. Extremely high data transfer rates arepossible.

5. Name the special purpose register that stores the address of the next instruction tobe fetched from memory. program counter

6. Name the special purpose register that is used to store the instruction while it isdecoded and executed by the processor. instruction register

7. Explain the Hamming code algorithm and how it is used as error correction code?Construct a Hamming code for memory 1111 0000 1010 1110 by adding the 5 clock bits.

Hamming code is a set of error-correction code s that can be used to detectand correct bit errors that can occur when computer data is moved or stored.Makes use of the concept of parity and parity bits, which are bits that are addedto data so that the validity of the data can be checked when it is read or after ithas been received in a data transmission. Using more than one parity bit, anerror-correction code can not only identify a single bit error in the data unit, butalso its location in the data unit.

8. List 4 of the 5 major components that are found in all computers.

Input, Output, Memory, Datapath (ALU), Control

9. In reference to Moores law, assume that in a certain point in time, a transistor on achip was .2 micron in diameter. How big will the transistor be in the next year model?

Moore said that the next generation computer will increase constantly withabout 4 times in terms of transistor number. So this next year chip will have 1 + .6or 1.6 times the number of transistors. The transistor area would be 2/1.6 or 1.25smaller than the previous years chip. Therefore, the size would be about 1.58microns if the last chip was .2 microns.

10. Explain the concept of a stored program computer.

A stored program computer is one in which the machine language programis stored in memory along with data, and the computer is able to manipulate bothprogram and data in identical ways.
http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Disk_mirroring


3/12

11. Draw a block diagram that illustrates the concept of a memory hierarchy. What is thefastest and most expensive memory in your hierarchy What is the slowest and leastexpensive memory in your hierarchy?

Fastest, Most Expensive Memory - registers

Slowest, Least Expensive Memory - tape

Block diagram:

Fastest SlowestCPU Registers, Cache, Main memory, Disk memory, Tape memory

12. Consider an operation with the single pipeline Von Neumann data path machine.Suppose that the loading ALU input registers take 10 nsec, running ALU takes 20 nsec,and storing the result back in the register takes 10 nsec. What is the maximum numberof MIPS this machine is capable of in the absence of pipelining?

Loading into register A takes 10 nsecLoading into register B takes 10 nsecComputation 20 nsecRestoring A+B into register = 20 nsecTotal = 60 nsec

1 instruction takes 60 nsecMIPS = millions of instructions per second = (1)/((60*10 -9)*(1/106)) = 16.666666667Therefore MIPS = 17

13. On computer 1, instructions take 10 nsec to execute. On computer 2, they all take 5nsec to execute. Can you say for certain that computer 2 is faster? Discuss?

No, because there are too many other factors that have to be taken intoconsideration like memory, hardware, RAM, etc.

> Quiz 3

1. True or False

a. Exactly one output of a decoder will be asserted for any input. True

b. A 4-input multiplexer, where each input is 32-bits, can be constructed from 32multiplexers, where each multiplexer has four 4-bit inputs. False

c. If the clock rate of a processor is too high, the memory elements (registers, etc.)will capture incorrect values emanating from the combinational logic (e.g. theALU). True

d. In a rising-edge triggered flip-flop, the data will enter the first latch when the clockrises and then enter the second latch when the clock falls. False


4/12

e. A narrow SRAM (many locations, each location containing a small number ofbits) will require fewer input pins than a wide SRAM (fewer locations, eachlocation containing more bits) with equivalent memory capacity.True

2. Use a diagram to show how a transistor inverter is used to implement

a. a NAND gateb. a NOR gate

3. Can you build a device that, logically, behaves like an OR gate from only AND and

NOT gates? If so, do so. If not, explain why not.

4. Outline the derived general method on how to implement a circuit for a Boolean

function?

1. Write truth table for function2. Provide inverters to generate complement of each input3. Draw AND gate for each term with 1 in result column4. Wire AND gates to appropriate inputs5. Feed output of all AND gates into an OR gate


5/12

5. Applying distributive law and de-Morgans law, show equivalency of the followingfunctions. Show circuit and truth tables for AB + AC and A(B+C).

6. Show how the AND function can be constructed from NOR gates?

> Test 2

1. True or False

a. Exactly one output of a decoder will be asserted for any input. True


6/12

b. A 4-input multiplexer, where each input is 32-bits, can be constructed from 32multiplexers, where each multiplexer has four 4-bit inputs. False

c. If the clock rate of a processor is too low, the memory elements (registers, etc.)will capture incorrect values emanating from the combinational logic (e.g. theALU). False

d. In a rising-edge triggered flip-flop, the data will enter the first latch when the clockrises and then enter the second latch when the clock falls. Falsee. A wide SRAM (many locations, each location containing a small number of bits)

will require fewer input pins than a narrow SRAM (fewer locations, eachlocation containing more bits) with equivalent memory capacity.False

f. DRAM cells need to be refreshed because 1) reading changes the voltage levelof the capacitor in a cell and 2) capacitors leak current. True

g. In an ALU, subtraction is performed by changing the sign (i.e. leftmost) bit of thesecond operand and then adding the operands. False

h. The fastest way to load a 32-bit constant on a MIPS 32-bit processor is to put theconstant within a single instruction. False

i. A synchronous bus has a line driven by a crystal oscillator. Truej. There are two ways to increase the bus bandwidth of a bus: decrease bus cycle

tie or increase data bandwidth. True

2. Circuits:

a. Use truth table to show that A = (A AND B) OR (A AND NOT B)

b. What is a comparator?

comparator is a device that compares two voltages or currents and outputsa digital signal indicating which is larger
http://en.wikipedia.org/wiki/Electric_currenthttp://en.wikipedia.org/wiki/Voltage


7/12

c. Give a circuit diagram for a a 4-bit word comparator?

3. What is the difference between a flip-flop and a latch as it relates to memorytechnology?

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous

or edge-triggered); the simple ones are commonly called latches. The word latch

is mainly used for storage elements, while clocked devices are described as flip-

flops.

4. Outline the derived general method on how to implement a circuit for a Boolean

function?



8/12

5. What is an ALU? Arithmetic Logic Unit

a. List the 3 parts of an ALU?

1. registers

2. control unit3. logic unit

b. By the use of a circuit diagram, outline a full adder and explain how it sums twoinputs and handles a carry?

6. Use diagrams:a. tri-state deviceb. non-inverting buffer


9/12

7. What is difference between:

a. SRAM, DRAM, and SDRAM?

- SRAM: Static random access memory uses multiple transistors, typically four

to six, for each memory cell but doesn't have a capacitor in each cell.

- DRAM:Dynamic random access memory has memory cells with a pairedtransistor and capacitor requiring constant refreshing.

- SDRAM: Synchronous dynamic random access memory takes advantage of theburst mode concept to greatly improve performance

b. ROMS, PROM, and EEPROM?

- The difference between a PROM and a ROM (read-only memory) is that a PROMis manufactured as blank memory, whereas a ROM is programmed during the

manufacturing process.

- PROM - (programmable read-only memory) is a memory chip on which data canbe written only once.

- EEPROM - (electrically erasable programmable read-only memory).Pronounced e-e-prom, an EEPROM is a special type of PROM that can be

erased by exposing it to an electrical charge.

8. List at least 3 categories of bus control pins and their functions?

a. USB - universal serial busb. AGP - advanced graphics portc. ISA - industry standard architectured. PCI - peripheral component-interconnector

e. EISA - extended ISA


10/12

9. Extra credit: Build a decoder with 3 input lines but with only 6 output lines. If the valueof the input corresponds to 6 or 7, then all output lines should be asserted to signal anerror.

> Test 3

1. A digital circuit is one which only two logical values are present. True

2. A transistor has 4 connections to the inside world collector the base and emitteroutput. False

3. NOT gates are often called inverters. True

4. NAND and NOR gates require 2 transistors each, whereas the AND and OR gates

require 3 each. True

5. Boolean algebra is a new type of algebra where variables and functions can take ononly the values 0 and 1. True

6. The small circles used or part of the symbols for the inverter NAND gate and NORgate are called inversion bubbles. True


11/12

7. Use symbols that depict 3 circuit gates or their equivalent that form the 3 simplestgates.a. NOTb. NANDc. NOR

8. Assuming A and B as inputs and X as an output, use a truth table to specify theoutput for different combination of the inputs. Adopt the convention that a high is alogical 1, and that low is a logical 0, and express the out values..

a. NOTb. NANDc. NORd. AND

9. Outline the derived general method on how to implement a circuit for a Booleanfunction?


10. Fill in:a. Gates are not manufactured or sold individually but rather in units called

integrated circuits.b. Multiplexeris a circuit with 2^n data inputs, 1 data output, and n control input

that select one of the data inputs.c. Decoderis a circuit that takes an orbit number or inputs and uses it to select

exactly one of the 2n output lines


12/12

d. Comparatorcompares 2 inputs and produces a 1 if they are equal and a 0otherwise.

e. Adderis a hardware circuit that performs addition, which is an essential part ofevery CPU.

11. Use a truth table to make a circuit for a half adder to outline a 1-bit integer additionwith sum of inputs A and B, and the carry to the next position.

12. Use a truth table to show that A = (A AND B) OR (A AND NOT B)

13. What type of gates are used to implement adder with a carry. or and xor gate

Documents

CSC 204 - Final Study Guide