CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 7 Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660

EEGN-CSCI 660

Introduction to VLSI DesignLecture 7

Khurram Kazi



CSCI 660 2

Behavioral Modeling with VerilogVerilog allows design functionality in an

algorithmic manner: i.e. describe the behavior of the model.

Design at this level resembles C programming more than it resembles digital circuit design.

Verilog is rich in behavioral construct



CSCI 660 3

Topics under Behavioral Modeling

Structured procedures always and initial Define blocking and nonblocking procedural

assignments Delay based timing control mechanism in

behavioral modeling Event based timing control mechanism in

behavioral modeling Use the level-sensitive timing control mechanism

in behavioral modeling Conditional statements using if and else Multiway branching, using case, casex and casx

statements



CSCI 660 4

Topics under Behavioral Modeling

Looping statements such as while, for, repeat and forever

Define sequential and parallel blocksSome examples



CSCI 660 5

Structured procedures always and initial: Review

All statements inside an initial statement constitute an initial block

Initial block starts at time 0Executes only once during a simulation If there are multiple initial blocks, each

block starts to execute concurrently at time 0

Each block finishes execution independently of the other blocks

Multiple behavioral statements must be grouped, typically using begin and end.



CSCI 660 6

Structured procedures always and initial: Review

All statements inside an always statement constitute an always block

always block starts at time 0Executes the statements continuously

in a looping fashionThis statement is typically used to

model a block of activity that is repeated continuously in a digital circuit



CSCI 660 7

Procedural assignments

Procedural assignments update values of reg, integer, real or time variables

The values placed on a variable will remain unchanged until another procedural assignment updates the variable with another value



CSCI 660 8

Blocking assignments

Blocking assignments are executed in the order they are specified in a sequential block

A blocking assignment will not block execution of statements that follow in a parallel block

The = operator is used to specify blocking assignments



CSCI 660 9

Blocking assignmentsreg x, y, z;reg [15:0] reg_a, reg_b;integer count;//All behavioral statements must be inside an initial or always

block

initial

beginx = 0; y = 1; z = 1; //scalar assignmentscount = 0; //Assignment to integer variablesreg_a = 16’b0; reg_b = reg_a; //initialize vectors#15 reg_a[2] = 1’b1; //bit select assignment with delay#10 reg_b[15:13] = {x, y, z} //assign result of concatenation

to part of a vector // {variable within these braces

are concatenated}

count = count + 1; // assignment to an integer (increment)end

Executed at time 0

Executed at time = 15

Executed at time = 25



CSCI 660 10

Nonblocking assignments

Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block.

A <= operator is used to specify nonblocking assignments



CSCI 660 11

Nonblocking assignments affects on the code

module blocking; reg clk, reset, enable; reg x, y, z; reg [15:0] reg_a, reg_b; integer counter; initial begin reset = 1'b0; enable = 1'b0; #25 reset = 1'b1; #40 enable = 1'b1; end

initial begin

clk = 0;forever #10 clk = !clk;

end

// describing the differences between blocking and non-blocking operator

// "=" blocking and "<=" non-blocking operator initial begin

x = 0;y = 1;z = 1;counter = 0;reg_a <= 16'b0;reg_a <= reg_b;

reg_a[2] <= #15 1'b1; //this value changes @ time 15

reg_b[15:13] <= #10 {x, y, z}; //this value changes @ time 10

// i.e. changes before reg_acounter <= counter + 1; //this value changes @ time 0

end endmodule concatenation operator: values

within the curly braces are concatenated

Simulator schedules a nonblocking assignment statement to execute and continues to the next statement in the block without waiting for the nonblocking statement to complete execution



CSCI 660 12

Blocking vs non BlockingThe difference between the two is that

one is similar to variable in VHDL and the other acts like a signal

Blocking in synonymous to = assignment (more like a

variable)Where as non blocking is represented

by<= assignment (more like a

signal)



CSCI 660 13

Non blocking assignment: Non blocking infers two flip flop after synthesis (when clock is in the sensitivity list)

module SimpleFlipFlop (clk, a, b, c);//Input ports input clk; input a;//Output ports output b, c; reg b, c;//Input ports data type//By rule all the input ports should be

wires wire clk, a;always @(posedge clk)begin

b <= a;c <= b;

end endmodule



CSCI 660 14

blocking assignment: blocking statement infers one flip flop in synthesis all the time (code dependent)

module SimpleFlipFlop_blocking (clk, a, b, c);

//Input ports input clk; input a;//Output ports output b, c; reg b, c;//Input ports data type//By rule all the input ports should be

wires wire clk, a;always @(posedge clk)begin

b = a;c = b;

end endmodule

Not a good way of inferring a flip flop



CSCI 660 15

Why at times blocking assignment is preferredAt times some designers prefer blocking as they can see sharing of resources morereadily:

reg [15:0] a, b, c, d, e, f, g, h; reg [16:0] x, y, z; always @ (posedge clk) begin x = a + b + c + d + e + f; y = x + g; z = x + h; end

reg [15:0] a, b, c, d, e, f, g, h; // In this example resource sharing is synthesizer reg [16:0] y, z; // dependant always @ (posedge clk) begin y <= (a + b + c + d + e + f) + g; z <= (a + b + c + d + e + f) + h; end



CSCI 660 16

Why at times blocking assignment is not desiredBlocking statement can cause race condition: file first.v module first (a, b, clk) input b, clk; output a; always @ (posedge clk) begin a = b; endfile second.v module first ( b, c, clk) input c, clk; output b; always @ (posedge clk) begin b = c; end

Some simulators may evaluate module second.v and then module first. This effectively transfers contents of c to a in ONE clock cycle. This is known as simulator race condition.

While some other simulators will execute module first followed by second.

Hence two different simulation results

AVOID USING BLOCKING STATEMENT



CSCI 660 17

Inferring Latches

module latches (y1, y2, y3, enable, a1, preset1, a2, preset2, a3, preset3);

output y1, y2, y3; input a1, preset1; input a2, preset2; input a3, preset3; input enable; reg y1, y2, y3;

always @ (a1 or a2 or a3 or preset1 or preset2 or preset3 or enable)

begin if (preset1) y1 <= 1’b1; else if (enable) y1 <= a1; if (preset2) y2 <= 1’b0; else if (enable) y2 <= a2; if (preset3) y3 <= 1’b1; else if (enable) y3 <= a3; endendmodule



CSCI 660 18

Golden Rule

Golden Rule 1: To synthesize combinational logic using an always block, all inputs to the design must appear in the sensitivity list.

http://www.doulos.com/knowhow/verilog_designers_guide/if_statement/Good website that gives simple Verilog examples

http://www.doulos.com/knowhow/verilog_designers_guide/if_statement/

http://www.doulos.com/knowhow/verilog_designers_guide/if_statement/



CSCI 660 19

Inferring counters

module counters (y1, y2, y3, y4, y5, y6, d, clk, enable, clear, load, up_down);

output [7:0] y1, y2, y3, y4, y5, y6; input [7:0] d; input clk, enable, clear, load, up_load; reg [7:0] y1, y2, y3, y4, y5, y6; integer direction; always @ (posedge clk) begin if (enable) // enable counter y1 <= y1 + 1; endalways @ (posedge clk) begin if (load) // loadable counter y2 <= d; else y2 <= y2 + 1; end

always @ (posedge clk) begin if (clear) // Sync clear counter y3 <= 0; else y3 <= y3 + 1; endalways @ (posedge clk) begin if (up_down) // up down counter direction <= 1; else direction <= -1; y4 = y4 + direction; // NOTICE HERE

// y4 assignment is outside the if else

endendmodule

WOULD THIS CODE GENERATE DANGLING/ UNCONNECTED WIRES OR PORTS???



CSCI 660 20

Frequency Divider

module div11 (clkdiv11, clk, reset_n); output clkdiv11; input clk, reset_n; reg div11; reg [3:0] counter; always @ (posedge clk or negedge

reset_n) begin if (!reset_n) counter <= 0; else if (counter == 10) counter <= 0; else counter <= counter + 1; end

always @ (posedge clk or negedge reset_n)

begin if (!reset_n) div11 <= 0; else if (counter == 10) div11 <= 1; else div11 <= 0; end



CSCI 660 21

Some simple ALU functions

module alu (f, a, b, opcode); parameter addab = 4’b0000, inca = 4’b0001, incb =

4’b0010, andab = 4’b0011, orab = 4’b0100, nega = 4’b0101, shal = 4’b0110,

shar = 4’b0111, passa = 4’b1000, passb = 4’b1001;

output [7:0] f; input [7:0] a, b; input [3:0] opcode; reg [7:0] f;

always @ (a or b or opcode) begin case (opcode) addab: f <= a + b; //add inca: f <= a + 1; //increment a incb: f <= b + 1; //increment b andab: f <= a & b; //a and b orab: f <= a | b; // a or b nega: f <= !a; //negation of a shal: f <= a << 1; //shift “a” left shar: f <= a >> 1; //shift “a”

right passa: f <= a; //pass a as is passb: f <= b; //pass b as is default: f <= 8’bx; defautl

output endcase endendmodule



CSCI 660 22

FSM with four states

module state_machine (lsb, msb, up_down, clk, reset_n);

output lsb, msb; input up_down, clk, reset_n; parameter [1:0] st_zero = 2’b00, st_one = 2’b01, st_two = 2’b10, st_three = 2’b11; reg lsb, msb; reg present_state, next state; always @ (up_down or present_state) // combinatorial part begin case (present_state) //0 = up, 1 = down st_zero: if (up_down == 0) begin next_state <= st_one; lsb <= 1; msb <= 0; end

else begin next_state <= st_three; lsb <= 1; msb <= 1; endst_one: if (up_down == 0) begin next_state <= st_two; lsb <= 0; msb <= 1; end else begin next_state <= st_zero; lsb <= 0; msb <= 0; end



CSCI 660 23

FSM with four states cont’d

st_two: if (up_down == 0) begin next_state <= st_three; lsb <= 1; msb <= 1; end else begin next_state <= st_one; lsb <= 1; msb <= 0; endst_three: if (up_down == 0) begin next_state <= st_zero; lsb <= 0; msb <= 0; end

else

begin

next_state <= st_two;

lsb <= 0;

msb <= 1;

endendcase

end

always @ (posedge clk or negedge reset_n)

//sequential part

begin

if (!reset_n) present_state <= st_zero;

else

present_state <= next_state;

end

endmodule



CSCI 660 24

While Loop example

module While_example;

`define TRU 1'b1;`define FALSE 1'b0;reg [15:0] flag;integer i; //integer to keep the count in

"flag"reg continue;

integer count;initialbegin count = 0; while (count < 128) // Execute loop till

count is 27 //Exit loop at count

of 128 begin

$display ("Count = %d", count); count = count + 1;

endend

initialbegin flag = 16'b 0010_0000_0000_0000; i = 0; continue = `TRU;

while ((i < 16) && continue) //Multiple conditions using operatorsbegin if (flag[i]) begin $display ("Encountered a TRUE bit at element number %d", i);

continue = `FALSE; end i = i + 1;end

endendmodule

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CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 7 Khurram Kazi