1Kazi Spring 2008 CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

1Kazi Spring 2008 CSCI 660

CSCI-660

Introduction to VLSI Design

Khurram Kazi




Selecting a Semiconductor vendor

One of the first things that needs to be done when designing a chip is to select the semiconductor vendor and technology one wants to use. The following issues need to be considered during the selection process Maximum frequency of operation Power restrictions Packageing restrictions Clock tree implementation Floor planning Back-annotationsupport Design support for libraries, megacells, and RAMs Available cores Available test methods and scans




Understanding the library

Design Compiler (DC) uses these libraries Technology libraries Symbol libraries DesignWare libraries




Technology libraries

Contain information about the characteristics and functions of each cell provided in a semiconductor vendor’s library. The manufacturers maintain and distribute the technology libraries

Cell characteristics include information such as cell name, pin names, area, delay arcs and pin loading.

The technology library also defines the conditions that must be met for a functional design (e.g., the maximum transition time for nets). These conditions are called design rule constraints.

Also specify the operating conditions and wire load models specific to that technology

DC requires the technology libraries to be in “.db” format. These libraries are typically provided by the semiconductor manufacturer




Symbol libraries

Symbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics. Semiconductor vendors maintain and distribute the symbol libraries.

Design Compiler uses symbol libraries to generate the design schematic. You must use Design Vision to view the design schematic.

When you generate the design schematic, Design Compiler performs a one-to-one mapping of cells in the netlist to cells in the symbol library.




DesignWare Library

A DesignWare library is a collection of reusable circuit-design building blocks (components) that are tightly integrated into the Synopsys synthesis environment.

DesignWare components that implement many of the built-in HDL operators are provided by Synopsys. These operators include +, -, *, <, >, <=, >=, and the operations defined by if and case statements.

You can develop additional DesignWare libraries at your site by using DesignWare Developer, or you can license DesignWare libraries from Synopsys or from third parties.




Specifying Libraries

Use dc_shell variables to specify the libraries used by the Design Compiler as shown in the table below




Target Library

Design Compiler uses the target library to build a circuit. During mapping, Design Compiler selects functionally correct gates from the target library. It also calculates the timing of the circuit, using the vendor-supplied timing data for these gates.

Use the target_library variable to specify the target library. The syntax is

set target_library my_tech.db




Link Library

Design Compiler uses the link library to resolve references. For a design to be complete, it must connect to all the library components and designs it references. This process is called linking the design or resolving references. During the linking process, Design Compiler uses the link_library system variable, the local_link_library attribute, and the search_path system variable to resolve references The syntax is set link_library {* my_tech.db}




Specifying DesignWare Library

You do not need to specify the standard synthetic library, standard.sldb, that implements the built-in HDL operators. The software automatically uses this library.

If you are using additional DesignWare libraries, you must specify these libraries by using the synthetic_library variable (for optimization purposes) and the link_library variable (for cell resolution purposes).




Describing environmental attributes

set_max_capacitance

Set_max_transition

& set_max_fanout

on Inputs and Output ports or current design

set_operating_conditions

on the whole design

ClockDividerLogic

BlockBIP calc

FramingState

Machine

Top Level

set_wire_loadfor each block,

including top level

set_loadon outputs

set_driving_cellon input signals

clkset_driveon Clock




Environmental attributes

Design environment consists of defining the process parameters, I/O port attributes, and statistical wire load models. Set_min_library <max_library filename>

-min_version <min library filename>

dc_shell> set_min_library “ex25_worst.db” \

-min_version “ex25_best.db”

This command allows the users to simultaneously specify the best case and worst case libraries. Can be used to fix set up and hold violation. The user should set both the min and the max values for the operating conditions




Setting operating conditions

set_operating_conditions Specifies the process, voltage and temperature conditions of

the design.

Synopsys library consists of WORST, TYPICAL and BEST cases. Each vendor has their own naming convention for the libraries!

Changing the value of the operating condition command, full range of process variations are covered.





set_operating_conditions WORST is generally used during pre-layout synthesis phase to

optimize the maximum set-up time.

BEST is normally used to fix any hold violations.

TYPICAL is generally not used since it is covered when both WORST and BEST cases are used.





set_operating_conditions It is possible to optimize the design with both WORST and

BEST cases simultaneously

dc_shell> set_operating_conditions WORST

dc_shell> set_operating_conditions –min BEST

-max WORST




Operating conditions

best

typicalworst

Delay

Process

best

typicalworst

Delay

temperature

besttypical

worst

Delay

Voltage

min typical max

% yield

PVT (Process, Voltage andTemperature curve)




Modeling wire loads

•DC uses wire loads models to estimate capacitance, resistance and the area of the nets prior to floor planning or layout.

•The wire load model is based upon a statistically average length of a net for a given fan out for a given area

“10 x 10”“20 x 20”




Wire load command

DC uses wire load information to model the delay which is a function of loading

Synopsys provides wire load models in the technology library, each representing a particular size.

Designer can create their own wire load models for better accuracy

set_wire_load_model –name <wire-load model>

dc_shell>set_wire_load_model –name MEDIUM




Wire load mode

There are 3 modes associated with the set_wire_load_mode: top, enclosed and segmented

top Defines that all nets in the hierarchy will inherit the same wire load

model as the top level block. Use it if when the plan is to flatten the design later for layout.

enclosed Specifies all the nets (of the sub-blocks) inherit the wire load model

of the block that completely encloses the sub-blocks. For example, if blocks X and Y are enclosed within block Z, then the blocks X and Y will inherit the wire load models defined for block Z.




Wire load mode

segmented Used when wires are crossing hierarchical boundaries. From the previous

example, the sub-blocks X and Y will inherit the wire load models specific to them, while nets between sub-blocks X and Y(which are contained within Z) will inherit wire-load model specified for block Z

Not used often, as the wire load models are specific to the net segments

set_wire_load_mode <top|enclosed|segmented>dc_shell>set_wire_load_mode top Accurately using wire load models is highly recommended as this directly

affects the synthesis runs. Wrong model can generate undesired results. Use slightly pessimistic wire load models. This will provide extra time margin that may be absorbed later in the test circuit insertion or layout




Wire load models across hierarchy

50x50

20x20

40x40

40x40

30x30

50x50

20x20

40x40

50x50

30x30

50x50

20x20

40x40

40x40

30x30

mode = top: (ignores lower level wire loads)

mode = enclosed: (uses best fitting wire loads)

mode = segmented: (uses several wire loads)

30x3020x20




set_drive

set_drive is used at the input ports of the block. It is used to specify the drive strength at the input port. Is typically used to model the external drive resistance to the ports of the block or chip. 0 signifies highest strength and is normally used for clock or reset ports.

set_drive <value><object list> dc_shell> set_drive 0 {clk rst}




set_driving_cell

set_driving_cell is used to model the drive resistance of the driving cell to the input ports.

set_driving_cell –cell <cell name> -pin <pin name> <object list>

dc_shell>set_driving_cell –cell BUFF1 –pin Z [all_inputs]




set_load

set_load sets the capacitive load in the units defined in the technology library (pf), to the specified ports or nets of the design. It typically sets capacitive loading on output ports of the blocks during pre-layout synthesis, and on nets, for back annotating the extracted post layout capacitive information

set load <value> <object list>

dc_shell>set_load 1.5 [all_outputs]

dc_shell> set_load 0.3 [get_nets blockA/n1234]




Design rule constraints

Design rule constraints consist of set_max_transition, set_max_fanout and set_max_capacitance. These rules are technology dependent and are generally set in the technology library. The DRC commands are applied to input ports, output ports or on the current_design. It can be useful if the technology library is not adequate of is too optimistic, then these commands can be used to control the buffering in the design

set_max_transition <value> <object list> set_max_capacitance <value> object list> set_max_fanout ,value> <object list>dc_shell –t>set_max_transition 0.3 current_designdc_shell –t>set_max_capacitance 1.5 [get_ports out1]dc_shell –t>set_max_fanout 3.0 [all_outputs](dc_shell –t> corresponds to DC operating in tcl mode)




Some more design constraints

dc_shell –t >create_clock –period 40 -waveform [list 0 20] CLKset_dont_touch_network is a very useful command and is

usually used for clock and reset. It is used to set_dont_touch property on a port, or a net. This prevents DC from buffering the net in order to meet DRCs.

dc_shell –t>set_dont_touch_network {clk, rst}





If a block generates a secondary clock from the primary, e.g. byte clock from the serial clock, in this apply set_dont_touch_network on the generated clock output port of the block. Helps prevent DC from buffering it up. Clock trees can later be inserted to balance the clock skew.





set_dont_touch is used to set a dont_touch property on the current design, cells, references or net. This is frequently used during hierarchical compilations of the block.

dc_shell –t>set_dont_touch current_design Useful in telling DC not to touch the current design if it has

been optimized to designer’s satisfaction. For example, if some spare gates block is instantiated, DC will not touch it or optimize it.

Documents

1Kazi Spring 2008 CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi