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CSE 670 Winter 2004Mid-Term examination
Implementation of Bubble sort aglorithm
By, Sumitha Nath .K.N
Bubble sort algorithm
for i n to 1{for j 2 to i {if a[j-1] > a[j] then temp = a[j-1]a[j-1] = a[j]a[j] = tempJ++}i - - }
S1
S2
S3j
S3j1
S5
S4
S6
S7
S8
S0
S9
S1Iflag = 1(I < 0)
Iflag = 0(I > 0)Jflag = 1
(j > i)
Jflag = 0 (j < i)
Chkflag = 1 (j-1 > j)
Chkflag = 0 (j-1 < j)
Clearing counters andregisters
Load j and j-1 inregisters
Temp <= j-1
Wj1 <= j
Wj <= temp
J ++
Clear jcounterand I --
Sort done <= 1
State Machine for sorting
S1
S2
S3j
S3j1
S5
S4
S6
S7
S8
S0
S9
S1Iflag = 1(I < 0)
Iflag = 0(I > 0)Jflag = 1
(j > i)
Jflag = 0 (j < i)
Chkflag = 1 (j-1 > j)
Chkflag = 0 (j-1 < j)
Clearing counters andregisters
Load j and j-1 inregisters
Temp <= j-1
Wj1 <= j
Wj <= temp
J ++
Clear jcounterand I --
Sort done <= 1
State Machine for sorting case current_state is
when s0=> next_state <= s1;
when s1 =>if iflag = '1' then
next_state <= sdisp;else
next_state <= s2; end if;when s2 =>if jflag = '1' then
next_state <= s9 ;else
next_state <= s3j; end if;when s3j => next_state <= s3j1;when s3j1 =>if chkflag = '1' then
next_state <= s4 ;else
next_state <= s8; end if; when s4 =>
next_state <= s5;when s5 =>
next_state <= s6;when s6 =>
next_state <= s7;when s7 =>
next_state <= s8;when s8 =>
next_state <= S2;when s9 =>
next_state <= s1;when sdisp =>
next_state <= s0;
end case;
case current_state is
when s0 =>loopclr <= '1';
when s1 =>loopclr <= '0';
when s2 =>null;
when s3j => jload <='1'; when s3j1 =>
addrsel <= '0';j1load <= '1';
when s4 =>tload <= '1';
when s5 => wj1load <= '1';
addrsel <= '0';fload <= '1';
when s6 =>addrsel <= '1';datasel <= '1';
when s7 =>wjload <= '1'; fload <= '1';
when s8=> jinc <= '1';when s9 =>
loopclr <= '1'; iinc <= '1'; when sdisp => sortdone <= '1'; when others => null; end case;
>
J COUNTER
>
<
-1
I DOWNCOUNTER
STORE
Ri
TEMP REG
Rj-1
WRj1WRjwjload
Clr
Clr
tload
Clr
Clr
jout
wj1load
Clr
Clr
Jload
Clr
Clr
j1load
Clr
Clr
j1outa b
dataj1
dataj
b adatasel
donttemp
addr
dinClk
fload
addrsel
jflag
jcountertempjflag
b
a
Iinc
Clr
Clkjinc
Clr
Clk
b a
chkflag
tempj1
J COUNTER
jinc
Clr
Clk
din
-1
J COUNTER
dflag
stop
dout
Clk
fload
din
displayDATA PATH
C1: process(current_state,dflag,sortdone,BTN4) begin case current_state is
when swait => if BTN4 = '1' then next_state <= swait; else next_state <= s0; end if;
when s0=> if BTN4 = '1' then
next_state <= s1; else next_state <= s0;
end if;
when s1 =>if dflag = '1' then
next_state <= swait; else next_state <= s2; end if;
when s2 => next_state <= s1 ;
end case;end process C1;
Swait
S0
S1
S2
BTN4
!BTN4
!BTN4
BTN4
Dflag = 0
Dflag = 1
d ++
State machine for display
After sort done <= 1
C2: process(current_state) begin dinc <= '0'; floaddisp <= '0'; case current_state is when swait =>
null; when s0 =>
null;
when s1 =>
null;
when s2 => dinc <= '1';
when others => null;
end case;
end process C2;
>
J COUNTER
>
<
-1
I DOWNCOUNTER
STORE
Ri
TEMP REG
Rj-1
WRj1WRjwjload
Clr
Clr
tload
Clr
Clr
jout
wj1load
Clr
Clr
Jload
Clr
Clr
j1load
Clr
Clr
j1outa b
dataj1
dataj
b adatasel
donttemp
addr
dinClk
fload
addrsel
jflag
jcountertempjflag
b
a
Iinc
Clr
Clkjinc
Clr
Clk
b a
chkflag
tempj1
J COUNTER
jinc
Clr
Clk
din
-1
J COUNTER
dflag
stop
dout
Clk
fload
din
displayDATA PATH
