cse477 lecture10

8/8/2019 cse477 lecture10

1/23

CSE477 L10 Inverter, Dynamic.1 Irwin&Vijay, PSU, 2002

CSE477VLSI Digital Circuits

Fall 2002

Lecture 10: The Inverter, A Dynamic View

Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~cg477

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]


2/23


Inverter Propagation Delay

Propagation delay is proportional to the time-constant of

the network formed by the pull-down resistor and the loadcapacitance

tpHL = ln(2) Reqn CL = 0.69 Reqn CL

tpLH = ln(2) Reqp CL = 0.69 Reqp CL

tp = (tpHL + tpLH)/2 = 0.69 CL(Reqn + Reqp)/2

To equalize rise and fall times make the on-resistance ofthe NMOS and PMOS approximately equal.

VDD

Rn

Vout = 0

Vin = V DD

CL

tpHL = f(Rn, CL)


3/23


Inverter Transient Response

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

t (sec)x 10-10

VDD=2.5V

0.25QmW/Ln = 1.5

W/Lp = 4.5

Reqn= 13 k; (z 1.5)

Reqp= 31 k; (z 4.5)


4/23


Inverter Transient Response

-0.5

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

Vin

t (sec)x 10-10

VDD=2.5V

0.25QmW/Ln = 1.5

W/Lp = 4.5

Reqn= 13 k; (z 1.5)

Reqp= 31 k; (z 4.5)

tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

tf trtpHL tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec


5/23

CSE477 L10 Inverter, Dynamic. Irwin&Vijay, PSU, 2002

Inverter Propagation Delay, Revisited

To see how a designercan optimize the delay of a gate

have to expand the Req in the delay equation

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V)

tpHL = 0.69 Reqn CL

= 0.69 (3/4 (CL VDD)/IDSATn )

} 0.52 CL / (W/Ln kn VDSATn )


6/23


Design for Performance

Reduce CL internal diffusion capacitance of the gate itself

- keep the drain diffusion as small as possible

interconnect capacitance

fanout

Increase W/L ratio of the transistor the most powerful and effective performance optimization

tool in the hands of the designer

watch out forself-loading! when the intrinsic capacitancedominates the extrinsic load

Increase VDD can trade-off energy for performance

increasing VDD above a certain level yields only very minimalimprovements

reliability concerns enforce a firm upper bound on VDD


7/23


8/23


PMOS/NMOS Ratio Effects

.

4

4.

1 2 4

F = (W/Lp)/(W/Ln)

x 10-11

F of 2.4 (= 31 k;/13 k;)gives symmetrical

response

F of 1.6 to 1.9 givesoptimal performance

tpLH

tp

tpHL


9/23


Device Sizing for Performance

Divide capacitive load,CL, into

Cint : intrinsic - diffusion and Miller effect Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint)

where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of thegate

Widening both PMOS and NMOS by a factorS reducesReq by an identical factor (Req = Rref/S), but raises theintrinsic capacitance by the same factor (Cint = SCiref)

tp

= 0.69 Rref

Ciref

(1 + Cext

/(SCiref

)) = tp0

(1 + Cext

/(SCiref

))

tp0 is independent of the sizing of the gate; with no load the driveof the gate is totally offset by the increased capacitance

any S sufficiently larger than (Cext/Cint) yields the bestperformance gains with least area impact


10/23


Sizing Impacts on Delay

2

2.2

2.4

2.

2.

.2

.4

.

.

1 7 11 1 1

S

x 10-11 The majority of theimprovement is already

obtained for S = 5. Sizing

factors larger than 10

barely yield any extra gain

(and cost significantlymore area).

for a fixed load

self-loading effect

(intrinsic capacitance

dominates)


11/23


Impact of Fanout on Delay

Extrinsic capacitance, Cext, is a function of the fanout of

the gate - the larger the fanout, the larger the externalload.

First determine the input loading effect of the inverter.

Both Cg and Cint are proportional to the gate sizing, soCint = KCg is independent of gate sizing and

tp = tp0 (1 + Cext/ KCg) = tp0 (1 + f/K)

i.e., the delay of an inverter is a function of the ratio

between its external load capacitance and its input gatecapacitance: the effective fan-out f

f = Cext/Cg


12/23


Inverter Chain

If CL is given

How should the inverters be sized?

How many stages are needed to minimize the delay?

In Out

CL

Real goal is to minimize the delay through an inverter

chain

the delay of the j-th inverter stage is

tp,j = tp0 (1 + Cg,j+1/(KCg,j)) = tp0(1 + fj/ K)

and tp = tp1 + tp2 + . . . + tpN

so tp = tp,j = tp0 (1 + Cg,j+1/(KCg,j))

Cg,11 2 N


13/23


Sizing the Inverters in the Chain

The optimum size of each inverter is the geometric mean

of its neighbors meaning that if each inverter is sized upby the same factor f wrt the preceding gate, it will have thesame effective fan-out and the same delay

f = CL/Cg,1 = F

where F represents the overall effective fan-out of thecircuit (F = CL/Cg,1)

and the minimum delay through the inverter chain is

tp = N tp0 (1 + ( F ) / K)

The relationship between tp and F is linear for one inverter,square root for two, etc.

N N

N


14/23


Example of Inverter Chain Sizing

CL/Cg,1 has to be evenly distributed over N = 3 inverters

CL/Cg,1 = 8/1f =

In Out

CL = 8 Cg,1Cg,11


15/23


Example of Inverter Chain Sizing

CL/Cg,1 has to be evenly distributed over N = 3 inverters

CL/Cg,1 = 8/1f =

In Out

CL = 8 Cg,1Cg,11 f = 2 f 2 = 4

38 = 2


16/23


Determining N: Optimal Number of Inverters

What is the optimal value for N given F (=fN) ?

if the number of stages is too large, the intrinsic delay of thestages becomes dominate

if the number of stages is too small, the effective fan-out of eachstage becomes dominate

N N

The optimum N is found by differentiating the minimumdelay expression divided by the number of stages andsetting the result to 0, giving

K + F - ( F lnF)/N = 0

ForK = 0 (ignoring self-loading) N = ln (F) and theeffective-fan out becomes f = e = 2.71828

ForK = 1 (the typical case) the optimum effective fan-out(tapering factor) turns out to be close to 3.6


17/23


Optimum Effective Fan Out

Choosing f larger than optimum has little effect on delayand reduces the number of stages (and area).

Common practice to use f = 4 (forK = 1)

But too many stages has a substantial negative impact on delay

2.5

3

3.5

4

4.5

5

0 0.5 1 1.5 2 2.5 3

K

0

1

2

3

4

5

6

7

1 1.5 2 2.5 3 3.5 4 4.5 5

f


18/23


Example of Inverter (Buffer) Staging

CL = 64 Cg,1Cg,1 = 1

1

CL = 64 Cg,1Cg,1 = 1

1 8

CL = 64 Cg,1Cg,1 = 1

1 4 16

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3


19/23


20/23


Input Signal Rise/Fall Time

In reality, the input signal

changes gradually (and bothPMOS and NMOS conduct fora brief time). This affects thecurrent available forcharging/discharging CL and

impacts propagation delay.

.

.

.

.

.

.

.

.

ts(sec)

x 1 -11

x 1 -11

for a minimum-size inverter

with a fan-out of a single gate

tp increases linearly withincreasing input slope, ts,once ts > tp

ts is due to the limited drivingcapability of the preceding gate


21/23


Design Challenge

A gate is never designed in isolation: its performance isaffected by both the fan-out and the driving strength of thegate(s) feeding its inputs.

tip = tistep + L t

i-1step (L } 0.25)

Keep signal rise times smaller than or equal to the gatepropagation delays.

good for performance

good for power consumption

Keeping rise and fall times of the signals small and ofapproximately equal values is one of the major challengesin high-performance designs - slope engineering.


22/23


Delay with Long Interconnects

When gates are farther apart, wire capacitance and

resistance can no longer be ignored.

tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan

where Rdr= (Reqn + Reqp)/2

= 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2

cint

Vin

cfan

(rw, cw, L) Vout

Wire delay rapidly becomes the dominate factor (due tothe quadratic term) in the delay budget for longer wires.


23/23


Next Lecture and Reminders

Next lecture

Designing fast logic- Reading assignment Rabaey, et al, 6.2.1

Reminders

Project specifications due today

HW3 due next Thursday, Oct 10th

(hand in to TA) Class cancelled on Oct 10th as make up for evening midterm

I will be out of town Oct 10th through Oct 15th and Oct 18th

through Oct 23rd, so office hours during those periods arecancelled

We will have a guest lecturer on Oct 22

nd

Evening midterm exam scheduled

- Wednesday, October 16th from 8:15 to 10:15pm in 260 Willard

- Only one midterm conflict filed for so far

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cse477 lecture10