DA - Giam Sat Va Dieu Khien Thiet Bi Qua Duong PSTN - Le Thanh Phu

MC LC

Li ni u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Li cm n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Nhn xt gio vin hng dn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Nhn xt gio vin phn bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Gii thiu ti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chng 1-Gii thiu tng quan mng in thoi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1. Gii thiu tng qut v tng i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2. Gii thiu tng qut v my in thoi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chng 2 - Gii thiu linh kin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1. Vi iu khin AVR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 IC MT8888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.3 IC LM358 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.4 IC MAX232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Chng 3-S thit k v gii thut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.1. S thit k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.1.1 S khi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.1.2 S nguyn l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.2. Gii thut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.2.1 Module PSTN-RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.2.2 Module trm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Chng 4-Kt lun v hng pht trin ti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.1 Kt lun. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2 Hng pht trin ti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Ti liu tham kho. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

1

LI NI U

Trong lnh vc k thut ngy nay th lnh vc in t ng vai tr v cng

quan trng trong thi i cng nghip ho hin i ho t nc. Ni n lnh vc

in t th chng ta khng th khng nhc n ngnh k thut in t vin thng.

l chic cha kho vng m ra mt k nguyn mi, nh n ta c th thu thp

nhiu thng tin t mi ni trn hnh tinh phc v cuc sng.

Tuy ch mi thm nhp vo nc ta gn y nhng cng ngh in t

pht trin rt nhanh v ngy cng gi vai tr quan trng trong nn cng nghip

ho nc nh. H thng vin thng, dch v khch hng, thng tin di ng, nhn

tin cng pht trin vi tnh hin i v t ng ha ngy cng cao.

Vi s pht trin nhanh chng ca ngnh cng ngh in t, th vic iu

khin cc thit b in t ng ngy cng nhiu, chng ta cn s dng cc chip

iu khin lp trnh chng hot ng theo mun. Hin nay, do nhu cu trao

i thng tin ca ngi dn l v cng ln nn mng in thoi ngy cng c

m rng khng ch dng li vic lin lc thng tin m cn thm nhiu tnh nng

v dch v khc. Mt trong nhng tnh nng l s dng mng in thoi

truyn tn hiu iu khin, n gip tit kim c rt nhiu thi gian cho cng

vic. Chnh v vy m ti quyt nh chn ti Gim st v iu khin thit

b qua ng PSTN.Song, do gii hn v thi gian cng nh kin thc nn ni dung cn nhiu

thiu st. Rt mong s ng gp kin ca qu thy c v cc bn sinh vin

tp n c hon thin hn. Xin chn thnh cm n !

2

LI CM N

Trong thi gian hon thnh xong ti, ti c s gip ca qu bc

thy c v bn b nn ti c hon thnh ng thi gian. Ti xin chn

thnh cm n n: Thy Trn Minh Hng, ht lng quan tm, gip tn tnh v to mi iu kin ti c th hon thnh n ny. Xin chn thnh gi

li cm n n qu thy c trong Khoa in T cung cp cho ti nhng kin

thc nn, chuyn mn lm c s ti c th hon thnh n ny. Ti cng xin

chn thnh cm n n cc bn sinh vin v cc bc anh ch gip v nhiu

mt: kin, ti liu., ti c th hon thnh n ng thi gian .

3

NHN XT CA GIO VIN HNG DN

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TP.HCM ngy....... thng... nm 2010

Gio vin hng dn

4

NHN XT CA GIO VIN PHN BIN

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TP.HCM ngy....... thng... nm 2010

Gio vin phn bin

6

GII THIU TI

1. L DO CHN TI.Trong thi i pht trin ca th k 21, h thng thng tin lin lc v v tr

l mt trong nhng vn quan trng. l nhng ng dng ca thng tin lin

lc vo lnh vc kinh t, khoa hc v i sng. c bit trong nhng thp nin gn

y, ngnh Bu chnh vin thng pht trin mnh m to ra bc ngoc quan

trng trong lnh vc thng tin p ng nhng nhu cu khc ca con ngi nh:

t ng tr li in thoi khi ch vng nh, hp th thoi,

iu khin thit b thng qua h thng thng tin lin lc l s kt hp gia

cc ngnh in in t v Vin thng, s phi hp ng dng vi iu khin

hin i v h thng thng tin lin lc hnh thnh mt hng nghin cu v

pht trin khng nh trong khoa hc k thut. iu khin thit b thng qua mng

in thoi khc phc c nhiu gii hn trong h thng iu khin t xa v bo

ng thng thng. H thng ny khng ph thuc vo khong cch, mi trng

,i tng iu khin v i tng bo ng. im ni bc ca h thng l tnh

lu ng ca tc nhn iu khin (ngi iu khin), v i tng c iu

khin l c nh.

Trn th gii, cc nc pht trin khng t nhng cng trnh nghin cu

khoa hc thnh cng khi dng mng iu khin thng qua ng truyn ca h

thng thng tin: Ti Nga c nhng nh my in, nhng kho lu tr ti liu qu

ng dng h thng iu khin t xa v t ng bo ng thng qua ng in

thoi ng ngt nhng ni cao p, t ng quay s bo ng khi c s c, t

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ng x bnh cha chy v cng ti Nga c h thng iu khin v bo ng

thng qua mng Internet iu khin nh my in nguyn t. Ngoi ra, ng

dng ca h thng iu khin t xa bng in thoi, gip ta iu khin cc thit b

in nhng mi trng nguy him m con ngi khng th lm vic c hoc

nhng dy chuyn sn xut thay th con ngi.

2. TM TT NI DUNG TI. ti bao gm:

Module giao tip my tnh (PSTN-RS232): c chc nng chuyn i tn

hiu t chun PSTN sang RS232 v ngc li giao tip vi phn mm gim st

trn my tnh.

Module trm: c cc cm bin ng vo v o nhit , c cc ng ra

iu khin cc thit b.

Phn mm gim st:

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Set port connect: chn cng Com kt ni, tc baudrate.

Device connect: nhp vo s phone ca module trm nhp vo nt

connect kt ni. Khi kt ni thnh cng chng ta s thy ch disconnect.

Temperature: bo nhit m module trm o c.

Control: 3 nt control iu khin 3 ng ra.

Status: theo di trng thi 3 ng vo (mu xanh bnh thng, cnh

bo ).

Configuration: cu hnh cho module trm, phone l s in thoi m

module trm s kt ni gi trng thi (module PSTN-RS232) , time thi

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gian module trm s gi trng thi.

Nu ta khng kt ni vi module trm th sau khong thi gian time

th module trm s gi trng thi ln, hoc khi c cnh bo (ng vo tc

ng hoc nhit thay i qu phm vi 2oC).

CHNG 1:GII THIU TNG QUAN V MNG IN

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THOI1.1 GII THIU TNG QUT V TNG I :1.1.1 nh ngha v tng i :

Tng i l mt h thng chuyn mch c h thng kt ni cc cuc lin

lc gia cc thu bao vi nhau, vi s lng thu bao ln hay nh tu thuc vo

tng loi tng i, tng khu vc.

1.1.2 Chc nng ca tng i :

Tng i in thoi c kh nng :

Nhn bit c khi thu bao no c nhu cu xut pht cuc gi.

Thng bo cho thu bao bit mnh sn sng tip nhn cc yu cu ca thu

bao.

X l thng tin t thu bao ch gi iu khin kt ni theo yu cu.

Bo cho thu bao b gi bit c ngi cn mun lin lc.

Gim st thi gian v tnh trng thu bao ghi cc v gii ta.

Giao tip c vi nhng tng i khc phi hp iu khin.

1.1.3 Phn loi tng i :

Tng i cng nhn :

Vic kt ni thng thoi, chuyn mch da vo con ngi.

Tng i c in :

B phn thao tc chuyn mch l h thng c kh, c iu khin bng h

thng mch t. Gm hai h thng chuyn mch c kh c bn : chuyn mch tng

nc v chuyn mch ngang dc.

Tng i in t :

Qu trnh iu khin kt ni hon ton t ng, v vy ngi s dng cng

khng th cung cp cho tng i nhng yu cu ca mnh bng li ni c.

Ngc li, tng i tr li cho ngi s dng cng khng th bng li ni. Do ,

cn qui nh mt s thit b cng nh cc tn hiu ngi s dng v tng i c

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th lm vic c vi nhau.

1.1.4 Cc loi m hiu :

Tn hiu mi quay s (Dial tone) : Khi thu bao nhc t hp xut pht cuc

gi s nghe m hiu mi quay s do tng i cp cho thu bao gi, l tn hiu hnh

sin c tn s 425 25 Hz lin tc.

Tn hiu bo bn (Busy tone) : Tn hiu ny bo cho ngi s dng bit thu bao

b gi ang trong tnh trng bn hoc trong trng hp thu bao nhc my qu lu

m khng quay s th tng i gi m hiu bo bn ny. Tn hiu bo bn l tn

hiu hnh sin c tn s 425 25 Hz, ngt qung 0.5 giy c v 0.5 giy khng.

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Tn hiu Busy toneTn hiu chung (Ring back tone) : Tn hiu chung do tng i cung cp cho

thu bao b gi, l tn hiu hnh sin c tn s 25 Hz v in p 90V hiu dng. ngt

qung tu thuc vo tng i, thng 2 giy c v 4 giy khng.

Tn hiu hi chung (Ring tone) : Tn hiu hi chung do tng i cp cho thu

bao gi, l tn hiu hnh sin c tn s 425 25 Hz l hai tn hiu ngt qung 2s c

4s khng tng ng vi nhp chung.

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Tn hiu chung1.1.5 Phng thc chuyn mch ca tng i in t :

Tng i in t c nhng phng thc chuyn mch sau :

Tng i in t dng phng thc chuyn mch khng gian (SDM :

Space Devision Multiplexer).

Tng i in t dng phng thc chuyn mch thi gian (TDM Timing

Devision Multiplexer) : c hai loi. Phng thc ghp knh tng t theo thi

gian (Analog TDM) gm c :

+ Ghp knh bng phng thc truyn t cng hng.

+ Ghp knh PAM (PAM : Pulse Amplitude Modulation).

Trong k thut ghp knh PCM ngi ta li chia 2 loi : iu ch Delta v

iu ch PCM.

Ngoi ra, i vi tng i c dung lng ln v rt ln (dung lng ln n

c vi chc ngn s) ngi ta phi hp c hai phng thc chuyn mch SDM v

TDM thnh T S T, T S, S T S .

u im ca phng thc kt hp ny l tn dng ti a s link trng v

gim bt s link trng khng cn thit, lm cho kt cu ca ton tng i tr nn

n gin hn. bi v, phng thc ghp knh TDM lun lun to ra kh nng ton

thng, m thng thng i vi tng i c dung lng ln, vic d link l khng

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cn thit. Ngi ta tnh ra thng thng ch c ti a 10% cc thu bao c yu

cu cng 1 lc, nn s link trng ch cn t 10% tng s thu bao l .

Tng i in t dng phng thc ghp knh theo tn s (FDM :

Frequence Devision Multiplexer).

1.2 GII THIU TNG QUT V MY IN THOI :1.2.1 Cc thng s c bn ca my in thoi :

Tng i c ni vi cc thu bao qua 2 c truyn TIP v RING.

Thng qua 2 ng dy ny thng tin t tng i qua cc thu bao c cp bng

ngun dng t 25 mA n 40 mA (trung bnh chn 35 mA) n cho my in

thoi.

Tng tr DC khi gc my ln hn t 20 K

Tng tr AC khi gc my t 4K n 10K

Tng tr DC khi nhc my nh hn 1K (t 0,2K 0,6K).

Cc thng s v gii hn my in thoi:

Thng s Cc gi tr mu Gi tr s dng

Dng lm vic 20 80 mA 20 120 mA

Ngun tng i -48 -> -60 V -47 -> -150 V

in tr vng 0 1300 0 1600

Suy hao 8 dB 17 Db

Mo dng Tng cng 50 Db

Dng chung 90 Vmrs/20 Hz 75 90 Vmrs/16-25Hz

Tai nghe 70 90 Db < 15dB

1.2.2 Cc hot ng trn mng ca my in thoi:

Tng i nhn bit trng thi nhc my ca thu bao hay gc my bng

cch s dng ngun mt chiu 48VDC.

Khi gc my tng tr DC bng 20K rt ln xem nh h mch.

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Khi nhc my tng tr DC gim xung nh hn 1K v hai tng i nhn

bit trng thi ny thng qua dng DC xut hin trn ng dy. Sau , tng i

cp tn hiu mi gi ln ng dy n thu bao.

Quay s :

Ngi gi thng bo s mnh mun gi cho tng i bit bng cch gi s

my in thoi ca mnh mun gi n cho tng i. C hai cch gi s n tng

i :

Phng thc quay s tone DTMF v PULSE: Khi c mt phm c n th

trn ng dy s xut hin 2 tn s khc nhau thuc nhm fthp v fcao. Phng

php tn ghp ny chng nhiu tt hn, ngoi ra dng dng tone DTMF s tng

c tc quay nhanh gp 10 ln so vi vic thc hin quay s PULSE. Mt

khc phng php s s dng c mt s dch v cng thm tng i.

Phng php quay s pulse: tn hiu quay s l chui xung vung, tn s

chui d n = 10Hz,s in thoi bng s xung ra, ring s 0 s l 10 xung, bin

mc cao l 48v, mc thp l 10v.

Quay s bng Tone (Tone Dialing) : My in thoi pht ra cng lc hai

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tn hiu vi tn s dao ng khc nhau tng ng vi s mun quay (DTMF :

Dual Tone Multi Frequence) theo bng sau :

BNG PHN LOI TN S TN HIU TONEPhm Tn s thp (Hz) Tn s cao (Hz)

1 697 1209

2 697 1336

3 697 1447

4 770 1209

5 770 1336

6 770 1447

7 852 1209

8 852 1336

9 852 1447

* 941 1209

0 941 1336

# 941 1447

Kt ni thu bao :

Tng i nhn c cc s liu s xem xt :

Nu cc ng dy ni thng thoi u b bn th tng i s cp tn hiu

bo bn.

Nu ng dy ni thng thoi khng bn th tng i s cp cho ngi b

gi tn hiu chung v ngi gi tn hiu hi chung. Khi ngi c gi nhc

my, tng i nhn bit trng thi ny, th tng i ngng cp tn hiu chung

khng lm h mch thoi v thc hin vic thng thoi. tn hiu trn ng dy

n my in thoi tng ng vi tn hiu thoi cng vi gi tr khong 300 mV

nh nh. Tn hiu ra khi my in thoi chu s suy hao trn ng dy vi

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mt mt cng sut trong khong 10 dB 25 dB. Gi s suy hao l 20 dB, suy ra

tn hiu ra khi my in thoi c gi tr khong 3V nh nh.

Ngng thoi :

Khi mt trong 2 thu bao gc my, th tng i nhn bit trng thi ny, ct

thng thoi cho c 2 my ng thi cp tn hiu bo bn cho my cn li

Tn hiu thoi:

Tn hiu thoi trn ng dy l tn hiu in mang cc thng tin c ngun

gc t m thanh trong qu trnh trao i gia 2 thu bao. Trong , m thanh c

to ra bi cc dao ng c hc, n truyn trong mi trng dn m.

Khi truyn i trong mng in thoi l tn hiu thng b mo dng do

nhng l do : nhiu, suy hao tn hiu trn ng dy do bc x sng trn ng

dy vi cc tn s khc nhau. m bo tn hiu in thoi nghe r v trung

thc, ngy nay trn mng in thoi ngi ta s dng tn hiu thoi c tn s t

300 Hz 3400 Hz.

1.3 PHNG THC HOT NG GIA TNG I V MY IN

THOI:Tng i nhn dng thu bao gi nhc my thng qua s thay i tng tr

mch vng ca ng dy thu bao. Bnh thng khi thu bao v tr gc my

in tr mch vng l rt ln. Khi thu bao nhc my, in tr mch vng thu

bao gim xung cn khong t 150 n 1500. Tng i c th nhn bit s

thay i tng tr mch vng ny (tc l thay i trng thi ca thu bao) thng

qua cc b cm bin trng thi. Tng i cp m hiu mi quay s (Dial Tone) cho

thu bao. Dial Tone l tn hiu mi quay s hnh sin c tn s 425 25 Hz. Khi

thu bao nhn bit c tn hiu Dial Tone, ngi gi s hiu l c php quay

s. Ngi gi bt u tin hnh gi cc xung quay s thng qua vic quay s hoc

nhn phm chn s. Tng i nhn bit c cc s c quay nh vo cc chui

xung quay s pht ra t thu bao gi. Thc cht cc xung quay s l cc trng thi

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nhc my hoc gc my ca thu bao. Nu cc ng kt ni thng thoi b bn

hoc thu bao c gi b bn th tng i s pht tn hiu bo bn cho thu bao.

Am hiu ny c tn s f = 425 25 Hz ngt nhp 0,5s c 0,5 s khng. Tng i

nhn bit cc s thu bao gi n v nhn xt :

Nu s u nm trong tp thu bao th tng i s phc v nh cuc gi ni

i. Nu s u l s qui c gi ra th tng i phc v nh mt cuc gi lin i

qua trung k v gi ton b phn nh v s quay sang tng i i phng gii

m.

Nu s u l m gi cc chc nng c bit, tng i s thc hin cc chc

nng thu yu cu ca thu bao. Thng thng, i vi loi tng i ni b c

dung lng nh t vi chc n vi trm s, c thm nhiu chc nng c bit lm

cho chng trnh phc v thu bao thm phong ph, tin li, a dng, hiu qu

cho ngi s dng lm tng kh nng khai thc v hiu sut s dng tng i.

Nu thu bao c gi rnh, tng i s cp tn hiu chung cho thu bao

vi in p 90Vrms (AC), f = 25 Hz, chu k 2s c 4s khng. ng thi, cp m

hiu hi chung (Ring Back Tone) cho thu bao gi, m hiu ny l tn hiu sin f

= 425 25 Hz cng chu k nhp vi tn hiu chung gi cho thu bao c gi.

Khi thu bao c gi nhc my, tng i nhn bit trng thi my ny tin

hnh ct dng chung cho thu bao b gi kp thi trnh h hng ng tic cho

thu bao. ng thi, tin hnh ct m hiu Ring Back Tone cho thu bao gi v

tin hnh kt ni thng thoi cho 2 thu bao.

Tng i gii ta mt s thit b khng cn thit tip tc phc v cho cc

cuc m thoi khc.

Khi hai thu bao ang m thoi m 1 thu bao gc my, tng i nhn bit

trng thi gc my ny, ct thng thoi cho c hai bn, cp tn hiu bn (Busy

Tone) cho thu bao cn li, gii ta link phc v cho cc m tho khc. Khi

thu bao cn li gc my, tng i xc nhn trng thi gc my, ct m hiu bo

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bn, kt thc chng trnh phc v thu bao.

Tt c hot ng ni trn ca tng i in t u c thc hin mt cch

hon ton t ng. Nh vo cc mch iu khin bng in t, in thoi vin c

th theo di trc tip ton b hot ng ca tng i mi thi im nh vo cc

b hin th, cnh bo.

in thoi vin c th trc tip iu khin cc hot ng ca tng i qua

cc thao tc trn bn phm, h thng cng tc.cc hot ng c th bao gm :

nghe xen vo cc cuc m thoi, ct cng bc cc cuc m thoi c xu,

t chc in thoi hi ngh. Tng i in t cng c th c lin kt vi my

in ton iu khin hot ng h thng. iu ny lm tng kh nng khai thc,

lm tng dung lng, cng nh kh nng hot ng ca tng i ln rt nhiu.

CHNG 2: GII THIU LINH KIN

20

2.1 VI IU KHIN AVR.

AVR l mt h vi iu khin do hng Atmel sn xut (Atmel cng l nh sn

xut dng vi iu khin 89C51 m c th bn tng nghe n). AVR l chip vi

iu khin 8 bits vi cu trc tp lnh n gin ha-RISC (Reduced Instruction

Set Computer), mt kiu cu trc ang th hin u th trong cc b x l.

Ti sao AVR: so vi cc chip vi iu khin 8 bits khc, AVR c nhiu c

tnh hn hn, hn c trong tnh ng dng (d s dng) v c bit l v chc nng:

Gn nh chng ta khng cn mc thm bt k linh kin ph no khi s dng AVR, thm ch khng cn ngun to xung clock cho chip (thng l cc khi

thch anh).

Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch np ch cn vi in tr l c th lm c. Mt s AVR cn h tr lp trnh on chip bng

bootloader khng cn mch np

Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch C.

Ngun ti nguyn v source code, ti liu, application notert ln trn internet.

Hu ht cc chip AVR c nhng tnh nng (features) sau: C th s dng xung clock ln n 16MHz, hoc s dng xung clock ni

ln n 8 MHz (sai s 3%).

B nh chng trnh Flash c th lp trnh li rt nhiu ln v dung lng ln, c SRAM (Ram tnh) ln, v c bit c b nh lu tr lp trnh c

21

EEPROM.

Nhiu ng vo ra (I/O PORT) 2 hng (bi-directional).

8 bits, 16 bits timer/counter tch hp PWM.

Cc b chuyn i Analog Digital phn gii 10 bits, nhiu knh.

Chc nng Analog comparator.

Giao din ni tip USART (tng thch chun ni tip RS-232).

Giao din ni tip Two Wire Serial (tng thch chun I2C) Master v Slaver.

Giao din ni tip Serial Peripheral Interface (SPI).Mt s chip AVR thng dng:

C bn h AVR c th chia lm 4 nhm sau:

tinyAVR the ATtiny series.

o 18 kB program memory.

o 632-pin package.

o Limited peripheral set.

megaAVR the ATmega series.


o 28100-pin package.

o Extended instruction set (Multiply instructions and instructions for handling

22

larger program memories).

o Extensive peripheral.

XMEGA the ATxmega series.


o 4464100-pin package (A4, A3, A1).

o Extended performance features, such as DMA, "Event System", and

cryptography support.

o Extensive peripheral set with DACs.

Atmel At94k FPSLIC (Field Programmable System Level Integrated Circuit), an

AVR core on-die with an FPGA. The FPSLIC uses SRAM for the AVR program

code, unlike all other AVRs. Partly due to the relative speed difference between

SRAM and flash, the AVR core in the FPSLIC can run at up to 50MHz.

AVR32 AP7000 Sram 32KB 1.8 - 3.3V

ATUC3A0xxxx (gi tr xxxx th hin dung lng flash ca VK).

ATUC3A0512 Flash 512kB sram64B 3.0-3.6V.

Ngoi ra cn c:

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

23

ATUC3A0xxxx

Cc dng AVR32 hin ti cha thy bn trn th trng tuy nhin y l dng vk

32bit kh mch vi nhiu tnh nng mi :

Tch hp USB , cng ngh x l ting ni (AC97) , tch hp b RTC -thi gian

thc , thm giao thc ethernet ...

2.1.1 Gii thiu cu trc phn cng IC ATmega8:8KB Programmable Flash c th ghi v xa 10.000 ln.

512 Bytes EEPROM c th ghi xa 100.000 ln.

1K Byte Internal SRAM.

2 Timer/Counters 8 bit.

1 Timer/Counters 16 bit.

3 knh iu xung PWM.

6 knh c ADC phn gii 8/10 bit.

2 ng vo ngt, 1 ng USART, 1 Watchdog Timer.

Giao tip ISP, I2C.

23 chn I/O.

in p hot ng 2.7-5.5V (ATmega8L) v 4.5-5.5V (ATmega8).

Thch anh dao ng 0-8MHz (ATmega8L) v 0-16MHz (ATmega8).

S chn:

24

S khi:

25

2.1.2 Chc nng cc chn ca ATmega8:Chn VCC: ngun nui chip.

Chn GND: mass.

Chn GND (22): mass b chuyn i ADC.

Chn VREF: in p tham chiu cho b chuyn i ADC.

Chn AVCC: ngun cp cho b chuyn i ADC.

a. Port B:

L port xut nhp 8 bit.

Bit Tn Chc nng

PB0 ICP1

PB1 OC1A Ng ra PWM

PB2 SS/OC1B Ng ra PWM

PB3 MOSI/OC2 S dng giao tip ISP/ng ra PWM

PB4 MISO S dng giao tip ISP

PB5 SCK S dng giao tip ISP

PB6XTAL1/TOSC

1Chn mc thch anh dao ng ngoi

PB7XTAL2/TOSC

2Chn mc thch anh dao ng ngoi

b. Port C:


Bit Tn Chc nng

PC0 ADC0 Ng vo c ADC


28



PC4 ADC4/SDA Ng vo c ADC/ giao tip I2C

PC5 ADC5/SCL Ng vo c ADC/ giao tip I2C

PC6 RST Chn reset

c. Port D:


Bit Tn Chc nng

PD0 RXD Giao tip USART

PD1 TXD Giao tip USART

PD2 INT0 Ng vo ngt

PD3 INT1 Ng vo ngt

PD4 XCK/T0 Ng vo Counters

PD5 T1 Ng vo Counters

PD6 AIN0 Ng vo ngt

PD7 AIN1 Ng vo ngt

2.1.3 T chc b nh:

B nh chng trnh (Program memory): L b nh Flash lp trnh c, trong

cc chip AVR c (nh AT90S1200 hay AT90S2313) b nh chng trnh ch

gm 1 phn l Application Flash Section nhng trong cc chip AVR mi chng ta

c thm phn Boot Flash setion. Application section bao gm 2 phn: phn cha

cc instruction (m lnh cho hot ng ca chip) v phn cha cc vector ngt

(interrupt vectors). Cc vector ngt nm phn u ca application section (t a

ch 0x0000) v di n bao nhiu ty thuc vo loi chip. Phn cha instruction

nm lin sau , chng trnh vit cho chip phi c load vo phn ny.

Vector ngt ca chip ATMEGA8 ch ko di n a ch 0x012, v vy chng

trnh chnh c th c bt u t bt c v tr no sau . Bng vector ngt:

29

V chc nng chnh ca b nh chng trnh l cha instruction, chng ta khng c nhiu c hi tc ng ln b nh ny khi lp trnh cho chip, v th i

30

vi ngi lp trnh AVR, b nh ny khng qu quan trng. Tt c cc thanh

ghi quan trng cn kho st nm trong b nh d liu ca chip.

B nh d liu (data memory): y l phn cha cc thanh ghi quan trng nht

ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh d liu

trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin v c bn

phn b nh ny c chia thnh 5 phn:

Phn 1: l phn u tin trong b nh d liu, nh m t trong hnh 1, phn

ny bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose

Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l

cc thanh ghi 8 bits.

Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch

tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n

255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no

Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia

thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh

ghi R16 n R31. Cc thanh ghi ny c cc c im sau:

c truy cp trc tip trong cc instruction.

Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k xung clock.

Register File c kt ni trc tip vi b x l trung tm CPU ca chip.

Chng l ngun cha cc s hng trong cc php ton v cng l ch cha kt qu tr li ca php ton.

minh ha, hy xt v d thc hin php cng 2 thanh ghi bng instruction ADD

nh sau:

31

ADD R1,R2

Bn thy trong dng lnh trn, 2 thanh ghi R1 v R2 c s dng trc tip

vi tn ca chng, dng lnh trn khi c dch sang opcode download vo

chip s c dng: 0000110000010010 trong 00001=1 tc thanh ghi R1 v 00010

= 2 ch thanh ghi R2. Sau php cng, kt qu s c lu vo thanh ghi R1.

Tt c cc instruction s dng RF lm ton hng u c th truy nhp tt c

cc RF mt cch trc tip trong 1 chu k xung clock, ngoi tr SBCI, SUBI, CPI,

ANDI v LDI, cc instruction ny ch c th truy nhp cc thanh ghi t R16 n

R31.

Thanh ghi R0 l thanh ghi duy nht c s dng trong instruction LPM

(Load Program Memory). Cc thanh ghi R26, R27, R28, R29, R30 v R31 ngoi

chc nng thng thng cn c s dng nh cc con tr (Pointer register) trong

mt s instruction truy xut gin tip. Chng ta s kho st vn con tr sau ny.

Hnh 3 m t cc chc nng ph ca cc thanh ghi.

32

Tm li 32 RF ca AVR c xem l 1 phn ca CPU, v th chng c

CPU s dng trc tip v nhanh chng, gi cc thanh ghi ny, chng ta khng

cn gi a ch m ch cn gi trc tip tn ca chng. RF thng c s dng

nh cc ton hng (operand) ca cc php ton trong lc lp trnh.

Phn 2: l phn nm ngay sau register file, phn ny bao gm 64 thanh ghi

c gi l 64 thanh ghi nhp/xut (64 I/O register) hay cn gi l vng nh I/O

(I/O Memory). Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi.

Tt c cc thanh ghi iu khin, trng thica thit b ngoi vi u nm y.

Xem li v d trong bi 1, trong ti c cp v vic iu khin cc PORT ca

AVR, mi PORT lin quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3

thanh ghi ny u nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit

b ngoi vi khc nh Timer, chuyn i Analog/Digital, giao tip USARTu

thc hin thng qua vic iu khin cc thanh ghi trong vng nh ny.

Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu

s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca

chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi

I/O th a ch ca chng c tnh t 0x0000 n 0x003F.

Xt v d instruction OUT dng xut gi tr ra cc thanh ghi I/O, lnh ny s

dng a ch kiu thanh ghi, cu trc ca lnh nh sau: OUT A, Rr, trong A l

a ch ca thanh ghi trong vng nh I/O, Rr l thanh ghi RF, lnh OUT xut gi

tr t thanh ghi Rr ra thanh ghi I/O c a ch l A. Gi s chng ta mun xut gi

tr cha trong R6 ra thanh ghi iu khin hng ca PORTD, tc thanh ghi

DDRD, a ch tnh theo vng I/O ca thanh ghi DDRD l 0x0011, nh th cu

lnh ca chng ta s c dng: OUT 0x0011, R6. Tuy nhin trong 1 trng hp

khc, nu mun truy xut DDRD theo dng SRAM, v d lnh STS hay LDS, th

phi dng a ch tuyt i ca thanh ghi ny, tc gi tr 0x0031, khi lnh OUT

33

trn c vit li l STS 0x0031, R6.

thng nht cch s dng t ng, t by gi chng ta dng khi nim a

ch I/O cho cc thanh ghi trong vng nh I/O ni n a ch khng tnh phn

Register File, khi nim a ch b nh ca thanh ghi l ch a ch tuyt i

ca chng trong SRAM. V d thanh ghi DDRD c a ch I/O l 0x0011 v

a ch b nh ca n l 0x0031, a ch b nh = a ch I/O + 0x0020.

V cc thanh ghi trong vng I/O khng c hiu theo tn gi nh cc Register

file, khi lp trnh cho cc thanh ghi ny, ngi lp trnh cn nh a ch ca tng

thanh ghi, y l vic tng i kh khn. Tuy nhin, trong hu ht cc phn mm

lp trnh cho AVR, a ch ca tt c cc thanh ghi trong vng I/O u c nh

ngha trc trong 1 file Definition, bn ch cn nh km file ny vo chng trnh

ca bn l c th truy xut cc thanh ghi vi tn gi ca chng. Gi s trong v d

bi 1, lp trnh cho chip Atmega8 bng AVRStudio, dng th 2 chng ta s

dng INCLUDE "M8DEF.INC" load file nh ngha cho chip ATMega8, file

M8DEF.INC. V vy, trong sau ny khi mun s dng thanh ghi DDRD bn ch

cn gi tn ca chng, nh: OUT DDRD,R6.

Phn 3: RAM tnh, ni (internal SRAM), l vng khng gian cho cha cc

bin (tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny tng t

cc thanh RAM trong my tnh nhng c dung lng kh nh (khong vi KB,

ty thuc vo loi chip).

Phn 4: RAM ngoi (external SRAM), cc chip AVR cho php ngi s dng

gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi no

ngi s dng gn thm b nh ngoi vo chip.

Phn 5: EEPROM (Electrically Ereasable Programmable ROM) l mt phn

quan trng ca cc chip AVR mi, v l ROM nn b nh ny khng b xa ngay

c khi khng cung cp ngun nui cho chip, rt thch hp cho cc ng dng lu

tr d liu. Nh trong hnh 1, phn b nh EEPROM c tch ring v c a

34

ch tnh t 0x0000.

S t chc b nh

2.1.4 Cc Thanh Ghi

1. Thanh ghi SREG (STATUS REGISTRY). Nm trong vng nh I/O, thanh ghi SREG c a ch I/O l 0x003F v a ch

b nh l 0x005F (thng y l v tr cui cng ca vng nh I/O) l mt trong

s cc thanh ghi quan trng nht ca AVR, v th m ti dnh phn ny gii

thiu v thanh ghi ny. Thanh ghi SREG cha 8 bit c (flag) ch trng thi ca b

x l, tt c cc bit ny u b xa sau khi reset, cc bit ny cng c th c c

v ghi bi chng trnh. Chc nng ca tng bit c m t nh sau:

35

Bit 0 C (Carry Flag: C nh): l bit nh trong cc php i s hoc logic, v d thanh ghi R1 cha gi tr 200, R2 cha 70, chng ta thc hin php cng c

nh: ADC R1, R2, sau php cng, kt qu s c lu li trong thanh ghi R1,

trong khi kt qu thc l 270 m thanh ghi R1 li ch c kh nng cha ti a gi

tr 255 (v c 8 bit) nn trong trng hp ny, gi tr lu li trong R1 thc cht ch

l 14, ng thi c C c set ln 1 (v 270=100001110, trong 8 bit sau

00001110 =14 s c lu li trong R1).

Bit 1 Z (Zero Flag: C 0): c ny c set nu kt qu php ton i s hay php Logic bng 0.

Bit 2 N (Negative Flag: C m): c ny c set nu kt qu php ton i s hay php Logic l s m.

Bit 3 V (Twos complement Overflow Flag: C trn ca b 2): hot ng ca c ny c v s kh hiu cho bn v n lin quan n kin thc s nh phn

(phn b), chng ta s cp n khi no thy cn thit.

Bit 4 S (Sign Bit: Bit du): Bit S l kt qu php XOR gia 1 c N v V, S=N xor V.

Bit 5 H (Half Carry Flag: C nh na): c H l c nh trong 1 vi php ton i s v php Logic, c ny hiu qu i vi cc php ton vi s BCD.

Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit LoaD) v BST (Bit STorage). Ti s gii thch chc nng Bit T trong phn gii

36

thiu v BLD v BST.

Bit 7 I (Global Interrupt Enable) : Cho php ngt ton b): Bit ny phi c set ln 1 nu trong chng trnh c s dng ngt. Sau khi set bit ny, bn

mun kch hot loi ngt no cn set cc bit ngt ring ca ngt . Hai instruction

dng ring Set v Clear bit I l SEI v CLI.

Ch : tt c cc bit trong thanh ghi SREG u c th c xa thng qua cc

instruction khng ton hng CLx v set bi SEx, trong x l tn ca Bit.V d

CLT l xa Bit T v SEI l set bit I.

Ti ch gii thch ngn gn chc nng ca cc bit trong thanh ghi SREG, c th

chc nng v cch s dng ca tng bit chng ta s tm hiu trong cc trng hp

c th sau ny, ngi c c th t tm hiu thm trong cc ti liu v

INSTRUCTION cho AVR.

Ti cung cp thm 1 bng tm tt s nh hng ca cc php ton i s, logic

ln cc Bit trong thanh ghi SREG.

2. Thanh ghi MCUCR:

MCUCR l mt thanh ghi 8 bit nhng i vi hot ng ngt ngoi, chng ta ch

quan tm n 4 bit thp ca thanh ghi ny (4 bit cao dng cho Power manager v

Sleep Mode), 4 bit thp l cc bit Interrupt Sense Control (ISC), 2 bit ISC11,

ISC10 dng cho INT1 v ISC01, ISC00 dng cho INT0. Hy nhn vo bng tm

tt bn di bit chc nng ca cc bit trn, y l bng chn tr ca 2 bit

ISC11, ISC10. Bng chn tr cho cc bit ISC01, ISC00 hon ton tng t.

37

Tht d dng hiu chc nng ca cc bit Sense Control, v d bn mun set

cho INT1 l ngt cnh xung (Falling Edge) trong khi INT0 l ngt cnh ln

(Rising Edge), hy t dng lnh MCUCR =0x0B (0x0B = 00001011 nh phn)

trong chng trnh ca bn.

3. Thanh ghi GICR:

Thanh ghi iu khin ngt thng thng GICR (General Interrupt Control

Register) (trn cc chip AVR c, nh cc chip AT90Sxxxx, thanh ghi ny c tn

l thanh ghi mt n ngt thng thng GIMSK, bn tham kho thm datasheet ca

cc chip ny nu cn s dng n). GICR cng l 1 thanh ghi 8 bit nhng ch c 2

bit cao (bit 6 v bit 7) l c s dng cho iu khin ngt, cu trc thanh ghi nh

bn di (trch datasheet).

Bit 7 INT1 gi l bit cho php ngt 1(Interrupt Enable), set bit ny bng 1

ngha bn cho php ngt INT1 hot ng, tng t, bit INT0 iu khin ngt

38

INT0.

4. Thanh ghi GIFR:

Thanh ghi c ngt thng thng GIFR (General Interrupt Flag Register) c 2 bit

INTF1 v INTF0 l cc bit trng thi (hay bit c - Flag) ca 2 ngt INT1 v INT0,

nu c 1 s kin ngt ph hp xy ra trn chn INT1, bit INTF1 c t ng set

bng 1 (tng t cho trng hp ca INTF0), chng ta c th s dng cc bit ny

nhn ra cc ngt, tuy nhin iu ny l khng cn thit nu chng ta cho php

ngt t ng, v vy thanh ghi ny thng khng c quan tm khi lp trnh ngt

ngoi. Cu trc thanh ghi GIFR c trnh by trong hnh ngay bn di.

5. Thanh ghi TCCR0:

TCCR0 (Timer/Counter Control Register): l thanh ghi iu khin hot ng ca T/C0. Tuy l thanh ghi 8 bit nhng thc cht ch c 3 bit c tc

dng l CS00, CS01 v CS02.

Cc bit CS00, CS01 v CS02 gi l cc chip chn ngun xung nhp cho T/C0

(Clock Select). Chc nng cc bit ny c m t trong bng 1.

Bng 1: chc nng cc bit CS0X

39

6. Thanh ghi TCNT0:

TCNT0 (Timer/Counter Register): l 1 thanh ghi 8 bit cha gi tr vn hnh ca T/C0. Thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip.

7. Thanh ghi TIMSK:

TIMSK (Timer/Counter Interrupt Mask Register): l thanh ghi mt n cho ngt ca tt c cc T/C trong Atmega8, trong ch c bit TOIE0 tc bit s 0 (bit u

tin) trong thanh ghi ny l lin quan n T/C0, bit ny c tn l bit cho php ngt

khi c trn T/C0. Trn (Overflow) l hin tng xy ra khi b gi tr trong thanh

ghi TCNT0 t n MAX (255) v li m thm 1 ln na.

Bit 1, TOIE0=1, bit quy nh ngt trn cho thanh T/C0.

Bit 2, TOIE1, bit quy nh ngt trn cho thanh T/C1.

40

Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh

TCNT1 vi OCR1B.

Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh

TCNT1 vi OCR1A.

Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng.

Bit 6, TOIE2, bit quy nh ngt trn cho thanh T/C2.

Bit 7, OCIE2 l bit cho php ngt khi c 1 Match xy ra trong vic so snh

TCNT2 vi OCR2.

8. Thanh ghi TIFR:

TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0.

Khi c ngt trn xy ra, bit ny t ng c set ln 1.

9. Thanh ghi TCNT1:

TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8 bit to thnh thanh ghi 16 bits (TCNT1) cha gi tr vn hnh ca T/C1. C 2 thanh ghi ny cho

php bn c v ghi gi tr mt cch trc tip. 2 thanh ghi c kt hp nh sau:

41

10. Thanh ghi TCCR1:

TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh ghi iu khin hot ng ca T/C1. Tt c cc mode hot ng ca T/C1 u c xc

nh thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, y khng phi l 2 byte

cao v thp ca mt thanh ghi m l 2 thanh ghi hon ton c lp. Cc bit trong 2

thanh ghi ny bao gm cc bit chn mode hay chn dng sng (Waveform

Generating Mode WGM), cc bit quy nh dng ng ra (Compare Output Match

COM), cc bit chn gi tr chia prescaler cho xung nhp (Clock Select CS)

Cu trc ca 2 thanh ghi c trnh by nh bn di.

Nhn chung thuc ht cch phi hp cc bit trong 2 thanh ghi TCCR1A

v TCCR1B l tng i phc tp v T/C1 c rt nhiu mode hot ng, chng ta

s kho st chng trong phn cc ch hot ng ca T/C1 bn di. y,

trong thanh ghi TCCR1B c 3 bit kh quen thuc l CS10, CS11 v CS12. y l

cc bit chn xung nhp cho T/C1 nh truong T/C0. Bng 2 s tm tt cc ch

42

xung nhp trong T/C1.

Bng 2: chc nng cc bit CS12, CS11 v CS10.

Cc mode hot ng: c tt c 5 ch hot ng chnh trn T/C1. Cc ch

hot ng c bn c quy nh bi 4 bit Waveform Generation Mode (WGM13,

WGM12, WGM11 WGM10) v mt s bit ph khc. 4 bit Waveform Generation

Mode li c b tr nm trong 2 thanh ghi TCCR1A v TCCR1B (WGM13 l bit

4, WGM12 l bit 3 trong TCCR1B trong khi WGM11 l bit 1 v WGM10 l bit 0

trong thanh ghi TCCR1A) v th cn phi hp 2 thanh ghi TCCR1 trong lc iu

khin T/C1. Cc ch hot ng ca T/C1 c tm tt trong bng sau 3:

Bng 3: cc bit WGM v cc ch hot ng ca T/C1.

43

Ch cc bit COM1A1, COM1A0 v COM1B1, COM1B0 l cc bit chn dng

tn hiu ra ca PWM (Compare Output Mode bits). COM1A1, COM1A0 dng cho

knh A v COM1B1, COM1B0 dng cho knh B. Hy i chiu bng 4.

Bng 4: m t cc bit COM trong ch fast PWM.

44

11. Thanh ghi OCR1:

OCR1A v OCR1B (Ouput Compare Register A v B): c mt s khi nim mi m chng ta cn bit khi lm vic vi T/C1, mt trong s l Ouput

Compare (sorry, I dont wanna translate it to Vietnamese). Trong lc T/C hot

ng, gi tr thanh ghi TCNT1 tng, gi tr ny c lin tc so snh vi cc thanh

ghi OCR1A v OCR1B (so snh c lp vi tng thanh ghi), vic so snh ny trn

AVR gi l gi l Ouput Compare. Khi gi tr so snh bng nhau th 1 Match

xy ra, khi mt ngt hoc 1 s thay i trn chn OC1A (hoc/v chn OC1B)

xy ra (y l cch to PWM bi T/C1). Ti sao li c A v B? l v ngi

thit k AVR mun m rng kh nng ng dng T/C1 cho bn. A v B i din

cho 2 knh (channel) v B. Cng v iu ny m chng ta c th to 2 knh PWM

bng T/C1. Tm li, c bn 2 thanh ghi ny cha cc gi tr so snh, chc nng

v cc ch hot ng c th ca chng s c kho st trong cc phn sau.

45

12. Thanh ghi ICR1:

ICR1 (InputCapture Register 1): khi nim mi th 2 ca T/C1 l Input Capture. Khi c 1 s kin trn chn ICP1 (chn 14 trn Atmega8), thanh ghi

ICR1s capture gi tr ca thanh ghi m TCNT1. Mt ngt c th xy ra trong

trng hp ny, v th Input Capture c th c dng cp nht gi tr TOP

ca T/C1.

13. Thanh ghi UDR:

UDR: hay thanh ghi d liu, l 1 thanh ghi 8 bit cha gi tr nhn c v pht i ca USART. Thc cht thanh ghi ny c th coi nh 2 thanh ghi TXB

(Transmit data Buffer) v RXB (Reveive data Buffer) c chung a ch. c UDR

thu c gi tr thanh ghi m d liu nhn, vit gi tr vo UDR tng ng t

gi tr vo thanh ghi m pht, chun b gi i. Ch trong cc khung truyn

s dng 5, 6 hoc 7 bit d liu, cc bit cao ca thanh ghi UDR s khng c s

dng

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14. Thanh ghi UCSRA:

UCSRA (USART Control and Status Register A): l 1 trong 3 thanh ghi iu khin hot ng ca module USART.

Thanh ghi UCSRA ch yu cha cc bit trng thi nh bit bo qu trnh nhn

kt thc (RXC), truyn kt thc (TXC), bo thanh ghi d liu trng (UDRE),

khung truyn c li (FE), d liu trn (DOR), kim tra parity c li (PE)Bn

ch mt s bit quan trng ca thanh ghi ny:

* UDRE (USART Data Register Empty) khi bit by bng 1 ngha l thanh ghi d

liu UDR ang trng v sn sng cho mt nhim v truyn hay nhn tip theo. V

th nu bn mun truyn d liu u tin bn phi kim tra xem bit UDRE c

bng 1 hay khng, sau khi chc chn rng UDRE=1 hy vit d liu vo thanh ghi

UDR truyn i.

* U2X l bit ch nh gp i tc truyn, khi bit ny c set ln 1, tc

truyn so cao gp 2 ln so vi khi bit ny mang gi tr 0.

* MPCM l bit chn ch hot ng a x l (multi-processor).

15. Thanh ghi UCSRB:

UCSRB (USART Control and Status Register B): y l thanh ghi quan trng iu khin USART. V th chng ta s kho st chi tit tng bit ca thanh ghi ny.

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* RXCIE (Receive Complete Interrupt Enable) l bit cho php ngt khi qu trnh

nhn kt thc. Vic nhn d liu truyn bng phng php ni tip khng ng b

thng c thc hin thng qua ngt, v th bit ny thng c set bng 1 khi

USART c dung nhn d liu.

* TXCIE (Transmit Complete Interrupt Enable) bit cho php ngt khi qu trnh

truyn kt thc.

* UDRIE (USART Data Register Empty Interrupt Enable) l bit cho php ngt khi

thanh ghi d liu UDR trng.

* RXEN (Receiver Enable) l mt bit quan trng iu khin b nhn ca USART,

kch hot chc nng nhn d liu bn phi set bit ny ln 1.

* TXEN (Transmitter Enable) l bit iu khin b pht. Set bit ny ln 1 bn s

khi ng b pht ca USART.

* UCSZ2 (Chracter size) bit ny kt hp vi 2 bit khc trong thanh ghi UCSRC

quy nh di ca d liu truyn/nhn. Chng ta s kho st chi tit khi tm hiu

thanh ghi UCSRC.

* RXB8 (Receive Data Bit 8) gi l bit d liu 8. Bn nh li rng USART trong

AVR c h tr truyn d liu c di ti a 9 bit, trong khi thanh ghi d liu l

thanh ghi 8 bit. Do , khi c gi d liu 9 bit c nhn, 8 bit u s cha trong

thanh ghi UDR, cn c 1 bit khc ng vai tr bit th chn, RXD8 l bit th chn

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ny. Bn ch l cc bit c nh s t 0, v th bit th chn s c ch s l 8, v

l m bit ny c tn l RXD8 (khng phi RXD9).

* TXB8 (Transmit Data Bit 8), tng t nh bit RXD8, bit TXB8 cng ng vai

tr bit th 9 truyn thng, nhng bit ny c dung trong lc truyn d liu.

16. Thanh ghi UCSRC:

UCSRC (USART Control and Status Register C): thanh ghi ny ch yu quy nh khung truyn v ch truyn. Tuy nhin, c mt rc ri nho nh l thanh

ghi ny li c cng a ch vi thanh ghi UBRRH (thanh ghi cha byte cao dng

xc lp tc baud), ni mt cch khc 2 thanh ghi ny l 1. V th bit 7 trong

thanh ghi ny, tc bit URSEL l bit chn thanh ghi. Khi URSEL=1, thanh ghi ny

c chip AVR hiu l thanh ghi iu khin UCSRC, nhng nu bit URSEL=0 th

thanh ghi UBRRH s c s dng.

Cc bit cn li trong thanh ghi UCSRC c m t nh sau:

* UMSEL (USART Mode Select) l bit la chn gia 2 ch truyn thng ng

b v khng ng b. Nu UMSEL=0, ch khng ng b c chn, ngc

li nu UMSEL=1, ch ng b c kch hot.

* Hai bit UPM1 v UPM0( Parity Mode) c dng quy nh kim tra pariry.

Nu UPM1:0=00, parity khng c s dng (mode ny kh thng dng),

UPM1:0=01 khng c s dng, UPM1:0=10 th parity chn c dng,

UPM1:0=11 parity l c s dng (xem thm bng 1).

Bng 1: chn kim tra parity.

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* USBS (Stop bit Select), bit Stop trong khung truyn bng AVR USART c th

l 1 hoc 2 bit, nu USBS=0 th Stop bit ch l 1 bit trong khi USBS=1 s c 2

Stop bit c dng.

* Hai bit UCSZ1 v UCSZ2 (Character Size) kt hp vi bit UCSZ2 trong thanh

ghi UCSRB to thnh 3 bit quy nh di d liu truyn. Bng 2 tm tt cc gi

tr c th c ca t hp 3 bit ny v di d liu truyn tng ng.

Bng 2: di d liu truyn.

* UCPOL (Clock Pority) l bit ch cc ca xung kch trong ch truyn thng

ng b. nu UCPOL=0, d liu s thay i thay i cnh ln ca xung nhp,

nu UCPOL=1, d liu thay i cnh xung xung nhp. Nu bn s dng ch

truyn thng khng ng b, hy set bit ny bng 0..

17. Thanh ghi UBRR:

UBRRL v UBRRH (USART Baud Rate Register): 2 thanh ghi thp v cao quy nh tc baud.

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Nhc li l thanh ghi UBRRH dng chung a ch thanh ghi UCSRC, bn phi

set bit ny bng 0 nu mun s dng thanh ghi UBRRH. Nh bn quan st trong

hnh trn, ch c 4 bit thp ca UBRRH c dng, 4 bit ny kt hp vi 8 bit

trong thanh ghi UBRRL to thnh thanh ghi 12 bit quy nh tc baud. Ch l

nu bn vit gi tr vo thanh ghi UBRRL, tc baud s tc th c cp nht, v

th bn phi vit gi tr vo thanh ghi UBRRH trc khi vit vo thanh ghi

UBRRL.

Gi tr gn cho thanh ghi UBRR khng phi l tc baud, n ch c

USART dng tnh tc baud. Bng 3 hng dn cch tnh tc baud da

vo gi tr ca thanh ghi UBRR v ngc li, cch tnh gi tr cn thit gn cho

thanh ghi UBRR khi bit tc baud.

Bng 3: tnh tc baud.

Trong cc cng thc trong bng 3, fOSC l tc tn s xung nhp ca h thng

(thch anh hay ngun xung ni). tin cho bn theo di, ti nh km bng v

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d cch t gi tr cho UBRR theo tc baud mu.

Bng 4: mt s tc baud mu.

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18. Thanh ghi ADMUX:

ADMUX (ADC Multiplexer Selection Register): l 1 thanh ghi 8 bit iu khin

vic chn in p tham chiu, knh v ch hot ng ca ADC. Chc nng ca

tng bit trn thanh ghi ny s c trnh by c th nh sau:

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Bit 7:6- REFS1:0 (Reference Selection Bits): l cc bit chn in p tham chiu cho ADC, 1 trong 3 ngun in p tham chiu c th c chn l: in p

ngoi t chn VREF, in p tham chiu ni 2.56V hoc in p AVCC. Bng 2

tm tt gi tr cc bit v in p tham chiu tng ng.

Bit 5-ADLAR (ADC Left Adjust Result): l bit cho php hiu chnh tri kt qu chuyn i. S d c bit ny l v ADC trn AVR c phn gii 10 bit, ngha

l kt qu thu c sau chuyn i l 1 s c di 10 bit (ti a 1023), AVR b

tr 2 thanh ghi data 8 bit cha gi tr sau chuyn i. Nh th gi tr chuyn i

s khng lp y 2 thanh ghi data, trong mt s trng hp ngi dng mun 10

bit kt qu nm lch v pha tri trong khi cng c trng hp ngi dng mun

kt qu nm v pha phi. Bit ADLAR s quyt nh v tr ca 10 bit kt qu trong

16 bit ca 2 thanh ghi data. Nu ADLAR=0 kt qu s c hiu chnh v pha

phi (thanh ghi ADCL cha trn 8 bit thp v thanh ghi ADCH cha 2 bit cao

trong 10 bit kt qu), v nu ADLAR=1 th kt qu c hiu chnh tri (thanh ghi

ADCH cha trn 8 bit cao nht, cc bit t 9 n 2, v thanh ADCL cha 2 bit thp

nht trong 10 bit kt qu (bn xem hnh cch b tr 2 thanh ghi ADCL v ADCH

bn di hiu r hn).

Bits 4:0-MUX4:0 (Analog Channel and Gain Selection Bits): l 5 bit cho php chn knh, ch v c h s khuych i cho ADC. Do b ADC trn AVR c

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nhiu knh v cho php thc hin chuyn i ADC kiu so snh (so snh in p

gia 2 chn analog) nn trc khi thc hin chuyn i, chng ta cn set cc bit

MUX chn knh v ch cn s dng. Bng 3 tm tt cc ch hot ng

ca ADC thng qua cc gi tr ca cc bit MUX. Trong bng ny, ng vi cc gi

tr t 00000 n 00111 (nh phn), cc knh ADC c chn ch n knh

(tn hiu input ly trc tip t cc chn analog v so snh vi 0V), gi tr t 01000

n 11101 tng ng vi ch chuyn i so snh.

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19. Thanh ghi ADCSRA:

ADCSRA (ADC Control and Status RegisterA): l thanh ghi chnh iu khin

hot ng v cha trng thi ca module ADC.

Tng bit ca thanh ghi ADCSRA c m t nh bn di:

Bit 7 - ADEN(ADC Enable): vit gi tr 1 vo bit ny tc bn cho php module ADC c s dng. Tuy nhin khi ADEN=1 khng c ngha l ADC

hot ng ngay, bn cn set mt bit khc ln 1 bt u qu trnh chuyn i,

l bit ADSC.

Bit 6 - ADSC(ADC Start Conversion): set bit ny ln 1 l bt u khi ng qu trnh chuyn i. Trong sut qu trnh chuyn i, bit ADSC s c gi

nguyn gi tr 1, khi qu trnh chuyn i kt thc (t ng), bit ny s c tr v

0. V vy bn khng cn v cng khng nn vit gi tr 0 vo bit ny bt k tnh

hung no. thc hin mt chuyn i, thng thng chng ta s set bit

ADEN=1 trc v sau set ADSC=1.

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Bit 4 ADIF(ADC Interrupt Flag): c bo ngt. Khi mt chuyn i kt thc, bit ny t ng c set ln 1, v th ngi dng cn kim tra gi tr bit ny trc

khi thc hin c gi tr chuyn i m bo qu trnh chuyn i thc s

hon tt.

Bit 3 ADIE(ADC Interrupt Enable): bit cho php ngt, nu bit ny c set bng 1 v bit cho php ngt ton cc (bit I trong thanh ghi trng thi ca chip)

c set, mt ngt s xy ra khi mt qu trnh chuyn i ADC kt thc v cc gi

tr chuyn i c cp nht (cc gi tr chuyn i cha trong 2 thanh ghi

ADCL v ADCH).

Bit 2:0 ADPS2:0(ADC Prescaler Select Bits): cc bit chn h s chia xung nhp cho ADC. ADC, cng nh tt c cc module khc trn AVR, cn c gi

nhp bng mt ngun xung clock. Xung nhp ny c ly t ngun xung chnh

ca chip thng qua mt h s chia. Cc bit ADPS cho php ngi dng chn h s

chia t ngun clock chnh n ADC. Tham kho bng 4 bit cch chn h s

chia.

20. Thanh ghi ADC:

ADCL v ADCH (ADC Data Register): 2 thanh ghi cha gi tr ca qu trnh

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chuyn i. Do module ADC trn AVR c phn gii ti a 10 bits nn cn 2

thanh ghi cha gi tr chuyn i. Tuy nhin tng s bt ca 2 thanh ghi 8 bit l

16, con s ny nhiu hn 10 bit ca kt qu chuyn i, v th chng ta c php

chn cch ghi 10 bit kt qu vo 2 thanh ghi ny. Bit ADLAR trong thanh ghi

ADMUX quy nh cch m kt qu c ghi vo.

Thng thng, 2 thanh ghi data c sp xp theo nh dng ADLAR=0,

ADCL cha 8 bit thp v 2 bit thp ca ADCH cha 2 bit cao nht ca gi tr thu

c. Ch th t c gi tr t 2 thanh ghi ny, trnh c sai kt qu, bn cn

c thanh ghi ADCL trc v ADCH sau, v sau khi ADCH c c, cc thanh

ghi data c th c cp nht gi tr tip theo.

21. Thanh ghi SFIOR:

SFIOR(Special FunctionIO Register C): thanh ghi chc nng c bit, 3 bit cao

trong thanh ghi ny quy nh ngun kch ADC nu ch Auto Trigger c s

dng. l cc bit ADTS2:0 (Auto Trigger Source 2:0). Cc loi ngun kch

c trnh by trong bng 5.

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22. Thanh ghi SPCR:

SPCR (SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ng ca SPI.

* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c set

bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy ra sau

61

khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l i

vi chip Slave) khi truyn nhn d liu vi SPI.

* Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. Nu

SPIE=0 th module SPI dng hot ng.

* Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit c truyn

v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln nht ca

d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn

trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng

nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves.

* Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din l

Master, ngc li MSTR=0 th chip l Slave..

* Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhp v

cnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit ny

to thnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khng quan

trng nhng phi m bo Master v Slave cng ch hot ng. V th c th

2 bit ny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liu

trong 4 ch ca SPI trn AVR.

* Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR cho

php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun

xung clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVR

c th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp

cho chip.

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23. Thanh ghi SPSR:

SPSR (SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trong thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi

d liu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6

WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1

nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi

qu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc

truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp

tc cho SPI.

24. Thanh ghi SPDR:

SPDR (SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghi gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave,

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d liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn

trong SPDR s c truyn cho Master.

25. Thanh ghi EEAR:

a ch thanh ghi EEPROM s truy xut.

26. Thanh ghi EEDR:

Cha gi tr s ghi hoc c t EEPROM.

27. Thanh ghi EECR:

Bit 3 - EERIE - EEPROM Ready Interrupt Enable: cho php ngt khi

EEPROM sn sang nhn them d liu. Ngt ny c sinh ra sau khi EEWE b

xa.

Bit 2 - EEMWE - EEPROM Master Write Enable: quyt nh c cho php

viec ghi 1 vo EEWE s thc hin vic ghi EEPROM hay khng. Gi tr

EEMWE l 1(0) tng ng vi (khng) cho php. Sau khi ghi 1 vo EEMWE, n

s b xa bng phn cng sau 4 xung clock.

Bit 1 - EEWE - EEPROM Write Enable: set ln 1 s bt u vic ghi vo

EEPROM (xem thm EEMWE).

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Bit 0 - EERE - EEPROM Read Enable: set ln 1 s bt u vic c t

EEPROM.

28. Thanh ghi port xut nhp:

Thanh ghi DDRx (x tn port B,C,D):

Thanh ghi iu khin vic c hoc xut ra port, DDRx=0 cu hnh l

port c d liu, ngc li DDRx=255 cu hnh l port xut d liu.

Thanh ghi PORTx (x tn port B,C,D):

Thanh ghi cha gi tr s xut ra port.

Thanh ghi PINx (x tn port B,C,D):

Thanh ghi cha gi tr c vo t port.

2.2 KHO ST IC THU PHT TONE MT8888:MT8888 l mt IC thu pht DTMF trn b km theo mt b lc thoi (Call

Progress Filter). MT8888 l IC CMOS tiu th ngun thp. B thu DTMF da

trn k thut chun ca IC MT8870, cn gi l b pht DTMF s dng phng

php bin i D/A bin dung (Switched Capacitor) cho ra tn hu DTMF chnh

xc, t nhiu. Cc b m bn trong gip hnh thnh ch Burst Mode nh vy

cc cp tone xut ra vi thi hng chnh xc. B lc Call Progress cho php b vi

x l phn tch cc tone trng thi ng dy. Bus chun ca n kt hp MPU v

c bit thch hp h 6800 ca Motorola. MT8888 c 5 thanh ghi bn trong

giao tip vi vi x l, c th chia lm 3 loi:

Nhn pht d liu: 2 thanh ghi.

Thanh ghi trng thi.

Nhn t iu khin: 2 thanh ghi.

S khi bn trong IC MT8888

65

Hnh 2 1: S khi bn trong IC MT8888

2.2.1 S chn:

66

Hnh 2 2: S cc chn ca IC MT8888

Bng chc nng cc chn ca IC MT8888

PIN TN M T

1 IN+ Chn vo khng o ca OP-AMP

2 IN- Chn vo o ca OP AMP

3 GS Chn li cho b khuch i OP AMP

4 VREFu ra in p tnh VDD/2 c dng cn bng tnh

u vo.

5 VSS Ground (0V)

6 OSC1 u vo b dao ng thch anh.

7 OSC2

u ra ca b dao ng, dao ng thch anh 3.579545

MHz c ni gia OSC1 v OSC2 to thnh dao ng

dng in bn trong vi mch.

8 TONE Ng ra tone DTMF.

9 WR\ Chn ra CPU iu khin trc tip vit d liu.

10 CS\ Ng vo chip Select, tc ng mc thp

11 RSO Chn chn Register.

67

12 RD\ Chn CPU iu khin trc tip c d liu

13 IRQ/CP

Yu cu ngt gi ti MPU (Chn cc mng h). Khi Mode

Call Progress (CP)v Mode Interrupt cng c chn,

chn IRQ/CP s a ra dng sng hnh ch nht c trng

cho tn hiu u vo OP.AMP vi iu kin tn hiu u

vo ny phi nm trong di thng ca b lc thng di.

1417 D0-D3 Data Bus

18 Est

(Early Steering Output). Cho ra mc logic 1 khi pht hin

c mt cp tone hp l. Bt k trng thi no khng c

tn hiu hp l u cho ra logic 0.

19 St/GT

(Steering Output/ Guard Time Output 2 chiu). Mt cp

in p ln hn VEST khi xut hin ti ST lm cho thit b

ghi nhn cp tone v truy cp b cht ng ra.Mt in p

nh hn VEST gii phng thit b thu nhn cp tone

mi. Ng ra GT lm nhim v reset mch nh thi bn

ngoi. Trng thi ca n l mt hm ca VEST theo in

p ti chn ST.

20 VDD Ngun cung cp dng (c 5V)

2.2.2 M t chc nng:

MT8888 bao gm b thu DTMF cht lng cao (km b khuch i)

v mt b to DTMF s dng Burst Counter gip cho vic tng hp ng

ngt Tone c chnh xc. Ngoi ra ta c th chn ch Call Progress

gip pht hin cc tn s nm trong gii thng thoi. l cc tn hiu trng

thi ng dy.

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2.2.3 Cu hnh ng vo:

Thit k u vo ca MT8888 cung cp mt b khuch i OPAMP

ng vo vi sai cng nh mt ng vo VREF iu chnh thin p cho u

vo ti VDD/2. Chn GS gip ni ng ra b khuch i vi ng vo qua mt

in tr ngoi iu chnh li.

Hnh 2 3: Cu hnh ng vo ca MT8888

2.2.4 B thu:Hai b lc bng thng bc 6 gip tch cc tone trong cc nhm tone LOW

v HIGH. u ra mi b lc in dung gip nn dng tn hiu trc khi qua b

hn bin. Vic hn bin c m nhim bi b so snh (Comparator) c km

theo b tr trnh chn lm tn hiu mc thp khng mong mun. u ra ca b

so snh cho ta cc dao ng c mc logic ti tn s DTMF thu c.

Tip theo phn lc l b gii m s dng k thut m s kim tra tn s

ca cc tone thu c v bo m chng tng ng vi cc tn s DTMF chun.

Mt k thut ly trung bnh phc gip loi tr cc tone gi to thnh do ting ni

trong khi vn m bo mt khong bin ng cho tone thu do b lch. Khi b kim

tra nhn dng c hai tone ng th u ra early steering (EST) s ln mc

69

kch hot( Active). Lc khng nhn c tn hiu tone th EST s mc Inactive.

Bng m ha cc tn hiu quay s DTMF

FLOW FHIGH DIGIT D3 D2 D1 D0697 1209 1 0 0 0 1

697 1336 2 0 0 1 0

697 1477 3 0 0 1 1

770 1209 4 0 1 0 0

770 1336 5 0 1 0 1

770 1477 6 0 1 1 0

852 1209 7 0 1 1 1

852 1336 8 1 0 0 0

852 1477 9 1 0 0 1

941 1336 0 1 0 1 0

941 1209 * 1 0 1 1

941 1477 # 1 1 0 0

697 1633 A 1 1 0 1

770 1633 B 1 1 1 0

852 1633 C 1 1 1 1

941 1633 D 0 0 0 0

2.2.5 Mch STEERING:Trc khi thu nhn mt cp tone gii m, b thu phi kim tra xem thi

hng ca tn hiu c ng khng. Vic kim tra ny c thc hin bi mt b RC

mc ngoi. Khi Est ln HIGH lm cho Vc tng ln khi t x. Khi m Est vn cn

HIGH trong mt thi on hp l( tone) th Vc tin ti mc ngng VSTt ca

logic Steering nhn mt cp tone v cht 4 bit m tng ng vi n vo thanh

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ghi Receive Data Register. Lc ny, u ra GT c kch hot v y Vc ln ti

VDD. Cui cng sau mt thi gian delay ngn cho php vic cht Data thc hin

xong th c ca mch Steering ln HIGH bo hiu rng cp tone thu c c

lu vo thanh ghi. Ta c th kim tra bit tng ng trong thanh ghi trng thi. Nu

ta cho Mode Interrupt th chn IRQ/CP s xung LOW khi c ny c kch hot.

D liu thu c s i ra Databus (2 chiu) khi thanh ghi Receive Data c c.

Mch steering li hot ng nhng theo chiu ngc li kim tra khong dng

gia hai s c quay. V vy b thu va b qua tn hiu qu ngn khng hp l

va khng chp nhn cc khong ngt qu nh khng th coi l khong dng gia

cc s. Chc nng ny cng nh kh nng chn thi hng Steering bng mch

ngoi cho php ngi thit k iu chnh hot ng cho ph hp vi cc i hi

khc nhau ca tng ng dng.

Hnh 2 4: Mch Steering

2.2.6 B lc thoi:Mode Call Progress khi c chn th cho php kim tra cc tone khc

nhau th hin trng thi ng dy. u vo ca Call Progress v mode tone

DTMF l chung nhng tone Call Progress ch c th kim tra nu ta chn mode

CP. DTMF tone li khng th nhn dng c nu ta chn mode CP.

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Cc tn s a n u vo +IN v IN nm trong gii hn bng thng

chp nhn ca b lc (280-550 Hz) s a qua b so snh c li cao v n

chn IRQ/CP. Dng sng u ra to bi mch trigger c th phn tch bi vi x

l xc nh tnh cht ca cc tone trng thi ng dy. Cc tn s trong vng

loi b s khng c kim tra v nh vy s khng c tn hiu no chn

IRQ/CP khi gp cc tn s ny.

2.2.7 B pht DTMF:B pht DTMF trong MT8888 c kh nng to tt c 16 cp tone DTMF

chun vi nhiu ti thiu v chnh xc cao. Tt c tn s ny u ly t dao

ng thch anh 3.579545 MHz mc ngoi. Dng sng sin ca tng tone c tng

hp s bng cch s dng b phn chia hng v ct tng hp c, v b bin i

D/A bin dung. Cc tone hng v ct c trn li v lc cho ra tn hiu DTMF

vi t hi v chnh xc cao. pht mt tn hiu DTMF th d liu tng ng

vi dng m bng 1 s phi c vit vo thanh ghi Transmit Data. Ch rng

m pht ny phi tng ng vi m nhn. Cc tone ring l c phn thnh hai

nhm l: nhm thp v nhm cao (low v high).

Cc s trong nhm tone thp l 697, 770, 852 v 941 (Hz).

Cc s trong nhm tone cao l: 1209, 1306, 1447 v 1663 (Hz).

2.2.8 Mch kch DTMF

Mch Clock tn s c tn s cng hng l 3.579545 MHz. Mt

nhm IC MT8888 c th ni chung li vi nhau dng chung mt dao ng

thch anh.

72

Hnh 2 5: Mch Clock DTMF

2.2.9 B giao tip vi vi x l:MT8888 s dng mt b giao tip vi x l cho php iu khin mt cch

chnh xc vi chc nng thu v pht. C tng cng 5 thanh ghi chia lm ba loi:

Thanh ghi d liu thu /pht, thanh ghi iu khin thu /pht v thanh ghi trng thi.

C hai thanh ghi d liu: thanh ghi Receive data cha m xut ra ca cp tone

DTMF hp l gn nht v l thanh ghi ch c. Data a vo thanh ghi Transmit

Data s qui nh cp tone no c pht i, Data ch c th c vo thanh ghi

ny.

iu khin thu pht tone c m nhn bi 2 thanh ghi Control Register

A v Control Register B( RA v CRB) c cng mt a ch. Mun ghi vo thanh

ghi CRB th trc phi c set mt bit tng ng CRA. Chu k ghi k tip vo

cng a ch vi CRA s cho php truy cp ti CRB. V chu k ghi k tip na s

tr li CRA. Khi cp in, mch in reset ni s xa cc thanh ghi iu khin.

Tuy vy, ngn nga th chng trnh phn mm nn c mt dng lnh kch

khi cc thanh ghi ny. Gi s rng thanh ghi pht rng sau khi reset, ta xem qua

cc bng bn di thy r chi tit v cc thanh ghi iu khin. Chn IRQ/CP c

th c lp trnh sao cho n c th cung cp tn hiu yu cu ngt sau khi nhn

xung DTMF hp l hay khi b pht sn sng cho data k tip (ch trong Burst

mode). Chn IRQ/CP l ng ra cc mng h v v th cn c mt in tr ko ln.

Thanh ghi nhn data cha m lnh xut ca gi tr cui cng cp tone

73

DTMF c gii m v ch l thanh ghi c data vo. Tn hiu data vo trong

thanh ghi pht s c nh r vi cp tone no m c pht sinh ra. Data ch c

th c vit vi thanh ghi pht.

Hai thanh ghi iu khin CRA v CRB ch chim ch trong mt khong a

ch tng ng ghp ghi vi CRB c th c thc hin bng cch t dnh ring

bit trong CRA php ghi tip theo ti a ch tng t s c trc tip a ti

CRB v tip theo sau cho chu k ghi s c trc tip tr li CRA.

Cch truy cp thanh ghi

RS0 WR\ RD\ CHC NNG

0 0 1 Ghi vo thanh ghi d liu pht

0 1 0 c t thanh ghi d liu thu

1 0 1 Ghi vo thanh ghi iu khin

1 1 0 c t thanh ghi trng thi

Trng thi thanh ghi CRA

B3 B2 B1 B0

REGISTER

SELECT

INTERRUPT

ENABLE

CP/DTMF MODE

\TONE OUT

Chc nng CRA (Control Register A)

BIT TN CCH S DNG

B0 TONE OUTPUT

Mc logic 1 cho php tone c pht ra. Chc

nng ny c th c thc hin trong Busrt

mode hoc None Busrt mode.

74

B1CP/DTMF MODE

\

Chn mode DTMF (mc 0) cho php thu v

pht tone ng thi. Khi chn mode CP

(mc1 b lc di bc 6) c kch hot cho

php kim tra cc tone trng thi ng dy(

call progress tone). Cc tone ny nu nm trong

di thng qui nh th c th hin chn

IRQ/CP dng sng hnh ch nht nu bit

IRQ c chn (CRA, B2=1).

B2INTERRUPT

ENABLE

Logic 1 cho php mode Interrup. Khi mode ny

mc tch cc v mode DTMF c chn (CRA,

1=0), ng ra IRQ/CP s b ko xung mc 0 khi:

+ Mt tn hiu DTMF hp l c nhn v

hin hu c trong khong thi gian an ton.

+ B pht sn sng cho data k tip( ch trong

Busrt mode).

B3REGISTER

SELECT

Logic 1 cho php CRB trong chu k ghi k tip

trn cng a ch ny. Chu k ghi k sau na s

tr li ghi vo CRA.

Trng thi thanh ghi CRB

B3 B2 B2 B0

COLUMN/ROW

TONE\

SINGLE/DUAL

TONETEST MODE BURST MODE\

Chc nng CRB (Control Register B)

BIT TN CCH S DNG

75

B0 BURST\

Mc 0 cho php chn Busrt mode khi mode ny c

chn, d liu tng ng vi cp tone DTMF c th c

vit vo thanh ghi pht to ra khong m tone vi thi

hng chun (51ms). K tip sau l khong ngt tone vi

thi hng tng t. Ngay sau khong ngt tone th thanh

ghi trng thi s c truy cp cho bit rng thanh ghi

pht sn sng cho cc lnh mi v mt ngt c to

ra nu mode Interrupt c chn trc . Khi CP

mode (CRA, B1) c chn th khong tone tt m t

51ms n 102 ms.

B1 TEST

Cho php chn Test Mode (logic 1). Khi chn IRQ/CP

s xut hin tn hiu Steering c lm tr t b thu

DTMF. DTMF Mode phi c chn (CRA, B1=0) trc

khi Test Mode c kch hot.

B2 S/D\

Mc logic 0 cho php tn hiu Dual Tone Multi

Frequency. Logic 1 chn ch tone n (single tone)

cho php to ra mt tone nhm thp hoc nhm cao da

vo trng thi ca bit B3 trong thanh ghi CRB.

B3 C/R\

S dng vi bit B2 trn. B pht c th c chn

pht tn s nm trn hng hay ct v mc logic 1 s chn

tn s ct, mc logic thp cho php chn hng.

Thanh ghi trng thi

BIT TNC TRNG THI

LP

C TRNG THI

XA

76

B0 IRQNgt xut hin. B1 hoc

B2 c lp.

Ngt cha kch hot. B

xa sau khi thanh ghi

trng thi c c.

B1

Thanh ghi d

liu pht

rng (ch

trong burst

mode)

Thi hng ngt tone

kt thc v b pht ang

ch d liu k tip.

B xa sau khi thanh ghi

trng thi c c hay

khi chn None_Burst

Mode.

B2Thanh ghi d

liu thu y

D liu hp l ang nm

trong thanh ghi d liu

thu.

B xa sau khi thanh trng

thi c c.

B3Delay

Steering

c lp khi pht hin

thy s khng xut hin

khng hp l ca tn hiu

DTMF

B xa sau khi pht hin

tn hiu DTMF hp l.

2.3 IC LM358:* LM358 l mt IC gm hai vi mch thut ton nm trong cng mt

v. Vi mch thut ton tiu chun l loi vi mch n khi tch hp ln

c ch to theo cng ngh mng mng. Nh kh nng tch hp ln nn

vi mch loi ny c ng dng rng ri trong thc t.

* u im ni bt ca vi mch l lm vic tt mc in p thp n

5VDC. Vi mch thut ton c cc c tnh chung nh sau:

C lch im tri v zero qu nh.

Khng cn b tn s, tng n nh ch lm vic tuyn tnh.

C bo v ngn mch v bo v qu ti.

77

Khng b kho nu tn hiu a vo khng thch hp.

H s nn dng pha ln.

Tiu hao cng sut nh.

78

2.3.1 S chn:

Hnh 2 7: S chn IC LM358

2.3.2 Chc nng cc chn:

Chc nng cc chn ca IC TL082

Chn Chc nng

1 Ng ra 1

2 Ng vo o 1

3 Ng vo khng o 1

4 -Vcc

79

5 Ng vo khng o 2

6 Ng vo o 2

7 Ng ra 2

8 +Vcc

2.3.3 Thng s:Ngun cung cp: VCC = 16V.

in p ng vo: Vi = -0.3->32V.

in p ng vo sai bit: Vid = 32V.

li AV = 100 dB.V mt nguyn l, vi mch l tng s c tng tr vo v cng ln, tng

tr ra v cng nh, tc d bm gi tn hiu ra vi tn hiu vo khng b gii hn

v c bng thng rt rng. Tuy nhin trn thc t khng th no c mt OPAMP

l tng nh vy.

V khuch i in p hay li:

Vi mch dng vng hi tip l mt vng h c li khong 100dB

Tng tr vo khong vi chc M

Tng tr ng ra khong n 100

Dng phn cc ng vo:khi dng transistor lng cc tn u vo, gi tr

IB c t 0,1A n 0,8A

Ngun cung cp:

Thng thng dng ngun lng cc khai thc ht hiu sut ca vi

mch.

Tn hiu vo khng vt qu VCC. Gi tr cc i cho php thng nh

hn VCC t 1 n 3V.

2.4 IC MAX232.Max-232 l IC thng c dng trong lnh vc giao tip vi my tnh, theo

chun RS-232, MAX-232 c nhiu loi, y ch cp n loi MAX-232E c

80

16 chn.

Vi in p l 5V th in ra ca ng xut s dao ng trong khong 8V khi

ti ng nhn c gi tr l 5k, trong iu kin ti t nht mc in p ti thiu

ng ra cng phi dao ng trong khong 5V.Gm c mt ti 3k, in p ti thiu,

v mt nhit hot ng ti a. Trong mt mch in m rng th in p ng ra

dao ng trong khong t (V+ - 0,6V) n V- . Ngng ng vo ca hai h

CMOS/TTL phi tng thch vi nhau. Max 232 khng c in tr ko ln ng

vo chn pht.

Hnh 2.4: Hnh dng v cu to ca max232

Ng nhn ca RS-232 s chuyn i tn hiu n ng ra ca con CMOS-

logic. m bo ngng vo ca ng nhn t c 0.8V v 2.4V th iu c

ngha l phi nh hn ngng 3V (theo bt buc v c im k thut ca

EIA/TIA-232E). iu ny cho php ng vo nhn (receiver) phn ng li mc

hp l ca TTL/CMOS cng ging nh ca RS-232.

Vic bo m ngng vo mc thp 0.8V l s m bo c rng ng

nhn khng th tn ti lu trng thi ng ra mc 1. in tr 5k ng vo hon

81

ton m bo c rng ng nhn vi ng vo tng ng s ch c duy nht mt

ng ra mc 1.

Ng vo nhn ch sai lch xp x 0.5V. iu ny lm cho ng ra c

chuyn trng thi nhanh gn hn, thm ch vi tn hiu tng chm hoc gim theo

thi gian th lng tn hiu nhiu cng va phi hn.

CHNG 3: S THIT K V LU GII THUT

3.1 S THIT K.

3.1.1 S khi.

a. MODULE PSTN-RS232:

b. MODULE TRM:

82

3.1.2 S nguyn l.

a. Khi ngun.

83

Dng IC n p 7805 v 7812, c nhim v cung cp in p n nh cho

84

mch. Ngoi ra mch cn to in p -12V nh vo IC555.

Tn s dao ng ca IC555 l: f=1/0.693*C28*(R23+R24).

Khi ng ra chn 3 IC mc cao th t C26 s c np thng qua D16, khi

ng ra chn 3 mc thp th t C26 s x qua D15 v np vo C27. Vy

in p ly ra gia hai u t C27 s l in p m -12V.

b. Khi cm bin chung.

Nhim v ca mch l cm bin khi c chung gi vo.

Bnh thng th t C3 s ngn p DC khng cho vo mch, khi opto

P521 cha dn nn chn ng ra RING s mc cao.

Khi c chung gi vo th t C3 s cho in p i qua, chnh lu 1 chiu

nh cu diode, khi P521 s dn v ng ra RING s mc thp bo cho

VXL bit.

c. Khi chuyn mch, ti gi.

85

C nhim v kt ni line in thoi vi khi thu pht DTMF.

Mch to ti gi nhm to tr khng ging nh 1 thu bao nhc my. Q2 c

nhim v thay th mt thu bao trn lnh vc tr khng. in tr DC ca mt

my in thoi l 300 , in tr xoay chiu ti tn s f = 1 KHz l 700 30%.

Tng tr vo ca mch ny phi ph hp cc thng s trn, t C9 nhm lc

xoay chiu. Tn hiu AC khng nh hng n tr khng DC ca mch.

D10,D11,Q2,R6 to thnh ngun dng n nh I=0.6/22=27mA.

d. Khi thu, pht DTMF.

86

T C10 ngn DC ch cho tn hiu m tn i qua, tn hiu m tn ny c

ti qua bin p sut m. Hai diode D12,D13 chng qu p.

Tn hiu vo c khuch i qua U5A. H s khuch i Av= -R4/R13= -

10.

Tn hiu ra c khuch i qua U5B. H s khuch i Av= -R11/R20= -

10.

T C11,C12,C5 l cc t lin lc.

R14 chng in p sai bit R14=R13//R4.

e. Khi x l trung tm.

88

f. Khi giao tip RS232.

g. Khi o nhit .

89

c nhit nh IC LM35 ,ng ra IC LM35 thay i 10mV/oC. iu

chnh gi tr nhit nh bin tr R39, sau a qua b khuch i vi

h s khuch i l Av=1+R38/R37=11.

h. Khi cm bin ng vo.

90

Khi iu khin.

91

3.2 Lu gii thut.

3.2.1 Module PSTN-RS232.

93

3.2.2 Module trm.

97

CHNG 4: KT LUN V HNG PHT TRIN TI

4.1 KT LUN.Sau thi gian nghin cu v tin hnh thi cng n c hon thnh.

100

Trong qu trnh thi cng v thc hin ti gp rt nhiu vn pht sinh ngoi

mong i. Tuy c gng sa cha tuy nhin vn cn mt vi li nh.

4.2 HNG PHT TRIN TI.Theo ti th ti ny cn c th pht trin hon chnh hn:

M rng thm cc ng vo c trng thi, nhit v cc ng ra. Thm

chc nng chn la c th iu khin t ng ti ch hoc iu khin t phn

mm gim st. C th set cu hnh nh ngng gi nhit cao, thp.. .Phn

mm gim st c th cng lc gim st c nhiu module trm hn.

TI LIU THAM KHO Gio trnh H Thng Vin Thng- Bi Th Cao- Trng i Hc

Cng Nghip Thnh Ph H Ch Minh.

Gio trnh Thit B u Cui Vin Thng- Trn Minh Hng-

101

Trng i Hc Cng Nghip Thnh Ph H Ch Minh.

Cc Website : www.diendandientu.comwww.dientuvietnam.net

www.datasheetcatalog.com

102

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DA - Giam Sat Va Dieu Khien Thiet Bi Qua Duong PSTN - Le Thanh Phu