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Deep Submicron CMOS and theNew Era of Creativity
in Analog Design
John A. McNeillWorcester Polytechnic Institute (WPI),
Worcester, MA [email protected]
McNEILL: CREATIVITY IN DSM CMOS … MAY 3, 2006
2
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … MAY 3, 2006
3
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
4
Career ClassificationCREATIVE USEFUL
GOOD PAY
ENGINEER
PROFESSOR TEACHERNURSE
ARTISTPOET
DOCTORADVERTISING
LAWYERSTOCKBROKER
5
Why be creative?• Need
–Easy problems solved already–Tough problems need creative solution
• Dealing with environment of change–Coping, thriving
• Human nature–Fun!
6
Creativity Resources
7
Creativity Framework
Explorer
Artist
Judge
Warrior
8
Creativity Framework
Explorer
Artist
Judge
Warrior
Seek out new informationSurvey the landscapeGet off the beaten pathPoke around in unrelated areasGather lots of ideasShift your mindsetDon't overlook the obviousLook for unusual patterns
9
Creativity Framework
Explorer
Artist
Judge
Warrior
Create something originalMultiply optionsUse your imaginationAsk what-if questionsPlay with ideasLook for hidden analogiesBreak the rulesLook at things backwardChange contextsPlay the fool
10
Creativity Framework
Explorer
Artist
Judge
Warrior
Evaluate optionsAsk what's wrongWeigh the riskEmbrace failureQuestion assumptionsLook for hidden biasBalance reason and hunchesMake a decision!
11
Creativity Framework
Explorer
Artist
Judge
Warrior
Put decision into practiceCommit to a realistic planGet helpFind your real motivationSee difficulty as challengeAvoid excusesPersist through criticismSell benefits not featuresMake it happenLearn from every outcome
12
Example: Time (Stages of project)
Explorer
Artist
Judge
Warrior
Background Research
Brainstorm Options
Choose Solution
Implement Design
13
Why a Creativity Model?
Education• Standardized-test-numbed students• Paralysis in face of open-ended problem
Designer• Awareness of strengths, weaknesses• Recognize preferences
Not Right or Wrong!• One way of looking at process• Orchard analogy
14
Example: Modes of Thinking
Explorer
Artist
Judge
Warrior
DivergentSoft
Qualitative
ConvergentHard
Quantitative
15
Example: Preferred Problem Solution
Explorer
Artist
Judge
Warrior
Add Complexity
Eliminate Complexity
16
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
17
Good Old Days
• Large strong inversion region• Square law, easy hand analysis
Op 't Eynde and Sansen, "Design and Optimization of CMOS Wideband Amplifiers," CICC 1989
W/L
ID
18
TSMC L=0.25µm process
• Moderate inversion• Graphical / numerical analysis
W[µm]
ID [µA]100
101
102
103
104
10-6 10-5 10-4 10-3 10-2
19
DSM CMOS Thin tox: Gate Leakage
µA GateCurrents!
R. Van Langevelde et. al., "Gate current: Modeling, ∆L extraction and impact on RF performance, IEDM 2001
Tunneling current through thin tox
20
DSM CMOS: MOSFET Current Gain
A.-J. Annema et. al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp. 132-143
⇒ Bipolar-like current gain for longer L
21
DSM CMOS: Gate Leakage
R. Van Langevelde et. al., "Gate current: Modeling, ∆L extraction and impact on RF performance, IEDM 2001
⇒ Long L devices unsuitable
22
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
23
Matching
• Classical: Matching improves with ⇒ Spend area to match⇒ Power penalty to drive COX W L
!
WL
Pelgrom et.al., "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, Oct. 1989, pp. 1433-1440
24
Technology Dependence
• As VDD scales downwith Lmin …
• Some improvement inmatching AVth …
K. Bult, "Analog Design in Deep Sub-Micron CMOS ," ESSCIRC2000, Sept. 2000.
25
Technology Dependence
• Dynamic Rangelimited by matching
K. Bult, "Analog Design in Deep Sub-Micron CMOS ," ESSCIRC2000, Sept. 2000.
26
Speed / Accuracy / Power Tradeoff
• Limited by matching, not noise ⇒ Some improvement with technology
Kinget, " Device mismatch and tradeoffs in the design of analog circuits," JSSC, June, 2005
27
Matching / Gate Leakage Issues
• Spend area:Gate leakage mismatch increases with⇒ Limit to attainable matching
!
WL
A.-J. Annema et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp. 132-143
28
Matching / Gate Leakage Issues
• Break limit: Spend area (same L):⇒ But extra power penalty
A.-J. Annema et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp. 132-143
29
Or: Abandon Matching! Options:Fix with analog complexity: Autozero, …
Fix with digital complexity …
Enz and Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated DoubleSampling, and Chopper Stabilization," Proceedings of the IEEE, November 1996, pp. 1584-1614
or
30
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
31
Self-Calibrating ADC GoalsGeneral: Take advantage of CMOS scaling
• Digital–Relax requirements on analog precision–All calibration / complexity in digital domain
• Background–Calibration continuous in background
• Deterministic–Short time constant for adaptation–No requirements on input signal behavior
Specific Implementation:16b 1MS/s Cyclic ADC in 0.25µm CMOS
J. McNeill, et. al., "'Split-ADC' Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC ," ISSCC2005
32
Cyclic ADC
1) Sample input, compare to threshold → digital decision d
2) Amplify input by factor G3) Subtract d.VREF → residue voltage vRES4) Repeat cycle with vRES as inputResult: sequence of decisions dk
S/H
+
!
DIGITAL
G
dk
+/-VREF COMP
RESIDUE AMPLIFIER
vIN
TIMING
x
vRES
DAC
33
Cyclic ADC
Input-Output Relationship:
Residue amplifier: Residue plot:vRES(O)
vRES(I)
SLOPE = G
d = -1 d = +1
+
! G
dk
+/-VREF COMP
vRES(I) vRES(O)
DAC
REFIRESORESVdvGv !"!= )()(
Multiply input by cyclic gain G, subtract d.VREF
34
Example: 3-Cycle ADC• Follow residues; start …
[ ]
[ ][ ]REF
RES
REFREFINRES
REF
RES
REFINRES
REFINRES
IN
Vd
v
VdVdGvGGv
Vd
v
VdGvGv
VdGvv
v
3
)2(
21)3(
2
)1(
1)2(
1)1(
!!!=
"
!!=
"
!=
"
4444 84444 76
44 844 76
[ ]REFINRESVdGdGdGvGv 3
0
2
1
1
23
)3( ++!=
• Cycle 1 residue:
• Cycle 2:
• Cycle 3:
• Rearrange:
35
1: Cyclic ADC as Negative Feedback Loop
•Residue voltages bounded if G isn't "too big"•Safety margin: Choose G < 2•Bonus: Redundancy
Cyclic amplifier tryingto "blow up" vIN
DAC trying to driveresidue to zero
[ ]REFINRESVdGdGdGvGv 3
0
2
1
1
23
)3( ++!=
36
Redundancy• Key: Multiple valid decision paths to output code
G < 2
d = -1 d = +1
d = -1 d = +1
G = 2
-1 or +1 OK
37
2: Digital Correction• Divide both sides by G3 VREF and rearrange
Output code x(radix G)
REF
RES
REF
IN
V
v
Gd
Gd
Gd
GV
v )3(333221
1111!++=
Quantizationerror
• Digital reconstruction from comparator decisions dk:Use estimated gain G(EST) to calculate output code x :
• Only G needed to digitally correct ADC linearity• Calibration: G(EST) = G to within converter accuracy
3
)(
2
)(
1
)(
)(
31
211
dG
dG
dG
x
ESTESTEST
EST !!
"
#
$$
%
&+
!!
"
#
$$
%
&+
!!
"
#
$$
%
&=
38
Output Code
!
vIN
VREF
=1
Gd1 +
1
G2d2 +
1
G3d3 + L
Digital:• Use estimated gain G(EST) tocalculate output code x :
• Calibration: How todetermine G(EST) = G towithin converter accuracy?
3
)(
2
)(
1
)(
)(
31
211
dG
dG
dG
x
ESTESTEST
EST !!
"
#
$$
%
&+
!!
"
#
$$
%
&+
!!
"
#
$$
%
&=
Analog:• G = 2 to within
converteraccuracy
• Calibration:trim, match
39
Previous Calibration Techniques
• No previous technique has all desired features1. Galton, "Digital cancellation of D/A converter noise in pipelined ADCs," TCAS-II, March 20002. Murmann ..., "A 12b 75MS/s Pipelined ADC using open-loop residue amplification," ISSCC20033. Liu .., "A 15b 20MS/s CMOS Pipelined ADC with Digital Background Calibration," ISSCC20044. Nair ..., "A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipelined A/D Converter," ISSCC20045. Ryu ..., "A 14b-Linear Capacitor Self-Trimming Pipelined ADC," ISSCC20046. Erdogan ..., "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90-dB THD," ISSC19997. Chiu ..., "Least mean square adaptive digital background calibration of pipelined ADCs," TCAS-I, Jan. 20048. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," JSSC, Apr. 19949. Karanicolas … , "A 15-b 1-MS/s digitally self-calibrated pipeline ADC," JSSC, Dec. 1993
[1]
Deterministic?
(All) Digital?
Background?
[2] [3] [4] [5] [6] [7] [8] [9]
40
Previous Digital Background Calibration
N
CONVERSIONSREQUIRED FORCALIBRATION
12 14 16
BITSRESOLUTION
104
105
106
107
108
109
22N
[1] Galton2000[2] Murmann2003[3] Liu2004[4] Nair2004[5] Ryu2004
21
4 3
5
41
Statistical Techniques ProblemHow long to calibrate with 22N samples?
msMsps
20075
2122
!"
hourMsps
11
2162
!"
12 bits, 75 MS/s [2]
⇒ Deterministic approach needed
16 bits, 1 MS/s
The problem: How to do a …– deterministic calibration procedure– in background– without a known input?
42
Split ADC Architecture
• Average of A, B results is ADC output code• Calibration signal developed from difference
ADC "A"
!
xA
!
vIN
!
xB
ERRORESTIMATION
+
+
+
-
!
x =xA + xB
2
!
"x = xB # xA
ADC OUTPUT CODE
DIFFERENCE
ADC "B"
43
Intuitive View of Split ADC
• Different paths to (ideally) same answer• Estimate errors from "disagreements"• Only way for A, B to always agree
is for both to be correctly calibrated
ADC "A"
!
xA
!
vIN
!
xB
ERRORESTIMATION
+
+
+-
!
x
!
"x = xB # xA
ADC "B"
!
x
!
t
RESIDUEMODES
44
Robert Frost: “New Hampshire”
“... a figure of the waythe strong of mindand strong of armshould fit together,
One thick where one is thinand vice versa. ”
V T
N H
45
Robert Frost: “New Hampshire”
“... a figure of the waythe strong of mindand strong of armshould fit together,
One thick where one is thinand vice versa. ”
V T
N H
• Key idea: two “partners”trying to do the same thing
in different ways
46
Same Area, Noise, Speed, Power
• Negligible impact on analog complexity
C gm
!
" x = nkT
C
!
fT = bgm
C
!
P = p " gm
A
ANALOG DIGITAL
!
C
2
!
gm2
B
!
C
2
!
gm2!
xA
!
xB!
vIN
!
x
ANALOG DIGITAL
!
vINSPLIT
Speed
Power
Noise
!
1
2n
kT
C 2
"
# $
%
& '
2
+1
2n
kT
C 2
"
# $
%
& '
2
=
!
bgm 2
C 2=
!
p "gm
2+ p "
gm
2=
!
xA + xB
2
!
x
!
nkT
C
!
bgm
C
"
# $
%
& '
!
p " gm
47
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
48
Evaluation Block Diagram
• Test chip mostly analog• Digital on FPGA (code "synthesis-ready" for product)
TEST CHIP
CYCLIC
ANALOG
CYCLIC
DIGITAL INPUT
SIGNAL
COND
DATA
FORMATTING
DSP
INTERFACE
OTHER FPGA
FUNCTIONS
CYCLIC
TIMING
CNVST EXT
TIMING
"PRODUCT"
FPGA
EVALUATION BOARD REF
TO
RAM /
DSP
VIN
49
ADC Block Diagram
“A” L.U.T.
!
dkA
!
vIN
!
1
ˆ G A
"
# $
%
& '
k
!
k1
G
"
# $
%
& ' k
!
xA
!
SDKA
ERROREST.
!
"x
!
ˆ " A
!
µ
!
ˆ G A
!
+
!
"
!
x
Σ
Σ
Σ
!
ˆ " B
!
µ
!
SDKB
!
xB
Σ
Σ
Σ!
ˆ G B
!
1
ˆ G B
"
# $
%
& '
k
!
dkB
!
+
!
+
OFF-CHIP DIGITAL PROCESSOR (FPGA)
PATH A
PATH B
S/H
!
GA
COMPS!
+
!
"
COMPS
S/H
!
GB
DAC
!
+
!
"
CYCLIC RESIDUEAMPLIFIERS
“B” L.U.T.
ERRORCOEFF
L.U.T.
DAC
50
ADC Digital Correction
“A” L.U.T.
!
dkA
!
vIN
!
1
ˆ G A
"
# $
%
& '
k
!
k1
G
"
# $
%
& ' k
!
xA
!
SDKA
ERROREST.
!
"x
!
ˆ " A
!
µ
!
ˆ G A
!
+
!
"
!
x
Σ
Σ
Σ
!
ˆ " B
!
µ
!
SDKB
!
xB
Σ
Σ
Σ!
ˆ G B
!
1
ˆ G B
"
# $
%
& '
k
!
dkB
!
+
!
+
OFF-CHIP DIGITAL PROCESSOR (FPGA)
PATH A
PATH B
S/H
!
GA
COMPS!
+
!
"
COMPS
S/H
!
GB
DAC
!
+
!
"
CYCLIC RESIDUEAMPLIFIERS
“B” L.U.T.
ERRORCOEFF
L.U.T.
DAC
51
ADC Digital Correction
• Decision weight L.U.T.–Periodically recalculated in background–Separate L.U.T.s for A, B output codes
ADC Digital Correction
!
dkA
!
1
ˆ G A
"
# $
%
& '
k
!
xAΣ
COMPARATORDECISIONS[ -1, 0 , +1 ] DECISION WEIGHT
L.U.T.
ACCUMULATEOUTPUT CODE
52
Error Estimation
“A” L.U.T.
!
dkA
!
vIN
!
1
ˆ G A
"
# $
%
& '
k
!
k1
G
"
# $
%
& ' k
!
xA
!
SDKA
ERROREST.
!
"x
!
ˆ " A
!
µ
!
ˆ G A
!
+
!
"
!
x
Σ
Σ
Σ
!
ˆ " B
!
µ
!
SDKB
!
xB
Σ
Σ
Σ!
ˆ G B
!
1
ˆ G B
"
# $
%
& '
k
!
dkB
!
+
!
+
OFF-CHIP DIGITAL PROCESSOR (FPGA)
PATH A
PATH B
S/H
!
GA
COMPS!
+
!
"
COMPS
S/H
!
GB
DAC
!
+
!
"
CYCLIC RESIDUEAMPLIFIERS
“B” L.U.T.
ERRORCOEFF
L.U.T.
DAC
53
Error Estimation
[ ][ ]
BBB
AAA
SDKxx
SDKxx
!
!
+=
+=[ ] [ ]
AABBSDKSDKx !! "=#
DifferenceA, B Outputs
IDEAL ERROR
• Ideal x cancelled from estimation signal path• No need for long decorrelation times
–Deterministic: solve for εA, εB froma few Δ x observations
• SDK error coefficients can be determinedfrom comparator decisions
54
Error Estimation
⇒ Need different dkA, dkB for “visibility” to errors!
dkA
!
k1
G
"
# $
%
& ' k !
SDKAΣ
ERRORCOEFF
L.U.T.
[ ] [ ]AABB
SDKSDKx !! "=#Difference:εA, εB
Fractional errors inGA, GB estimates
SDKA, SDKBError
coefficients
55
Multiple Residue Mode Amplifier
“A” L.U.T.
!
dkA
!
vIN
!
1
ˆ G A
"
# $
%
& '
k
!
k1
G
"
# $
%
& ' k
!
xA
!
SDKA
ERROREST.
!
"x
!
ˆ " A
!
µ
!
ˆ G A
!
+
!
"
!
x
Σ
Σ
Σ
!
ˆ " B
!
µ
!
SDKB
!
xB
Σ
Σ
Σ!
ˆ G B
!
1
ˆ G B
"
# $
%
& '
k
!
dkB
!
+
!
+
OFF-CHIP DIGITAL PROCESSOR (FPGA)
PATH A
PATH B
S/H
!
GA
COMPS!
+
!
"
COMPS
S/H
!
GB
DAC
!
+
!
"
CYCLIC RESIDUEAMPLIFIERS
“B” L.U.T.
ERRORCOEFF
L.U.T.
DAC
56
Multiple Residue Mode Amplifier
• 2b PATH sets residue mode entirely in digital domain
!
d
PATH
S/H
!
G
SEL
!
+
!
"
!
+VTH
!
0
!
"VTH
!
+VREF
!
0
!
"VREF
00 “CYCLIC”
DAC
-1 +1
01 “HIGH” 10 “LOW” 11 “WIDE”
!
vIN
CYCLEDECISION-1 / 0 / +1
-1 +10 -1 +10 -1 +10
PATH:
DECISION d:
57
S/H, 1.5b DAC, G=1.92 Cyclic Amplifier
• 2b PATH sets residue mode entirely in digital domain
!
d
PATH
S/H
!
G
SEL
!
+
!
"
!
+VTH
!
0
!
"VTH
!
+VREF
!
0
!
"VREF
00 “CYCLIC”
DAC
-1 +1
01 “HIGH” 10 “LOW” 11 “WIDE”
!
vIN
CYCLEDECISION-1 / 0 / +1
-1 +10 -1 +10 -1 +10
PATH:
DECISION d:
58
INL Shapes Vary by Residue Mode
[ ] [ ]AABB
SDKSDKx !! "=#
INL shape same as SDKA, SDKB error coefficients
59
Cyclic Amplifier: 3-Capacitor?
DACcap
Signal cap
Feedback cap
• Advantages– Easier to do signal-independent reference current– Decouple reference, cyclic gain paths (CM!)
• Disadvantages– Extra capacitor area– Extra noise gain (killer!)– Output only valid on one
phase (1/2 cycle)• Less time for comparator
P. Ferguson, “Practical Aspects of Delta-Sigma Data Converter Design,” MEAD Microelectronics
60
Cyclic Amplifier: 2-Capacitor
• Advantages– Less cap area– Lower noise gain– Output valid
both phases• Easier on
comparator
• Disadvantages– Signal-dependent reference current– Reference, cyclic gain paths constrained (CM!)
VREFM VREFP VCM
SDBVOUT
SDBP SDBZ SDBM SDTVCM
SDTA
SCF
CD
CF
VOUT
A
DT
VIN
VCM
DB
SFBVIN
SFBVOUT
STPA
VCM
SFBVIN
61
Cyclic Amplifier: 2-Capacitor• 2-Cap chosen:
–Lower total capacitancefor a given noise performance
• Different feedback β in DAC, sample modes–Changes effect of amplifier noise
VCM
CD
CF
"DAC mode" β ~ 1/2
CF
VCM
CD
"Sample mode" β ~ 1
62
S/H, 1.5b DAC, G=1.92 Cyclic Amplifier
• kT/C noise limited ⇒ large C
13.5pF15pF
13.5pF15pF
VINP
VOP
VINM
VOM
VCM
VCM
VCM VCMVOP
VOM
VREFMVREFP
63
Op-Amp
• kT/C noise limited ⇒ large C
13.5pF15pF
13.5pF15pF
VINP
VOP
VINM
VOM
VCM
VCM
VCM VCMVOP
VOM
VREFMVREFP
64
Op-Amp Requirements
Required by kT/C noise limit20-30pFCL80% of total IC power goal (100mW)33mAIDD16 bit settling, 30 ns, 1st half cycle150 MHzfTMaintain over full signal range100 dBAOLTrade SNR, linearity+/- 1.8VVOUTTrade with fT, settling time500 V/usSR
CommentsSpecParam
65
Op-Amp
SNR → ±2Vpp swing → Output not cascoded16b linear → ~100dB AOL → 2-stage⇒ First stage → Gain boosted cascode
VIPVOP
VIMVOM
VB3VB4
VB2
VB1VB5 VB5
Bult & Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," JSSC, Dec 1990Pan et. al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-µm CMOS with over 80-dB SFDR," JSSC, Dec. 2000
66
Op-Amp: Design for 90dB SNR
• Noise contributors:
Sample cap kT/C
Op-amp gm
• Plot SNR, total current
as function of CF, IBIAS
VREFM VREFP VCM
SDBVOUT
SDBP SDBZ SDBM SDTVCM
SDTA
SCF
CD
CF
VOUT
A
DT
VIN
VCM
DB
SFBVIN
SFBVOUT
STPA
VCM
SFBVIN
IBIAS
gm
67
Op-Amp: IBIAS CF Optimization
SNR [dB]
TOTALOP-AMPCURRENT[mA]
SAMPLE CAPACITANCE CF [F]
DIFFPAIRIBIAS[A]
68
Op-Amp: IBIAS CF Optimization
SNR → 90dB → Bias current, sample cap tradeoff
CF limited
gm limited
69
Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
70
Die Photo
ADC "A" ADC "B"
SWITCHEDCAPNETWORK
OP-AMP
COMPARATORS
71
Measured INL
72
Temperature Performance
73
Calibration Convergence
74
Comparison with Previous Work
• Long decorrelation times not necessary
N
CONVERSIONSREQUIRED FORCALIBRATION
12 14 16
BITSRESOLUTION
22N
THISWORK
[1] Galton2000[2] Murmann2003[3] Liu2004[4] Nair2004[5] Ryu2004
21
4 3
5
104
105
106
107
108
109
75
Performance Summary
* Excludes digital on FPGA
1.16mm x 1.38mmDie Area *105mWPower Consumption *+0.66 / –0.47 LSBDNL+2.1 / -4.8 LSBINL89 dBSNR1 MS/sConversion Rate16 bResolution2.5 VSupply Voltage0.25µm 1P4M CMOSTechnology
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"Split ADC" architecture
• Average: Output code• Difference: Drive to zero to correct errors• Deterministic: Rapid self-calibration
– Suitable for high resolution ADCs
• 16b 1MSps Cyclic ADC– Self-calibration in ~ 10,000 conversions
Complexity moved into digital domain
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Overview• Analog / Mixed Signal IC Design
–Role of Creativity• DSM CMOS Effects on Analog Design
–Short L, Thin tox–Matching Issues
• Self-Calibrating ADC–Overview–Design Details–Results
• Conclusion
McNEILL: CREATIVITY IN DSM CMOS … APRIL 28, 2006
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DSM CMOS Conclusions
• Performance challenges–Change in role of analog techniques
• Opportunities–Digital complexity enabled
• Need for designer creativity–Choose best from both worlds
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Acknowledgments• Analog Devices
–Precision Nyquist Converters group–Bob Adams–Bob Brewer–Larry DeVito–Paul Ferguson–Colin Lyden–Katsu Nakamura–Richard Schreier–Larry Singer
• Stanford University–Boris Murmann
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ReferencesSelf-Calibrating ADCs
J. McNeill, M. Coln, and B. Larivee, "'Split-ADC'Architecture for Deterministic Digital BackgroundCalibration of a 16b 1MS/s ADC ," ISSCC2005
B. Murmann and B. Boser, "A 12-bit 75-MS/s PipelinedADC Using Open-Loop Residue Amplification," IEEEJ.Solid-State Circuits, Dec. 2003.
Creativity
R. Von Oech, "A Whack on the Side of the Head" New York: Warner, 1998. ISBN 0446674559
R. Von Oech, "A Kick in the Seat of the Pants"New York: HarperCollins, 1986. ISBN 0060960248
CMOS Design
Op 't Eynde and Sansen, "Design and Optimization ofCMOS Wideband Amplifiers," Proc. CICC, 1989.
R. van Langevelde, A. J. Scholten, R. Duffy, F. N.Cubaynes, M. J. Knitel, and D. B. M. Klaassen, "Gatecurrent: Modeling, ∆L extraction and impact on RFperformance, Proc. IEDM, 2001.
A.-J. Annema, B. Nauta, R. van Langevelde, and H.Tuinhout, Analog Circuits in Ultra-Deep-SubmicronCMOS, IEEE J. Solid-State Circuits, Jan. 2005.
C. Enz and G. Temes, "Circuit Techniques for Reducingthe Effects of Op-Amp Imperfections: Autozeroing,Correlated Double Sampling, and ChopperStabilization," Proceedings of the IEEE, Nov. 1996.
Matching
M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matchingproperties of MOS transistors," IEEE J. Solid-StateCircuits, Oct. 1989.
P. R. Kinget, " Device mismatch and tradeoffs in thedesign of analog circuits," JSSC, June, 2005.
K. Bult, "Analog Design in Deep Sub-Micron CMOS ,"ESSCIRC2000, Sept. 2000.