Sep 11-15, 2006 STD6 @Carmel, CA 1

Deep-submicron FD-SOI for front-end application  

Hirokazu Ikedaikeda.hirokazu@jaxa.jp

Institute of space and astronautical scienceJapan aerospace exploration agency

Sep 11-15, 2006 STD6 @Carmel, CA 2

Abstract

SOI devices are free from parasitic PNPN structure, and, hence, intrinsically immune to single event latch-ups. Moreover SOI devices are located on a very thin silicon layer, the energy deposit by impinging particle is relatively small, and, then, the single event upsets and/or single-event transients are manageable with an appropriate design strategy.

When designing front-end circuits with an FD-SOI, we can take benefits such as small floating-body effect, superior sub-threshold characteristics and small temperature coefficient as well as common nature of SOI devices, i.e. small parasitic capacitance, low junction leakage, decrease in substrate coupling noise, and reduction of silicon area.

In order to confirm these benefits and to identify possible issues concerning front-end circuits with a deep sub-micron FD-SOI, we have submitted a small design to OKI via the multi-chip project service of VDEC, the university of Tokyo. The initial test results and future plan for development are presented in this talk.

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Team organization

Possible application forSuper-B, SLHC, ILC andmaterial science

Y.AraiA, K.HaraB, Y.IkegamiA, H.IshinoC,T.KawasakiD, T.KohrikiA,

E.MartinE, H.MiyakeF, A.MochizukiB, H.TajimaF, O.TajimaA, S.TeradaA,

T.TsuboyamaA, Y.UnnoA, H.UshirodaA, G.VarnerE

KEKA, U.TsukubaB, TITC, Niigata UD,

U. HawaiiE, Osaka UF, SLACF

H.Ikeda, H.Hayakawa, K.Hirose, Y.Kasaba,

T.Takahashi, T.Takashima, H.Tomita

JAXA

Possible applicationfor solar system exploration,and deep-space observation

JEM/ISS

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Contents for talk

1. Introduction2. TEG fabrication3. Circuit and operation4. Towards radiation-hardness assurance5. Conclusion

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1. Introduction

・ Full dielectric isolation: Latch-up free, Small area・ Low junction capacitance: High speed, Low power・ Low junction leakage: High Temp. application･ Decrease in substrate coupling: A/D mixed application・ High soft error immunity: Rad-hard application

Entering into late 1990's, the trend curve of a bulk CMOSprocess tends to go behind the Moore's law, and, hence, the manufactures are eager to find a way to recover development speed.

There exists a general trend :Post-scaling technology…..SOI/SOS, Strained-Si,3D-tr, Cu, High-k, Low-k…..

SOI CMOS is then revisited toreveal its performance over an existing bulk CMOS; the SOI CMOS eventually shows up as a successor of the CMOS process inheriting well-matured fabrication technologies for a bulk CMOS.

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FD-SOI

DepletionLayer

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2. TEG fabrication

4,5,6 inch wafer,CMOS/Bipolar 6,8 inch wafer

Mass production

Research

VDEC route(0.15 um) VLSI design & education center,

The university of Tokyo

JAXA/MHI route(0.2 um)

c/o K.Hirose

KEK route(0.15 um W/ pixel implant)

c/o Y.Arai

ISAS, JAXA

0.15-um FD-SOIProcessed by Oki Elec. Ind. Co., LtdSOI: 50 nm, BOX: 200 nm, 6”wafer(UNIBONDTM,SOITEC)Vdd: 1.0 V/1.8 V, Vth: 0.18/-0.25 for LVTMetal: 5-layers, Capacitor: MIMOption: Thick metal

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2.4 mm

Charge amplifier

TOT amplifier-1

TOT amplifier-2

Trans-impedance amplifier

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3. Circuit and operation

nMOS (LVT) inputId=100-500 uAW/L=5/0.5 M=360Cox*W*L=12.5 pFgm= 11.5 mS

Gain-boost

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Short decayLong decay

The leakage current of the FBcircuit determines the slowest decay.

Chain1

Sep 11-15, 2006 STD6 @Carmel, CA 11Adjustment to balanceLeakage current

nchl,pchlnchv,pchv

200 mV

500 mV

Good dynamic range

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4 fC40 fC

Chain2

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4 fC

Small overshoot40 fC

Chain3

Small overshoot as expected

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-8 fC

8 fC

Chain4

D/A interference is very severe.

2 fC

1 V CMOS

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Total dose:radiation hard? Not necessarily the case for gate edge and/or BOX.H-gate (Enclosed gate?): ready to useVoltage on handle wafer: control of Vth

4. Towards radiation-hardness assurance

Single event: radiation hard? Not necessarily the case.

Appropriate design-by-hardningis required.

Future of SOI-CMOS

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As a first step…..DUT

DUT Y.Ikegami et al.

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5. Conclusion

1) FD-SOI analog front-end circuits are examined under a joint effort of JAXA , KEK and related institutes as a part of the SOI-pixel detector development and/or future solar system/deep-space exploration.2) The FD-SOI TEG circuits are proved to work even with very low Vdd voltage thanks to stable low threshold transistors.3) Minor issues are identified, and confirmed to be fixed in the second RUN. The third RUN is scheduled in Dec, where we are going to proliferate the TEG design for a tracking application as well as spectropscopic use.4) Radiation hardness is still an issue to be examined in term of total dose and SEU/SET.5) Road-map for the SOI technology is on the way of the post-scaling technology, which conforms with application in a harsh environment in space and high energy physics.

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Large dynamic range

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18

Pulse width is sensitive to the leakage currentdue to the ESD pad!

The leakage current is adjusted by moving the VSS voltage for the ESD pad.

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