DELAY TESTagrawvd/BOOK/book12.pdf · 12.1 Delay Test Problem 419 0 0 5 1 2 3 1 2 2 1 3 4 6 P1 J K Q P2 P3 EG A B C H Figure 12.2: An example of transition propagation through paths

Chapter 12

DELAY TEST

\ . . . a new type of fault, called a delay fault, is introduced, anda model developed so that a test to detect this class of fault can begenerated via conventional test generation techniques. . . . so thattest generation is more of a science rather than a hit or miss process,and so that the correctness of results need not always be veri�ed viasimulation or physical fault injection." | Melvin Breuer, in a 1974paper [91].

A stuck-at-0 fault on a signal means that the signal can be set to 0, but thencannot be changed to 1. Alternatively, this situation can be described by sayingthat the signal will take an \in�nite" amount of time to rise from 0 to 1. Thus, astuck-at fault is an in�nite delay fault and, indeed, a circuit that passes stuck-atfault tests is not likely to have any in�nite delay fault. For digital systems thatwork at any appreciable speed, this is not su�cient. The operation of such systemsis usually synchronized by clock signals and it is necessary that all combinationallogic elements attain steady state within some speci�ed clock period. Applicationof stuck-at fault tests at higher speed can uncover some delay defects. However,at least four recent studies [108, 226, 438, 503] show that even that may not besu�cient and tests speci�cally generated to detect delay defects may be necessary.

This chapter is introductory and the reader may consult recent books on delaytesting [371, 608] and timing analysis [452].

12.1 Delay Test Problem

Figure 12.1 shows a schematic of a digital system. Some inputs and outputs canbe state variables connected to ip- ops (FF) (not shown) and others are primaryinputs (PI) and primary outputs (PO.) All input changes are synchronized with aclock signal and all outputs are expected to attain their �nal steady state valueswithin one clock period after the inputs change. Thus, for a correct operationthe delay of the combinational logic should not exceed the clock period. Typical

418 Chapter 12. DELAY TEST

Out

puts

Inpu

ts

Transient region

Time

logic

Combinational

Clock period

Figure 12.1: Delay fault problem de�ned.

outputs of logic circuits contain transients as shown in Figure 12.1. We make severalobservations:

� In order to examine the timing operation of a circuit we should examine signaltransitions. The input signal in Figure 12.1 consists of two vectors: 010! 100.Delay tests consist of vector-pairs.

� All input transitions occur at the same time in Figure 12.1. Thus, the durationof the transient region at the input is zero. This, of course, is an idealizedillustration though it closely represents the real situation. The transient regionat the output contains multiple transitions that are separated in time. As wewill see in the next example, the position of each output transition dependsupon the delay of some input to output combinational path.

� The right edge of the output transition region (grey shaded area in Figure 12.1)is determined by the last transition, or the delay of the longest combinationalpath activated by the current input vector-pair. Considering all possible inputvector-pairs, \the longest delay combinational path" of the circuit is known asthe critical path. There can be more critical paths than one if several pathsmeet the maximum delay criterion. The delay of critical paths determines thesmallest clock period at which the circuit can function correctly.

� For a manufactured circuit to function correctly, the output transition regionfor any input vector-pair must not expand beyond the clock period. Otherwise,the circuit is said to have a delay fault. A delay fault means that the delay ofone or more paths (not necessarily the critical path) exceeds the clock period.

Example 12.1 Propagation of transitions. Consider the circuit in Figure 12.2.Gates are modeled with equal rise and fall lumped delays that are integer multiplesof some small time unit (nanosecond or picosecond.) We will also assume that theseare purely transport delays and that the gates have negligible inertial delays. Thus,any waveforms are simply translated in time without distortion. More detailed delaymodels are discussed in Subsection 5.3.5. However, this simple model will su�ce forthe present discussion. Signal waveforms at various nodes are sketched in the �gure,with the time of each transition shown under it. The time of input transitions is 0,

12.1 Delay Test Problem 419

0

0

5

1

32

12

2

31

64

P1

JK

Q

P2

P3

E G

A

B

C

H

Figure 12.2: An example of transition propagation through paths.

making them the reference for all other transitions. The output has three transitions,brought via three paths. The reader can examine the progress of each transitionby following the dashed lines with arrows. This circuit has �ve paths, which canpotentially produce that many transitions at the output. The actual number dependson speci�c delays and the input stimuli.

Let us examine the three activated paths: Path P1: A�H �K, Path P2: B �E�Q�H �K, and Path P3: B �E�G� J �K. In the operation of this circuit,the input and output signals (irrespective of whether or not they are latched) aresynchronized with a clock of period T. Given that these delays have been derivedfrom the analysis of the design data (device parameters, routing capacitances, etc.),the critical path has a delay of 6 units in the fault-free circuit. Path P3 is one ofthe two critical paths. Suppose we choose T = 7. Any path will be faulty if its delayexceeds 7 units. Consider two cases:

1. Single faulty path: We examine the output at 7 units of time. As long as thedelay of path P3 is 6 units or less, the output will have risen to logic 1 valueirrespective of the delay of path P1 or P2. Thus, the delay faults of P1 and P2will not be detected by this input vector pair. If the delay of path P3 exceeds 7units, say, due to some manufacturing defect, then the last edge in the outputwill be shifted to the right and we will observe a 0 instead of 1. Thus, the delayfault of path P3 is detectable by this vector-pair.

2. Multiple faulty paths: Suppose all three paths have more than 7 units of delay.Then the entire waveform at the output will be translated to the right by morethan 7 units and we will observe a failure. If P1 is not faulty but P2 and P3 arefaulty, then the output will rise at 2 units and will remain high beyond 7 units.It may fall depending on the relative delays of P2 and P3. However, observingat 7 units, we will see no failure. In this case the fault of P2 interferes with thedetection of the fault of P3. As we shall see later, this is because the presentvector-pair is a \non-robust" test for the delay fault of P3.

We have considered only three paths that are activated by the given input vector-pair.Other paths, when activated, can be analyzed similarly.


12.2 Path-Delay Test

The path-delay fault is an important fault model used in delay testing. Thefollowing de�nitions characterize it.

De�nition 12.1 Path-delay fault. The delay defect in the circuit is assumed tocause the cumulative delay of a combinational path to exceed some speci�ed duration.The combinational path begins at a primary input or a clocked ip- op, contains aconnected chain of gates, and ends at a primary output or a clocked ip- op. Thespeci�ed time duration can be the duration of the clock period (or phase), or thevector period. The propagation delay is the time that a signal event (transition)takes to traverse the path. Both switching delays of devices and transport delays ofinterconnects on the path contribute to the propagation delay.

For each combinational path in a circuit, there are two path-delay faults cor-responding to rising and falling transitions, respectively. These faults for a pathconsisting of gates a, b, and c are speci�ed as " a � b � c and # a � b � c, wherethe arrow gives the direction of the transition at the input of the path. The totalnumber of path-delay faults is twice the number of physical paths in the circuit. Ingeneral, any combination of paths can be faulty. However, similar to the \singlestuck-at" fault model (see Section 4.5) we consider delay faults of single paths. Inpractice, though, multiple paths can be faulty.

De�nition 12.2 Non-robust path-delay test. A test that guarantees to detect apath-delay fault, when no other path-delay fault is present, is called a non-robusttest for that path. A path-delay fault for which a non-robust test exists is called a\singly-testable path-delay fault [245]."

A non-robust path delay test applies a transition (two-vectors) at the input ofthe path and measures the output value after a speci�ed interval (clock period.)For the test to be an e�ective measure of the path delay, the \expected or correct"output value must be uniquely controlled by the transition propagating through thepath. Consider the path-delay fault # P3 shown with bold lines in Figure 12.2.Signals B, E, G, J , and K are called the on-path signals. Signals that are not inthe path P3 but feed the gates on the path are called o�-path signals. Thus, C andH are o�-path signals for P3. A non-robust test consists of a vector-pair V 1; V 2,such that:

1. The change V 1! V 2 initiates the appropriate transition at the beginning ofthe path under test. For example, in Figure 12.2 the vector-pair (V 1; V 2) =(010; 100) produces a falling transition at B to test the fault # P3.

2. All o�-path input signals for the path under test assume non-controlling values(0 when feeding into OR/NOR gate, and 1, into AND/NAND gate) in thesteady-state following the application of the second vector V 2. This conditionis known as static sensitization of a path. We may point out that the staticsensitization of paths should not be confused with the \static timing analysis,"

12.2 Path-Delay Test 421

steady-state

Correct output

TimeT(CK)

Non-controlling

Observed output

Off-path input H

On-path input J

Output signal K

2

d(P2) - d(K)

d(P3) > T(CK)V1

d(x) = delay of path x or gate x

d(P1) - d(K)

V applied

steady-state

d(P1)

d(P2)

d(P3) - d(K)

Figure 12.3: Non-robust path-delay test output for # P3 being tested in Figure 12.2.

which simply refers to a topological analysis of physical paths without theapplication of any signals.

In Figure 12.2, transitions are applied to faults " P1 and # P3 but static sensitizationis achieved only for the latter. Therefore, only the fault # P3 is non-robustly tested.

The fact that the two conditions listed above indeed produce a non-robust testcan be easily veri�ed. First, by the de�nition of non-robust test, only a single pathis faulty. Hence, all transitions arriving through other paths ending at the samedestination must arrive prior to completion of the clock period (shown as the greyregion in Figure 12.3.) This implies that by the end of the clock period, all signalsother than the on-path signals of the path under test must be in their steady-state.Since the o�-path steady-state signals sensitize the entire path under test, the pathdestination signal is uniquely controlled by the transition propagating through thepath. If the path delay exceeds the clock period, then the observed value at the pathdestination at the end of the clock period will di�er from the steady-state outputdue to V 2, which is the correct expected value. This is illustrated in Figure 12.3.

Example 12.2 Non-robust test. Figure 12.4 shows a non-robust delay test for thepath delay fault " A�B�C. The AND gate has rise and fall delays of one unit each,shown as 1/1. The rise and fall delays of the inverter are 2 units. A vector-pair(0; 1) is derived to satisfy the conditions of a non-robust test and is derived withoutthe consideration of the speci�c gate delays. The �rst three waveforms are sketchedfor the fault-free circuit. The last two waveforms show the signals for a delay faultcaused by the inverter delay increasing to 4 units. We notice that the test doesnot produce a steady-state signal change in the output, which is 0 for all inputs.This logically trivial circuit is a pulse generator whose pulse width is controlled bythe inverter delay. If the position and width of the pulse have timing requirementswith respect to the clock period, then the delay fault in the inverter path may beimportant and such a test would be useful. Since this is a non-robust test, it is notguaranteed to work when other paths are faulty. For example, if an additional delayfault " A� C is present (either due to increased routing delay or due to increase inthe delay of the AND gate), then the signal C may remain as constant 0. In somedelay distributions the output pulse will be produced but will be pushed to the right


CNo fault:

Fault:

1/1BA

Non-robust testA

C

B

B

C

d(B)

210Time

Correct output = 0

Faulty output = 1

3

d(B)

T(CK)= 4

= 2

= 4

54

2/2

Figure 12.4: An example of a non-robust test.

and out of the clock period (grey region.) In either case, the correct logic value 0will be observed at the end of the clock period. The presence of the fault " A � C,therefore, \invalidates" the non-robust test for fault " A �B � C. We also observethat a non-robust test is not possible for the fault " A�C, because when we apply therising transition at A, the o�-path input B of the AND gate assumes the controllingvalue 0.

The notion of robust delay test, though implicit in Smith's 1985 paper [611], wasformally de�ned by Lin and Reddy [397]. The following is an important concept indelay testing:

De�nition 12.3 Robust path-delay test. A robust path-delay test guarantees toproduce an incorrect value at the destination if the delay of the path under test exceedsa speci�ed time interval (or clock period), irrespective of the delay distribution inthe circuit.

Figure 12.5 shows a hypothetical (though typical) output waveform produced bycombinational logic when a vector-pair (V 1; V 2) is applied at the input. If this logicis a part of a clocked sequential circuit, the output value at the end of the clock periodT (CK) is of interest. The initial value (0) is the steady-state output of V 1 and the�nal value is the steady-state output of V 2. Each transition produced by the vector-pair can potentially propagate through some path and produce a transition at theoutput at a time determined by the delay of that path. The transitions propagatingthrough paths whose delays are smaller than T (CK) are shown as \fast transitions"and those propagating through paths with delays greater than T (CK) are shown as\slow transitions." If the delay of a path increases, the corresponding transition atthe output will move to the right. If the delay reduces, the transition will move tothe left. When two neighboring transitions form a pulse, the pulse width equals thedi�erence between the delays of the corresponding paths. If the pulse width is zeroor negative (i.e., falling edge arrives earlier for a positive pulse), both transitionswill disappear. In other words, the position of an output event is determined by thedelay of the path the event travels through, while the existence of the event at theoutput depends upon the delays of other paths. A robust test that measures thedelay of a path should produce an event at the output with following properties:


transitionsSlow

Clock period, T(CK)

= 0

Final value = 1

Time

transitions

Initial value

Fast

Figure 12.5: Output events produced by combinational logic.

U1

U1

S1

S1 S0

S0

F0

R1/U1

F0/U0

F0

R1

R1/U1

F0/U0

R1

U0

U0V1 V2

V1 V2

V1 V2

V1 V2

V1 V2

V1 V2

Figure 12.6: Robust path delay sensitization for rising and falling transitions.

1. It should be a \real event" de�ned as a transition from the initial value to the�nal value. This is because a real event can exist without the help of any otherevent. For a falling transition in Figure 12.5, to appear it must be preceded byanother event (a rising transition.) Notice that the falling event at the outputin Figure 12.3 is not a real event.

2. It should be a \controlling event." A controlling event permits no other eventsto appear prior to its own appearance. Thus, the output will remain at theinitial value until the controlling event occurs at the output.

Having set the requirements for the event the test must produce at the output, weconstruct the test by recursively moving backward along the path under test. Theon-path input of the gate contains the source of the output transition. It is a realtransition of the same or the opposite type depending on whether or not the gate hasan inversion. If the on-path event is a transition from the controlling value to non-controlling value, then it will prevent any output events prior to its own occurrence.So, there is no speci�c requirement for o�-path inputs in V 1. To ascertain that theoutput has a real event, all o�-path inputs of the gate should have non-controllingvalue in V 2. When the on-path event is a transition from non-controlling valueto controlling value, all o�-path inputs must have a steady non-controlling value inboth V 1 and V 2. This is because any transition (even a glitch) can be propagated tothe output from the o�-path input. These conditions are illustrated in Figure 12.6for AND and OR gates. The reader can easily work them out for other types ofgates. The grey regions in waveforms are the times when \don't care" values ortransients (glitches) can occur. We notice that glitches are permitted in on-pathsignals (shown in bold lines.) This is because these are fault detection tests and not\diagnostic tests." That means the output will not change from the initial value(due to V 1) during an interval that equals the delay of the path under test. However,an incorrect output at the end of the clock period can also be due to some delayed


U1 XX

XX

XXXXXX

U0

U1

U0

S0

U0

S0S0

U0

S0

NOTORAND

U1 U1

S0 U0

U0

S0

U0S0

S0

S0

U1S1

S1

S1

U1S1

U1Input

S1S1

U0

U0

S1

XX

U1S1

XXU1S1U0

S0

XX

U1

S1

U0

U0 XX

XX

U1

S1

U0

S0

XX

XXU1S1U0S0

XX

S0 XX

Input 1

Inpu

t 2

XX

U1

S1

U1

S0

XXU1S1U0S0

S1 S1

U0

S0

Input 1In

put 2

U1

Figure 12.7: Five-valued algebra for path-delay tests.

transition or glitch propagating through o�-path inputs.

The signal values shown in Figure 12.6 are due to Lin and Reddy [397]. S0 andS1 are steady (without glitch) 0 and 1 values for both vectors V 1 and V 2. U0 andU1 specify the �nal value as 0 and 1, respectively, and leave the initial value as don'tcare or X. F0 and R1 are falling and rising transitions on the on-path signals. For ano�-path signal, F0 and R1 are treated same as U0 and U1, respectively. In addition,XX is used to denote both vectors in the don't care state. The value set (S0, U0,S1, U1, XX) is a �ve-valued algebra. With a careful examination, the reader caneasily obtain the the truth-tables for AND, OR, NOT, NAND and NOR gates, the�rst three of which are shown in Figure 12.7 [397].

Multi-valued algebras have useful applications in delay testing. Bose et al. [84]give a theoretical treatment leading to optimal algebras for speci�c cases of testgeneration and fault simulation in combinational and sequential circuits.

12.2.1 Test Generation for Combinational Circuits

Generation of a test for a path-delay fault requires placing the appropriate tran-sition at the origin of the path and justifying the required o�-path inputs of all gateson the path. This is easily accomplished using the �ve-valued algebra.

Example 12.3 Robust test generation. Consider the path-delay fault # P3 in Fig-ure 12.2. We proceed as follows:

1. Place a transition at the path origin, B = F0.

2. Propagate value F0 to line E, from Figure 12.6, C = U0 ) E = F0.

3. G = F0 ) J = R1.

4. F0 is interpreted as U0 for o�-path logic, Q = U0.

5. Propagate value R1 from J to K, using Figure 12.6 set H = S0 ) K = R1.

6. Justify H = S0, from Figure 12.7 set A = S0.

7. Test is A = S0, B = F0, C = U0; or V1 = 01X, V2 = 000.


We should remember that the value S0 implies that input A should hold its valuesteady for two vectors. We observe that this test is di�erent from the one consideredin Example 12.1. This test is robust and the reader can verify that it will not beinvalidated irrespective of the delay of P2.

The procedure of the above example can be implemented in many ways. Thepath can be sensitized starting at the output, or all o�-path signals can be setat once and then justi�ed. We chose to sensitize the path from input because ifsensitization becomes impossible at some gate, then we can immediately concludethat no robust test is possible. This simple example has only limited choices. Withincreasing number of inputs of a gate, justi�cation choices also increase. In general,when the circuit has reconvergent fanouts, the test generation procedure frequentlyhas to use backtracks in the same way as described in Chapter 7.

For some paths, robust tests are not possible and we must generate non-robusttests. As discussed before, non-robust tests only require static sensitization. Thatmeans all signals except the origin of the path under test can have arbitrary valuesin the �rst vector (V 1). This condition is easily incorporated in the multi-valuedalgebra by simple substitutions, S0 U0 and S1 U1.

Example 12.4 Non-robust test generation. Let us try to generate a robust test forpath-delay fault " P2 in Figure 12.2. We proceed as follows:

1. Place a transition at path origin, B = R1.

2. Propagate R1 to E, from Figure 12.6 set C = S0.

3. R1 is interpreted as U1 for o�-path logic, G = U1 ) J = U0.

4. Q = R1, Propagate R1 to H, from Figure 12.6 set A = U1.

5. H = R1, Propagate R1 to K, from Figure 12.6, must set J = S0 ) con ictsince J = U0 in step 3.

6. Since no step has any alternatives, a robust test is not possible.

For a non-robust test we change S0 and S1 to U0 and U1, respectively (static sen-sitization.) Now the Step 5 requirement becomes J = U0, which is consistent withStep 3. The non-robust test is A = U1, B = R1, C = U0 (changed from S0); or V1= X0X, V2 = 110.

An alternative and simpler method for generating non-robust tests is to derivesingle input change (SIC) tests. For a SIC test, the two vectors V 1 and V 2 in thetest di�er in exactly one bit. We �rst �nd V 2 to statically sensitize the entire pathusing any combinational ATPG procedure (see Chapter 7.) V 1 is then obtained byjust changing one bit in V 2 that corresponds to the origin of the path. It can beeasily shown that every non-robustly testable path must have a SIC test [245].

The procedure of Example 12.4 attempts to �nd a non-robust test only when arobust test is impossible. In view of the fact that the reliability of non-robust tests


is questionable (see Example 12.2), there is merit in �nding as many robust tests aspossible. The presence of robust tests for some paths can improve the reliability ofnon-robust tests for other paths. For example, in Figure 12.2 six path-delay faults," P1, # P1, " P3, # P3, " C � E � G � J � K and # C � E � G � J � K, arerobustly testable. Example 12.4 shows that " P2 only has a non-robust test. Byincluding the six robust tests we can ensure that if the circuit passes those, therewill be no delayed signal at o�-path inputs of the path P2. We can conclude thatin the presence of the other four tests, the non-robust test for " P2 is as good as arobust test. Such a test is called a validatable non-robust (VNR) test [371, 539, 632].

Example 12.5 Untestable path delay fault. Consider the path-delay fault # P2 inFigure 12.2. A falling transition (F0) is placed at B and is easily propagated to Hby setting appropriate values on A and C. However, a forward implication sets theo�-path input of the output OR gate to U1 (i.e., controlling value in V 2.) Thispath-delay fault has no test.

A path for which both (rising and falling) path-delay faults (PDFs) are singly(i.e., non-robustly) testable is called a testable path. A path having one singlytestable PDF and one singly untestable PDF is called a partially testable path [244].When no non-robust test exists for both PDFs of a path, that path is called asingly-untestable path. Such a path can be eliminated by circuit transformationsthat preserve the logic function.

An untestable path is (and a partially testable path may be) associated with oneor more redundant single stuck-at faults [415]. The function-preserving transforma-tion such as redundancy removal, as discussed in Chapter 7, eliminates such paths.The fault considered in Example 12.5 is on a partially testable path. We observethat the fault Q stuck-at-1 in this path is redundant. Removal of this fault removesthe AND gate H feeding input A directly to the OR gate K. This eliminates thepath completely.

In general, a partially testable path may not have a redundant stuck-at fault.However, there are procedures for modifying the circuit [244, 352] to expose redun-dant faults that can be removed. The resulting circuit always has fewer paths, agreater percentage of testable paths, and lower overall delay, but can be larger insize.

A combinational circuit may have paths whose delays cannot a�ect the time ofsignal change at the output. These paths are called false paths [244]. The paths ofsingly-untestable PDFs are not always false paths. For example, a singly-untestablePDF may be co-sensitized (sensitized simultaneously) with other singly-untestablePDFs and the timing of the circuit would be a�ected if all co-sensitized paths haveexcess delays. These paths belong to the classes of multiply-testable PDFs [245] andfunctionally sensitizable PDFs [155]. That is the reason why the delays of pathswhose PDFs may be untestable are still taken into account while determining theclock period of the circuit (a point in favor of the static timing analysis.)


C

R

A4A3

A2O1

Q1

A5

P1

P2

N2

N3

N4

O2

4

11

1 1

4

8

A4

A3

N3

A5

1

4

4

8

8

(b) Path graph for combinational logic.

1

Q2

FF1

FF2

(a) A modulo-3 counter circuit.

8

A2 Z

Q2

N2

N4

A1Z C

R

P1

P2

N1

A1N1

Source

O1

Q1

O2 Sink

11

2

2

181

Figure 12.8: An illustration of path counting.

12.2.2 Number of Paths in a Circuit

An often-cited hurdle for path-delay testing is the large number of paths thata combinational circuit can have. Pomeranz and Reddy [526] give an example of acircuit to show that the number of paths can be an exponential function of gates(see Problem 12.10.) The benchmark circuit c6288 is known to have 1:98 � 1020

paths. It is a parallel multiplier with 32 inputs, 32 outputs, and 2,406 gates. Many,though not all, practical circuits have such behavior. Pomeranz and Reddy pointout that path counting algorithms work e�ciently in spite of the exponential numberof paths.

Example 12.6 Path counting. The combinational circuit of a modulo-3 counteris enclosed in a dotted-line box in Figure 12.8(a). To count paths, we constructa directed acyclic graph (DAG) as shown in Figure 12.8(b). Every primary input(PI), pseudo-primary input (PPI), gate, primary output (PO), and pseudo-primaryoutput (PPO) is a vertex in this graph, with the name written alongside. Directededges in this DAG represent signal ow paths. Two extra vertices, source and sink,are added. The source node has 0 indegree and it has directed edges to all PI vertices.All PO vertices have directed edges to the sink vertex, which has a 0 outdegree. Eachvertex is given a label (written inside) that equals the number of paths arriving fromthe source. The source label is initialized to 1 and all others to 0. Vertices in an\active list" are processed in arbitrary order. The processing of a vertex involves twooperations: (1) updating its label to be the sum of labels of fanin vertices, and (2)adding its fanout vertices to the active list. The active list is initialized to contain thesource vertex and the process begins. Thus, all PI labels are changed to 1. Considervertex C whose processing places fanout vertices N1, A3 and A5 in the active list.It is possible that they will be processed before nodes such as N2, N3, and N4, thatare yet to be added to the active list. So, labels of N1, A3, and A5 will change to1. This is the �nal count for N1, but the counts of A3 and A5 will further changeas these vertices will be revisited. The maximum number of times a vertex can bevisited equals its indegree. The procedure ends when the active list becomes empty.The label of sink is then the number of paths in the circuit. In this case it is 18.


Since a vertex can potentially be visited as many time as its indegree, the worst-case complexity of path counting is O(N2) for a DAG with N vertices. This isbecause the maximum indegree of a node is O(N). For practical circuits the gatefanin has some upper bound that does not grow with the number of gates. Therefore,the complexity of path counting for a circuit with N gates is usually O(N).

Graph theorists [743] often consider the path counting algorithm as a folklore andthus explain its absence from books on the subject. Since Pomeranz and Reddy [526]proposed its application to delay testing, several new techniques for PDF coverageevaluation have been developed [246, 292, 344, 514].

Path counting does not help in test generation for PDFs. To contain the so-called \path explosion," several criteria for selecting paths have been proposed. Li etal. [396] give an algorithm that identi�es a set of paths including the longest delaypath through every line. Realizing that some selected paths may be untestable,Park and Mercer [507] generate tests for longest delay \testable" paths throughall lines. Majhi et al. [414] have de�ned such tests as line-delay tests. The upperbound on the number of line-delay tests is twice the number of lines in the circuit.However, as the authors of these papers point out, such tests o�er no guarantee tocover all types of delay defects. Besides, the problem of circuits such as c6288 isstill unsolved. That circuit has a very large number of \longest delay" paths veryfew of which are testable.

Several classi�cation schemes for path delay faults have been proposed [371],each identifying a subset of paths that must be tested to guarantee the coverageof all delay defects. However, often the large size of the target path set and theabsence of robust tests for many paths voids any guarantee.

12.3 Transition Faults

A simpler delay fault model, known as the transition fault, was de�ned in Chap-ter 4. A transition fault on a line makes the signal change on that line slow. The twopossible faults are slow-to-rise and slow-to-fall types. For detecting a slow-to-risefault on a line, we take a test for a stuck-at-0 fault on that line. This test will setthe line to 1 in the fault-free circuit and propagate the state of the line to a primaryoutput. Let us call this vector V 2 and precede it with any vector V 1 that sets theline to 0. Now the vector-pair (V 1; V 2) is a test for the slow-to-rise transition faulton the line. Note that V 1 sets the line to 0 and V 2 sets it to 1. V 2 also createsan observation path to a primary output. If the line is slow to rise then that e�ectwill be observed as a 0 at the output instead of the expected value of 1. The basicassumption in this test is that the faulty delay of the signal rise has to be large,since the observation path may be, and often is, a short path. Besides, the e�ectsof hazards and glitches can interfere with the observation of the output value. Asa result, the tests for transition faults can detect localized (spot) delay defects oflarge (gross) delay amounts. Because of sensitization of short paths these tests mayfail to detect distributed defects, where small delay increases in a large number of

12.4 Delay Test Methodologies 429

latchedoutput

Test clockperiodpriod

appliedV2V1

clockRated

applied

Outputtest clock test clock

CircuitOutput

test clock

CombinationalInputLatches

OutputLatches

Input

Inputtest clock

Figure 12.9: Skewed slow-clock test application to a combinational circuit.

gates cause a long path to fail. The advantages of the transition fault model are:

� The number of faults has an upper bound of twice the number of lines.

� Tests are easy to generate. A stuck-at fault test generator can be easily mod-i�ed to produce tests for transition faults [371, 392].

� Circuits that either have, or are modi�ed to have, a high stuck-at fault coverageusually also have high transition fault testability [707].

Transition fault tests have been used in the industry. It is generally recommendedthat they be augmented by some path delay tests, at least by tests for critical paths.

12.4 Delay Test Methodologies

Practical application of delay tests depends on the type of circuit under test andthe DFT hardware used. We will describe �ve di�erent test methodologies.

12.4.1 Slow-Clock Combinational Test

This procedure is applicable to combinational circuits or to those sequentialcircuits that are internally combinational with ip- ops only at PIs and POs. Thetest architecture is shown in Figure 12.9. Input and output latches can be eitherpart of the circuit or provided by the automatic test equipment (ATE.) Input andoutput test clocks control the application of vectors and latching of combinationaloutputs, respectively. These clocks should be independently controllable to allow aphase delay or skew. A two-vector delay test assumes that all signals due to the �rstvector V 1 will have reached their steady state when V 2 is applied. If this assumptionis not valid, then the actual circuit may still have some transient signals when V 2is applied. These transients can interfere with the testing of the targeted path. Toavoid this problem, vectors are applied at a slower than the rated clock frequency.In the timing diagram of Figure 12.9, the output clock is skewed by an amount thatequals the rated-clock period, which is the time allowed for the V 1! V 2 transitionsto ow through the combinational logic. If the delay of the activated path is longerthan the rated-clock period, then the output produced by V 1 will be captured inthe output latch and an observation of its state will detect the fault.


Normal mode

Scan modeHL

SFF

SFF

CK

CK

CK

TC

HOLD

HL

SCANOUT

Combinational

V1

SCANINHOLD

circuit

PI PO

TC

next V1scanin

scanout,

Test resultSFF: Scan flip-flop

CK period

V1 settles

latched

Test resultV2 statescanin

HL: Hold latch

TC

scanin

V1applied applied

V2

Figure 12.10: Enhanced-scan delay test application to sequential circuit.

In practice the test clock frequency can be slowed down by any amount at thecost of increased test time. This method is useful when the ATE cannot apply thevectors at the rated speed. Tests can be generated without restriction since anyarbitrary vector-pair can be applied. However, only the circuits that conform to thearchitecture of Figure 12.9 can by tested.

12.4.2 Enhanced-Scan Test

This method is applicable to scan types of sequential circuits. Its main advantageis that any arbitrary vector-pair can be applied. So, delay tests can be generatedby considering the combinational logic alone, making the test generation easier.However, a normal scan circuit should be enhanced by inserting hold latches and anadditional HOLD signal. The design and operation of the enhanced ip- op, knownas scan-hold ip- op (SHFF), is discussed in Section 14.4.

Figure 12.10 shows an enhanced scan circuit and the timing diagram of testapplication. Each vector contains two parts, namely, bits corresponding to the PIsand bits corresponding to state variables. The state portion of V 1 is serially shiftedin the scan register via the SCANIN terminal by setting test control TC = 0 andapplying the clock CK. Often, scan is done using a slow-clock to reduce the powerdissipation. However, it is also necessary that any delay faults in the scan path donot interfere with the vector. Scanned V 1 bits are then transferred to hold latches(HL) by activating the HOLD signal while the PI bits of V 1 are applied at PI. Assignals due to V 1 stabilize, the state bits of V 2 are scanned in. Next, simultaneousactivation of HOLD and application of V 2 bits to PI provides a V 1! V 2 transitionat the input of combinational logic. Test control TC = 1 sets the circuit in normalmode for exactly one rated-clock period, at the end of which the clock CK latchesthe combinational outputs in ip- ops. This one cycle of clock must have the ratedperiod. PO signals are directly observed and ip- op states are scanned out. Asusual, scanout can be overlapped with the scanin of the next test. As we pointedout, this architecture has the full exibility of combinational circuit test. Test time


clockSlow

periodclock

Slow clockSlow clock

period

Rated

Normal mode

Path tested

Scan mode

Scan modeSFF

SFF

CK TC

V2 applied

SCANIN

circuit

SCANOUT

Outputs latchedCombinational

V2 by scan shift

V2 functionalTC

TC

SFF: Scan flip-flop

(next V1 scanin)

CK TC

V1 scanin V2Generate Test result scanout

POPI

Figure 12.11: Normal-scan delay test application to sequential circuit.

is similar to that of full scan design (see Chapter 14.) However, scan area overheadis increased due to the hold latch, which also adds some delay in the signal path.

12.4.3 Normal-Scan Sequential Test

Normal full-scan circuits (with no hold latches) can be tested for delay faults,but the vector-pairs must be especially generated [156]. Here, the �rst vector V 1 isscanned in (usually with a slow scan clock) and is then replaced in the scan registerby either (a) applying a one-bit shift to the scan register, or (b) propagating V 1through the combinational logic in the normal mode. Figure 12.11 illustrates thetwo methods.

In the �rst method, known as scan-shift delay test or skewed-load delay test [564,565], scan in of V 1 is followed by one extra cycle of slow-clock while the circuit is stillin the scan mode TC = 0. The test is so designed that V 2 is obtained by a one-bittranslation of V 1. So, only the bit in the ip- op closest to the SCANIN input issupplied externally. PI bits of two vectors, which are not restricted, are directlyapplied at the proper time. As soon as V 2 is applied, the mode is changed fromscan to normal (TC = 1) and one application of clock CK with the rated periodlatches the outputs. The observation of PO is synchronized with the rated-clockand ip- op states are scanned out for observation.

In the second method, the state portion of V 2 must be justi�ed by V 1 appliedto the combinational logic. When the vector-pair has this characteristic, scanningin of V 1 and application of its PI bits automatically produce the state portion ofV 2 at the output of the combinational logic. An application of the clock in thenormal mode and application of the PI part of V 2 creates the V 1! V 2 transition.Keeping the circuit in the normal mode, one rated-clock period later, the outputsare observed at PO or scanned out. This method is also called broad-side delaytest [566].

Both methods are used for testing path-delay and transition faults. However, ahigh fault coverage is dependent on the circuit and cannot be guaranteed due to the


PIPI PI

POPO

11

PI

D23

10

PI PI

33

...

Slow clockclockSlowRated

clock

20

21

PO PO PO PO

Tn-2T1 n-1Tn+mTn+1TnT

...

Figure 12.12: Delay test application to non-scan sequential circuit.

correlation between the two vectors.

12.4.4 Variable-Clock Non-Scan Sequential Test

Testing of a delay fault in a non-scan sequential circuit requires more thantwo vectors [416]. First, the vector-pair should be like the one used in the secondmethod of the last subsection. That is, V 2 should be justi�ed by V 1 through thecombinational function. Second, V 1 should be generated, by a set of vectors startingat some initial state. We will call this set a justi�cation sequence. Third, if the pathdestination is a ip- op then the state should be propagated to some PO. We willcall this part of the test as the propagation sequence. This test scenario is depictedin Figure 12.12 by the time-frame expansion as was used in Chapter 8 for sequentialcircuit ATPG.

In Figure 12.12, vector V 1 is applied in time-frame Tn�1 and the target pathis partially sensitized. Recall that the path has to be fully sensitized only in V 2.That is why we have shown the path with a broken line. In Tn, V 1 produces V 2states in the three ip- ops. However, to ensure that V 2 is correctly produced andis not a�ected by some delays in Tn�1, we must allow extra time for V 1 to propagatethrough the circuit. This is done by using a slow-clock, which is also used for thesame reason for justi�cation and propagation sequences. Thus, only one vector, i.e.,V 2, in the entire test sequence uses the rated-clock. This procedure is known as theslow-clock or variable-clock delay testing.

The slow-clock prevents the delays in the circuit from interfering with the de-tection of the target fault. In practice, the clock can be slowed down by a factorof two or greater. One problem, however, remains. In the time-frame Tn, the pathdestination in Figure 12.12 is ip- op 2. Since the rated-clock is used in this time-frame, other path delays can also a�ect the signals and the state of ip- ops 1 and3 (shown in grey) can also have faulty values. It is very di�cult to generate a testto ensure that paths leading to those ip- ops are not activated. Chakraborty etal. [119] provide several alternatives.

De�nition 12.4 Combinational robust test. A test that guarantees to detect atarget delay fault of a combinational circuit in the presence of arbitrary delays inthe circuit is a combinational robust delay test. Such a test consists of a vector-pair


(V 1; V 2) that must satisfy the conditions we discussed in previous sections. Testapplication must ensure that su�cient time is allowed for changes due to V 1 tostabilize before V 2 is applied.

When a combinational circuit is embedded among ip- ops, a combinationalrobust test is not guaranteed to work in a non-scan circuit.

De�nition 12.5 Sequential robust test. A test that guarantees to detect a targetdelay fault of a sequential circuit in the presence of arbitrary delays in the circuitis a sequential robust test. For variable-clock test application, which applies therated-clock only to a single time-frame, we consider three fault models:

� Fault model A. All ip- ops other than the path destination are assumed to beuna�ected by any delay fault. The propagation sequence can be invalidated ifthe assumption is not true. The tests are not sequential robust.

� Fault model B. All ip- ops other than the path destination are assumed tobe in the unknown state (X) following the rated-clock time-frame. Tests aresequential robust, though the model is pessimistic.

� Fault model C. At the end of the rated-clock time-frame all non-destination ip- ops that have a steady (hazard-free) input during the period of both vectors(V 1; V 2) take that value as their state at the end of the rated-clock time-frame.All other ip- ops assume unknown (X) state. The tests for this model arerobust.

Chakraborty et al. [119] propose a 13-valued algebra for analyzing these faultmodels. Algorithms for deriving path-delay tests for sequential circuits using thevariable-clock mode have been described [17, 199]. According to the reporteddata [17], the sequential benchmark circuit s1494 has 976 paths. Of the 1,952PDFs, tests could be obtained only for 37% of the faults in the variable-clock non-scan mode. In the enhanced-scan mode, 98.7% of the PDFs were tested. Path delaytest generation for non-scan sequential circuits continues to be a di�cult problem.Fortunately, in delay testing, the issue of PDF coverage is not as important as thetesting of long paths.

Path-delay fault simulators can analyze the variable-clock mode. Such resultsgive data on the length of paths that are tested. Reported data [514] gives thefollowing result for the benchmark circuit s35932: Number of vectors = 2,124; TotalPDFs = 394,282; Tested PDFs = 26,228 (6.65% coverage); Longest PDF = 29 gates;Longest tested PDF = 27 gates. These vectors were randomly generated by lettingthe fault simulator select useful vectors. In spite of a low coverage, the longest pathtested is within two gates from the longest physical path. One problem with suchtests is the long test time. In actual test application, the vector sequence should berepeated 2,124 times. In each application a di�erent vector will have the rated-clockwhile all the rest will have slow-clocks. Thus, a total of 2; 124� 2; 124 = 4; 511; 376vectors will be applied.


12.4.5 Rated-Clock Non-Scan Sequential Test

This is the most natural form of test. All vectors, either functional or thosegenerated to cover any types of faults, are applied at the rated speed. A targetdelay fault can be activated in several time frames. If robust detection is desired,one must consider all delay combinations to be potentially possible. Even faultsimulation requires massive computation. Nevertheless, it shows a much reducedPDF coverage for vectors generated for variable-clock test. This is basically due tothe pessimism one assumes in simulating the rated-clock test. Bose et al. [83] givea 41-valued algebra for generating rated-clock tests. Because of high complexity,it will be fruitless to attempt rated-clock test generation for all PDFs. However,inclusion of such tests for critical paths may be extremely useful.

12.5 Practical Considerations in Delay Testing

Timing correctness of VLSI circuits is as important as their logical correctness.The design of a VLSI chip is veri�ed via timing simulation (Section 5.3) and timinganalysis. The timing analysis examines combinational paths in the circuit topology.Delays of gates and interconnects are obtained from the simulator data-base. Allpaths are examined without consideration to sensitizability. Because no signal valuesare used, this analysis is known as \static timing analysis [22, 301, 647]." Aninterested reader may exmine commercial tools like Primetime�. The results oftiming analysis are used in several ways to improve the design and test:

� Timing simulation. Critical paths are simulated by circuit-level or timingsimulators using the stimulus provided by the designer based on the functionalknowledge of the circuit (Chapter 5.) The results of simulation are used to\tune" the design to meet the timing speci�cation.

� Critical path tests. The critical path of a circuit is the longest delay combi-national path between clocked ip- ops. Critical path delay determines theclock period. Tests of a chip normally include test vectors that propagatesignal transitions through critical paths.

� Layout optimization. Critical path data is used for placement of standardcells and custom blocks (memories, etc.), to prioritize interconnects for rout-ing [208], and for transistor-sizing [223]. Chip area can be reduced by shrink-ing the devices in the gates on non-critical paths, letting their delays increase,while larger devices are selectively used only on critical paths.

A careful timing design increases the manufacturing yield but cannot guaranteethat every chip will function correctly. Tests developed for detecting stuck-at faults,when applied at a slower than the rated-clock frequency, uncover many manufactur-ing defects. However, such tests only ascertain the logical correctness of the circuit.

�H. Bhatnagar, Advanced ASIC Chip Synthesis using Synopsys Design Compiler and Primetime.

Boston: Kluwer Academic Publishers, 1999.

12.5 Practical Considerations in Delay Testing 435

Slow clock testing can be due to the limitation of the ATE and test �xturing (cables,probes, etc.) Since stuck-at faults do not model delay faults, this form of testing isoften termed \DC testing" or \static testing."

12.5.1 At-Speed Testing

At-speed testing in which vectors are applied and responses observed at therated-clock speed is essential unless the timing design is too pessimistic and processtolerances are extremely tight. Both of these attributes are not possible for today'sVLSI chips that drive extremely high speed systems and are manufactured throughleading edge processes. Application of the stuck-at fault test vectors at the rated-clock speed, though used frequently, is not the best strategy. This is because thosevectors may not have a high delay fault coverage. Path-delay tests for critical pathsshould be included in the at-speed testing. Considering the possibility of a verylarge number of paths, critical path testing is a good approach. These tests are verygood at uncovering \correlated defects." These defects are caused by variations inthe manufacturing process and a�ect all components on the chip in a similar way.For example, the resistivity of all interconnects may increase, or all transistors mayslow down. Obviously, longest delay paths will be the �rst to fail.

Another class of defects is referred to as spot defects or gross defects. Thesea�ect localized regions of the chip. Though physically small they can cause just afew devices or interconnects to have grossly excessive delays. Transition fault testsprovide the capability of detecting such defects. Besides, the number of transitionfaults is a linear function of the circuit size (similar to that of stuck-at faults) andso a high percentage can be covered. Therefore, a combination of critical path-delaytests and transition tests provides adequate at-speed testing.

Built-in self-test (BIST) for delay-faults. Considering the fact that a high-speedATE is expensive and sometimes unavailable, BIST is an alternative method ofat-speed testing. This requires on-chip circuitry for vector generation and responseanalysis. Only a high-speed clock, which determines the speed of testing, is suppliedfrom outside. While pseudo-random vectors provide good coverage (sometimes withtest points) of stuck-at faults, they can also cover a large percentage of transitionfaults if applied at high speed. Coverage of path-delay faults frequently requiresadditional modi�cations in the combinational logic, especially if robust tests aredesired (see Section 15.4.) There are several problems that require careful con-siderations in the implementation of at-speed BIST. First, if there are unscanned ip- ops in the logic being tested then their initialization must be examined. Theresponse signature register should be initialized only after all ip- ops have been ini-tialized. Second, when pseudo-random patterns are applied to combinational logic,some long combinational paths that are non-functional in the sequential mode canbe activated. If that happens, BIST can produce timing failures even in a circuitthat meets the functional timing requirements. In such cases, the clock rate of BISTshould be lowered below the speci�cation. A suitable clock rate can be found bytiming simulation. A recent paper reports the results on a boundary-scan master(BSM2) chip [299], designed for a 65 MHz clock rate. As determined by timing


simulation, BIST was operated at a 40 MHz clock rate to avoid failures due tothe activation of false-paths. Third, the power consumption of at-speed BIST canexceed the power rating of the chip. This is because of the high signal activitythat random vectors cause in some circuits. Both peak and average power for BISTshould be analyzed and corrected, if necessary. Increased average power can causeheating of the device under test and increased peak power can produce noise-relatedfailures.

12.6 Summary

In the 1974 paper, Breuer [91] was mainly concerned with the delay faults inasynchronous circuits. That is a very di�cult problem. In the following years,the industry largely adopted the synchronous (clocked) design style. That did notsimplify the delay test problem because sizes of VLSI chips grew beyond anythingimaginable in the early days. In 1980, Lesser and Shedletsky [391] studied theproblem of path delay testing for scan circuits. They used single-input-change (SIC)vector-pairs to measure delays of a subset of combinational paths. The measureddata were analyzed to characterize the delays of all paths of interest. Besides �ndinga suitable set of tests, di�culties in this method also arise in the application of tests.This is because the arrival times of events at combinational outputs should be exactlymeasured rather than just determining that the events occur prior to some clockedge. Still, in view of the fact that path delay testing must deal with a large numberof paths, there has been renewed interest in this type of technique [651].

All technology indicators point to the increasing use of delay testing in thefuture. The �eld of delay testing has expanded recently. Due to the limited space,we had to focus on fundamentals, leaving out many important techniques. We endby listing a set of topics on which an interested reader may continue the study:delay fault models, classi�cation of delay faults, multi-valued algebras, path delayfault simulators, path counting techniques, and design for delay fault testability.

Problems

12.1 Non-robust path-delay test. Does the exclusive-OR circuit in Figure 12.13have any redundant stuck-at fault? How many paths does the circuit have?Derive non-robust tests for all path-delay faults (PDFs). Are there any singly-untestable PDFs? Note: Any untestable PDFs can be eliminated by cir-

q

p

zm

ba

j

h n

k

c

g

Figure 12.13: Exclusive-OR circuit for Problem 12.1.

Problems 437

cuit transformation known as the KMS (Keutzer, Malik, and Saldanha) algo-rithm [352].

12.2 Robust path-delay tests. Remove the redundant fault Q stuck-at-1 from thecircuit of Figure 12.2 and verify that all path-delay faults in the irredundantcircuit are robustly testable.

12.3 Robust path-delay tests. Show that a robust path-delay test must produce a\real" transition (di�erent initial and �nal values) at the output. Is any pathin the circuit of Figure 12.4 robustly testable?

12.4 Single-input change (SIC) tests. Prove that every singly-testable (i.e., non-robustly testable) fault has a single-input change test.

12.5 Path-delay tests. Consider the path C�F�G in the circuit of Figure 12.14(a):

(a) Derive a test for a rising transition at C.

(b) Will the above test work if a falling transition is applied at B?

(c) Sketch all signals in the circuit of Figure 12.14(a) for the case (b) abovewhen all gates have one unit of delay. Assuming that the permitted delayfor the circuit is 2.5 units, interpret the result of the test. Can you locatethe faulty path?

(d) How will you diagnose the faulty path?

F0

B

z

y

x

a

b

(a) Circuit for Problem 12.5.

E

F

G

S1

S1

S1C

A

C

(b) Circuit for Problem 12.6.

D

D

B

A

Figure 12.14: Path-delay fault testing circuits for Problems 12.5 and 12.6.

12.6 Path-delay test robustness. Consider the path shown in bold lines in the circuitof Figure 12.14(b). Suppose that we choose a test: b = S1, a = F0, x = S1,and y = S1.

(a) The permitted circuit delay is 3.5 units. Assuming that the gate A hasa delay of 5 units and that all other gates have one unit of delay, sketchthe relevant waveforms to show that the test is not robust.

(b) Can you derive a robust test?

12.7 O�-path signals. Specify the o�-path signal states for delay testing of a two-input XOR gate.


12.8 Logical and timing conditions. Boolean gates have inputs A, B, C, ..., andoutput Z. To test the propagation delay from A to Z, a transition is prop-agated through the gate. Consider both rising and falling transitions at A.Find the least restrictive o�-path signal states to satisfy these conditions:

(a) Logical Condition { The pre-transition and post-transition steady statesof Z must be the same as the respective states of A, irrespective of thevalues at other inputs of the gate.

(b) Timing Condition { The signal at Z must not change from its pre-transition steady state as long as A is steady in the pre-transition state.

12.9 Path counting. Write an algorithm to count the number of paths in a combi-national circuit. What is the complexity of your algorithm?

12.10 Pomeranz-Reddy example [526]. Show that the number of paths in the circuitof Figure 12.15 is 3� 2k � 2.

Cell kCell 2Cell 1

Figure 12.15: Circuit for path counting in Problem 12.10.

12.11 Sequential path-delay fault testing. Prove that in the circuit of Figure 12.16(a),there is no robust path-delay fault test for the path d-e-f-g.

DA

(b) Circuit for Problem 12.12.(a) Circuit for Problem 12.11.

b

CK

cFF

cba

g

fe

d

FFCK

Figure 12.16: Circuits for Problems 12.11 and 12.12.

12.12 Sequential path-delay fault ATPG. In the circuit of Figure 12.16(b), determinewhether there are robust path-delay tests for faults " A �D and # A�D.

Documents

DELAY TESTagrawvd/BOOK/book12.pdf · 12.1 Delay Test Problem 419 0 0 5 1 2 3 1 2 2 1 3 4 6 P1 J K Q P2 P3 EG A B C H Figure 12.2: An example of transition propagation through paths