Dell Vostro 1310 schematics.pdf

Embed Size (px)

Citation preview

  • AA

    B

    B

    C

    C

    D

    D

    E

    E

    1 1

    2 2

    3 3

    4 4

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1Cover Sheet

    Custom

    1 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Schematic Document

    Crestline + ICH8Rev:0.2

    Compal Confidential

    2007 / 11 / 14

    Compal Electronics, Inc.

  • AA

    B

    B

    C

    C

    D

    D

    E

    E

    1 1

    2 2

    3 3

    4 4

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1Block diagram

    Custom

    2 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    File Name : LA-4231PCompal confidential

    Thermal SensorADM1032ARMZ

    Clock GeneratorICS 9LPRS365

    Fan conn

    Mobile Merom

    uFCPGA-478 CPU

    FSB667/800MHz 1.05V

    H_A#(3..35)H_D#(0..63)

    FCBGA 1299

    Intel Crestline MCH

    DMI X4

    BANK 0, 1, 2, 3DDR2-SO-DIMM X2DDR2 667MHz 1.8V

    Dual Channel

    LPC BUS

    CardBus ControllerO2MICRO OZ129

    CDROM Conn.

    PCI

    mBGA-676

    Intel ICH8

    Touch Pad CONN. Int.KBD

    ENE KB926

    10/100/1000 LAN

    RJ45/11 CONN

    PCI-E BUS

    SATA HDD Connector

    SATA MasterSATA Slave

    1394

    C-Link

    CK505

    ALC268Audio CKT AMP & Audio Jack

    USB conn x 4

    Felica ConnUSB2.0

    Azalia

    Mic

    FingerPrinter

    BT Conn

    SMB 13.3

    TSSOP-64

    Express Card

    Camera

    Power On/Off CKT.

    DC/DC Interface CKT.

    Power Circuit DC/DC

    RTC CKT.

    Power OK CKT.

    Express Card

    TPM CONN

    Mini-Card-2

    BIOS(System/EC)

    Mini-Card-1(WLAN)

    Mini-Card-2

    Compal Electronics, Inc.

    CRT

    LVDS Panel Interface

    nVidia NB8M-GS

    VRAM x 2

    Media Card

    REALTEKRTL8111C-GR

    P.15

    P.15

    P.4

    P.4

    P.4,5,6

    P.7,8,9,10,11,12P.34,35,36,37P.38

    P.40

    P.22P.24 P.24 P.28

    P.13,14

    P.16

    P.17,18,19,20

    P.29

    P.29P.31P.31

    P.29

    P.18

    P.21

    P.21

    P.25 P.26

    P.24

    P.28

    P.32

    P.32

    P.32

    P.32

    P.32

    ZZZ1

    PCB

  • AA

    B

    B

    C

    C

    D

    D

    E

    E

    1 1

    2 2

    3 3

    4 4

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1Notes

    Custom

    3 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    External PCI DevicesDevice IDSEL# REQ#/GNT# InterruptsCardBus AD21

    EC SM Bus1 addressDevice

    ADM1032

    EC SM Bus2 addressDevice

    Smart Battery

    0 PIRQE/PIRQF/PIRQG

    EEPROM(24C16/02)

    4D0001 011X b?

    1010 000X b?

    (24C04) 1011 000Xb?

    ICH7 SM Bus addressDevice

    Clock Generator(ICS ICS9LPR310)

    Address

    Address Address

    1101 001Xb?

    STATESIGNAL

    Full ON

    S1(Power On Suspend)

    S3 (Suspend to RAM)

    S4 (Suspend to Disk)

    S5 (Soft OFF)

    SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

    ON

    ON

    ON

    ON

    ON

    ON

    ON ON

    ON

    ON

    ON

    OFF

    OFF

    OFF

    OFF

    OFF

    OFF

    OFF

    OFF

    LOW

    LOW LOW LOW LOW

    LOWLOWLOW

    LOW

    LOW

    LOW

    HIGH HIGH HIGH HIGH

    HIGHHIGHHIGH

    HIGH

    HIGH

    HIGH

    Board ID Table for AD channel

    DDRII DIMM0 1001 000Xb?

    DDRII DIMM2 1001 010Xb?

    Vcc 3.3V +/- 5%100K +/- 5%Ra / Rc

    Board ID Rb / Rd V min0123

    08.2K +/- 5%

    0 V0.216 V 0.250 V 0.289 V0.436 V0.712 V

    0.503 V0.819 V

    0.538 V0.875 V

    AD_BID V typAD_BID VAD_BID max

    18K +/- 5%33K +/- 5%56K +/- 5%100K +/- 5%200K +/- 5%

    3.300 V

    0 V 0 V

    4567 NC

    1.036 V1.453 V 1.650 V 1.759 V1.935 V2.500 V

    2.200 V3.300 V

    2.341 V

    1.185 V 1.264 V

    BOARD ID Table Board ID

    01234567

    PCB Revision0.1

    BTO Option TableBTO Item BOM Structure

    0.2

    O MEANS ONX MEANS OFF

    O

    X

    Voltage Rails

    S3

    +3VS

    X

    X

    +3VALW

    +5VS

    O

    +CPU_CORE

    +1.8VS

    OO

    XX X

    +VCCP

    powerplane

    CLOCK

    OOOXX

    OOOOX

    S5 S4/ Battery only

    X X X

    +3V

    O MEANS ON X MEANS OFF

    +1.25VS+B

    State

    +1.5VS+1.8V

    S5 S4/AC & Batterydon't exist

    S5 S4/AC

    +5VALW

    S0

    OO

    S3 : STRS4 : STDS5 : SOFT OFF

    Compal Electronics, Inc.

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    EC_SMB_CK2EC_SMB_DA2

    H_THERMDA

    H_THERMDC

    THERM#

    EC_SMB_DA2

    EC_SMB_CK2

    H_PROCHOT# OCP#

    THERM_SCI#

    H_PROCHOT#

    H_REQ#2

    H_DBSY#

    H_ADS#H_A#3

    H_A#22

    H_A#19

    XDP_TRST#

    H_REQ#4

    H_ADSTB#0

    H_A#18

    H_TRDY#H_REQ#3

    H_INTR

    H_HITM#

    H_A#6

    H_A#26

    H_FERR#

    H_DRDY#

    CLK_CPU_BCLKCLK_CPU_BCLK#

    H_A#4

    H_A#23

    H_A#32

    H_BR0#

    XDP_BPM#1

    H_A#7

    H_A#13

    H_THERMDC

    XDP_TCK

    H_RS#1

    H_LOCK#

    H_A#5

    H_A#25

    H_A#21

    H_A#10

    H_A#34

    H_NMI

    H_DEFER#

    H_REQ#0

    XDP_DBRESET#

    H_BPRI#

    H_ADSTB#1

    H_A#9

    H_A#31

    H_A#35

    XDP_BPM#2

    XDP_TMS

    H_RESET#

    XDP_BPM#5XDP_BPM#4

    H_INIT#

    H_A#30

    H_A#24

    H_A#16

    H_A#11

    H_RS#2

    H_IGNNE#

    XDP_BPM#0

    H_REQ#1

    H_A#8

    H_A#28

    H_STPCLK#

    H_SMI#

    XDP_BPM#3

    XDP_TDOXDP_TDI

    H_A#27

    H_A#20

    H_A#15

    H_THERMTRIP#

    H_RS#0

    H_HIT#

    H_BNR#

    H_A20M#

    H_A#17

    H_A#12

    H_A#33

    H_THERMDA

    H_A#29

    H_A#14H_IERR#

    XDP_TDI

    XDP_TMS

    XDP_TCK

    XDP_BPM#5

    XDP_TRST#

    EN_DFAN1

    H_RESET#

    FAN1_POWER

    EC_SMB_DA229,31,35EC_SMB_CK229,31,35

    OCP# 19

    H_A#[3..16]7

    H_ADSTB#07

    H_REQ#07H_REQ#17H_REQ#27

    H_REQ#47H_A#[17..35]7

    H_ADSTB#17

    H_A20M#18H_FERR#18H_IGNNE#18

    H_STPCLK#18H_INTR18H_NMI18H_SMI#18

    H_ADS# 7H_BNR# 7H_BPRI# 7

    H_BR0# 7

    H_THERMTRIP# 7,18

    CLK_CPU_BCLK 16CLK_CPU_BCLK# 16

    EC_THERM# 19,29

    H_RESET# 7

    H_TRDY# 7

    H_DEFER# 7H_DRDY# 7H_DBSY# 7

    H_INIT# 18

    H_LOCK# 7

    H_HIT# 7H_HITM# 7

    XDP_DBRESET# 19

    H_REQ#37

    FAN_SPEED129

    EN_DFAN129

    H_RS#0 7H_RS#1 7H_RS#2 7

    +3VS

    +3VS

    +VCCP

    +VCCP

    +VCCP

    +3VS

    +VCCP

    +5VS

    +VCCP

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1

    Merom(1/3)-AGTL+/XDPCustom

    4 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Thermal Sensor EMC1402-1-ACZL-TR

    Address:100_1100

    H_THERMDA, H_THERMDC routing together,Trace width / Spacing = 10 / 10 mil

    FAN1

    FAN1 Control and Tachometer

    XDP Reserve

    40mil

    Add on 1003

    H_THRMTRIP# should connectto ICH8 and GMCH withoutT-ing (No stub)

    Compal Electronics, Inc.

    R6110K_0402_5%

    1

    2

    U3

    RT9027BPS SO 8P

    VEN1VIN2

    GND 5GND 6

    GND 8

    VO3VSET4

    GND 7

    R171 39_0402_1%

    1 2

    R114 56_0402_5%

    12

    R350

    10K_0402_5%

    1 2

    T29

    R35410K_0402_5%@

    1

    2

    T47

    R108

    56_0402_5%@

    1

    2

    R8956_0402_5%

    12

    C7610U_1206_16V4Z~N

    12

    C77 10U_1206_16V4Z~N1 2

    R172 150_0402_1%

    1 2

    C691000P_0402_50V7K~N

    12

    T28

    T48

    R182 560_0402_5%

    1 2

    R4154.9_0402_1%@

    1 2

    AD

    DR

    GR

    OU

    P 0A

    DD

    R G

    RO

    UP 1

    C

    O

    N

    T

    R

    O

    L

    X

    D

    P

    /

    I

    T

    P

    S

    I

    G

    N

    A

    L

    S

    H CLK

    THERMAL

    R

    E

    S

    E

    R

    V

    E

    D

    ICH

    JP2A

    Merom Ball-out Rev 1aconn@

    A[10]#N3A[11]#P5A[12]#P2A[13]#L2A[14]#P4A[15]#P1A[16]#R1

    A[17]#Y2A[18]#U5A[19]#R3A[20]#W6A[21]#U4A[22]#Y5A[23]#U1A[24]#R4A[25]#T5A[26]#T3A[27]#W2A[28]#W5A[29]#Y4

    A[3]#J4

    A[30]#U2A[31]#V4

    RSVD[01]M4RSVD[02]N5RSVD[03]T2RSVD[04]V3RSVD[05]B2RSVD[06]C3RSVD[07]D2RSVD[08]D22

    A[4]#L5A[5]#L4A[6]#K5A[7]#M3A[8]#N2A[9]#J1

    A20M#A6

    ADS# H1

    ADSTB[0]#M1

    ADSTB[1]#V1

    RSVD[09]D3

    BCLK[0] A22BCLK[1] A21

    BNR# E2

    BPM[0]# AD4BPM[1]# AD3BPM[2]# AD1BPM[3]# AC4

    BPRI# G5

    BR0# F1

    DBR# C20

    DBSY# E1

    DEFER# H5DRDY# F21

    FERR#A5

    HIT# G6HITM# E4

    IERR# D20

    IGNNE#C4

    INIT# B3

    LINT0C6LINT1B4

    LOCK# H4

    PRDY# AC2PREQ# AC1

    PROCHOT# D21

    REQ[0]#K3REQ[1]#H2REQ[2]#K2REQ[3]#J3REQ[4]#L1

    RESET# C1RS[0]# F3RS[1]# F4RS[2]# G3

    SMI#A3

    STPCLK#D5

    TCK AC5TDI AA6

    TDO AB3

    THERMTRIP# C7

    THERMDA A24THERMDC B25

    TMS AB5

    TRDY# G2

    TRST# AB6

    A[32]#W3A[33]#AA4A[34]#AB2A[35]#AA3

    RSVD[10]F6

    R170 27_0402_5%

    1 2

    R362 54.9_0402_1% @

    1 2

    JFAN1

    ACES_85205-03001conn@

    112233

    GND4GND5

    C940.01U_0402_16V7K 1

    2

    R3550_0402_5%

    @ 12

    EB

    C

    Q11MMBT3904_SOT23

    @

    2

    3 1

    T27

    U2

    EMC1402-2-ACZL-TR MSOP 8P

    VDD1

    ALERT# 6

    THERM#4 GND 5

    D+2

    D-3

    SCLK 8

    SDATA 7C423

    2200P_0402_50V7K~N

    1 2

    T33

    C424

    0.1U_0402_16V4Z~N 1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    V_CPU_GTLREF

    H_D#4

    H_D#14

    H_D#10H_D#9

    H_D#3

    H_D#13

    H_D#6

    H_D#2

    H_D#8

    H_D#12

    H_D#1

    H_D#5

    H_D#7

    H_D#11

    H_D#0

    H_D#15

    H_D#27

    H_D#25

    H_D#31

    H_D#24

    H_D#20

    H_D#30

    H_D#23

    H_D#19

    H_D#29

    H_D#16

    H_D#18

    H_D#22

    H_D#26

    H_D#28

    H_D#17

    H_D#21

    H_DINV#0

    H_DINV#1 H_DINV#3

    H_DINV#2

    H_DSTBN#2H_DSTBP#2

    H_DSTBP#1H_DSTBN#1

    H_DSTBP#0H_DSTBN#0

    H_DSTBN#3H_DSTBP#3

    H_D#48

    H_D#56

    H_D#52

    H_D#59

    H_D#63

    H_D#55

    H_D#51

    H_D#62

    H_D#58

    H_D#54

    H_D#50

    H_D#57

    H_D#61

    H_D#53

    H_D#49

    H_D#60

    COMP0

    COMP2COMP3

    COMP1

    CPU_BSEL2CPU_BSEL1CPU_BSEL0

    H_CPUSLP#

    H_DPSLP#H_DPRSTP#

    H_PSI#

    V_CPU_GTLREFTEST1TEST2

    VSSSENSE

    VCCSENSE

    H_DPWR#

    H_D#47

    H_D#43H_D#42

    H_D#37

    H_D#34H_D#33

    H_D#39H_D#38

    H_D#41H_D#40

    H_D#35H_D#36

    H_D#45H_D#44

    H_D#32

    H_D#46

    TEST3

    TEST5TEST4

    H_PWRGOOD

    VSSSENSE

    VCCSENSE

    TEST6

    VCCSENSE 49

    VSSSENSE 49

    H_D#[0..15]7

    H_DSTBN#07H_DSTBP#07H_DINV#07H_D#[16..31]7

    H_DSTBN#17H_DSTBP#17H_DINV#17

    CPU_BSEL016CPU_BSEL116CPU_BSEL216

    H_D#[32..47] 7

    H_DSTBN#2 7H_DSTBP#2 7H_DINV#2 7H_D#[48..63] 7

    H_DSTBN#3 7H_DSTBP#3 7H_DINV#3 7

    H_DPRSTP# 7,18,49H_DPSLP# 18

    H_CPUSLP# 7

    H_DPWR# 7

    H_PSI# 49

    CPU_VID0 49CPU_VID1 49CPU_VID2 49CPU_VID3 49CPU_VID4 49CPU_VID5 49CPU_VID6 49

    H_PWRGOOD 18

    +VCCP

    +VCCP

    +1.5VS

    +CPU_CORE +CPU_CORE

    +CPU_CORE

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1Merom(2/3)-AGTL+/PWR

    Custom

    5 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Close to CPU pin AD26within 500mils.

    CPU_BSEL CPU_BSEL2 CPU_BSEL1

    166

    200

    0 1

    0 1

    CPU_BSEL0

    1

    0

    Resistor placed within0.5" of CPU pin.Traceshould be at least 25mils away from any othertoggling signal.COMP[0,2] trace width is18 mils. COMP[1,3] tracewidth is 4 mils.

    Length match within 25 mils.The trace width/space/other is20/7/25.

    Close to CPU pinwithin 500mils.

    Near pin B26

    layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

    Compal Electronics, Inc.

    R861K_0402_1%

    1

    2

    JP2C

    Merom Ball-out Rev 1a .conn@

    VCC[001]A7VCC[002]A9VCC[003]A10VCC[004]A12VCC[005]A13VCC[006]A15VCC[007]A17VCC[008]A18VCC[009]A20VCC[010]B7VCC[011]B9VCC[012]B10VCC[013]B12VCC[014]B14VCC[015]B15VCC[016]B17VCC[017]B18VCC[018]B20VCC[019]C9VCC[020]C10VCC[021]C12VCC[022]C13VCC[023]C15VCC[024]C17VCC[025]C18VCC[026]D9VCC[027]D10VCC[028]D12VCC[029]D14VCC[030]D15VCC[031]D17VCC[032]D18VCC[033]E7VCC[034]E9VCC[035]E10VCC[036]E12VCC[037]E13VCC[038]E15VCC[039]E17VCC[040]E18VCC[041]E20VCC[042]F7VCC[043]F9VCC[044]F10VCC[045]F12VCC[046]F14VCC[047]F15VCC[048]F17VCC[049]F18VCC[050]F20VCC[051]AA7VCC[052]AA9VCC[053]AA10VCC[054]AA12VCC[055]AA13VCC[056]AA15VCC[057]AA17VCC[058]AA18VCC[059]AA20VCC[060]AB9VCC[061]AC10VCC[062]AB10VCC[063]AB12VCC[064]AB14VCC[065]AB15VCC[066]AB17VCC[067]AB18

    VCC[068] AB20VCC[069] AB7VCC[070] AC7VCC[071] AC9VCC[072] AC12VCC[073] AC13VCC[074] AC15VCC[075] AC17VCC[076] AC18VCC[077] AD7VCC[078] AD9VCC[079] AD10VCC[080] AD12VCC[081] AD14VCC[082] AD15VCC[083] AD17VCC[084] AD18VCC[085] AE9VCC[086] AE10VCC[087] AE12VCC[088] AE13VCC[089] AE15VCC[090] AE17VCC[091] AE18VCC[092] AE20VCC[093] AF9VCC[094] AF10VCC[095] AF12VCC[096] AF14VCC[097] AF15VCC[098] AF17VCC[099] AF18VCC[100] AF20

    VCCA[01] B26

    VCCP[03] J6VCCP[04] K6VCCP[05] M6VCCP[06] J21VCCP[07] K21VCCP[08] M21VCCP[09] N21VCCP[10] N6VCCP[11] R21VCCP[12] R6VCCP[13] T21VCCP[14] T6VCCP[15] V21VCCP[16] W21

    VCCSENSE AF7

    VID[0] AD6VID[1] AF5VID[2] AE5VID[3] AF4VID[4] AE3VID[5] AF3VID[6] AE2

    VSSSENSE AE7

    VCCA[02] C26

    VCCP[01] G21VCCP[02] V6

    T49

    +C140

    330U_V_2.5VM

    1

    2

    R

    8

    7

    5

    4

    .

    9

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    C

    4

    1

    2

    1

    0

    U

    _

    0

    8

    0

    5

    _

    1

    0

    V

    4

    Z

    ~

    N

    1

    2

    R

    1

    7

    3

    2

    7

    .

    4

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    DA

    TA G

    RP 0

    DA

    TA G

    RP 1

    D

    A

    T

    A

    G

    R

    P

    2

    D

    A

    T

    A

    G

    R

    P

    3

    MISC

    JP2B

    Merom Ball-out Rev 1aconn@

    COMP[0] R26COMP[1] U26COMP[2] AA1COMP[3] Y1

    D[0]#E22D[1]#F24

    D[10]#J24D[11]#J23D[12]#H22D[13]#F26D[14]#K22D[15]#H23

    D[16]#N22D[17]#K25D[18]#P26D[19]#R23

    D[2]#E26

    D[20]#L23D[21]#M24D[22]#L22D[23]#M23D[24]#P25D[25]#P23D[26]#P22D[27]#T24D[28]#R24D[29]#L25

    D[3]#G22

    D[30]#T25D[31]#N25

    D[32]# Y22D[33]# AB24D[34]# V24D[35]# V26D[36]# V23D[37]# T22D[38]# U25D[39]# U23

    D[4]#F23

    D[40]# Y25D[41]# W22D[42]# Y23D[43]# W24D[44]# W25D[45]# AA23D[46]# AA24D[47]# AB25

    D[48]# AE24D[49]# AD24

    D[5]#G25

    D[50]# AA21D[51]# AB22D[52]# AB21D[53]# AC26D[54]# AD20D[55]# AE22D[56]# AF23D[57]# AC25D[58]# AE21D[59]# AD21

    D[6]#E25

    D[60]# AC22D[61]# AD23D[62]# AF22D[63]# AC23

    D[7]#E23D[8]#K24D[9]#G24

    TEST5AF1

    DINV[0]#H25

    DINV[1]#N24

    DINV[2]# U22

    DINV[3]# AC20

    DPRSTP# E5DPSLP# B5DPWR# D24

    DSTBN[0]#J26

    DSTBN[1]#L26

    DSTBN[2]# Y26

    DSTBN[3]# AE25

    DSTBP[0]#H26

    DSTBP[1]#M26

    DSTBP[2]# AA26

    DSTBP[3]# AF24

    GTLREFAD26

    PSI# AE6

    PWRGOOD D6SLP# D7

    TEST3C24

    BSEL[0]B22BSEL[1]B23BSEL[2]C21

    TEST2D25

    TEST4AF26

    TEST6A26

    TEST1C23

    T14R90 1K_0402_5%@1 2

    R359100_0402_1%

    1 2

    R852K_0402_1%

    1

    2

    T15

    C

    4

    0

    9

    0

    .

    0

    1

    U

    _

    0

    4

    0

    2

    _

    1

    6

    V

    7

    K

    ~

    N

    1

    2

    R

    1

    7

    4

    5

    4

    .

    9

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R91 1K_0402_5%@1 2

    R

    8

    8

    2

    7

    .

    4

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R360100_0402_1%

    1 2

    T13

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    +CPU_CORE

    +VCCP

    +CPU_CORE

    +CPU_CORE

    +CPU_CORE

    +CPU_CORE

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1

    Merom(3/3)-GND&BypassCustom

    6 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Place these insidesocket cavity on L8(North sideSecondary)

    ESR 1980uFNear CPU CORE regulator

    Compal Electronics, Inc.

    10uF 0805 X5R -> 85 degree.High Frequence Decoupling

    Place these caps insidethe CPU socket cavity.( Left side on Top ).

    Place these caps insidethe CPU socket cavity.

    Place these caps insidethe CPU socket cavity.

    ( Right side on Top side).

    Place these caps insidethe CPU socket cavity.

    ( Left side on Bottom ).

    ( Right side on Bottom ).

    Place these caps insidethe CPU socket.( Left side on Top ).

    Place these caps insidethe CPU socket.( Right side on Top ).

    C117210U_0805_6.3V6M

    1

    2

    +C190

    330U_V_2.5VM

    1

    2

    C115910U_0805_6.3V6M

    1

    2

    C115710U_0805_6.3V6M

    1

    2

    C118010U_0805_6.3V6M

    1

    2

    C115310U_0805_6.3V6M

    1

    2

    +C426

    330U_V_2.5VM

    1

    2

    C117610U_0805_6.3V6M

    1

    2

    C183

    0.1U_0402_10V6K

    1

    2

    C116310U_0805_6.3V6M

    1

    2

    C118110U_0805_6.3V6M

    1

    2

    C209

    0.1U_0402_10V6K

    1

    2

    C115810U_0805_6.3V6M

    1

    2

    C116810U_0805_6.3V6M

    1

    2

    +C212

    220U_D

    2_4VY_R15M

    1

    2

    C117010U_0805_6.3V6M

    1

    2

    C210

    0.1U_0402_10V6K

    1

    2

    C116610U_0805_6.3V6M

    1

    2

    C117910U_0805_6.3V6M

    1

    2

    C184

    0.1U_0402_10V6K

    1

    2

    C117110U_0805_6.3V6M

    1

    2

    C117310U_0805_6.3V6M

    1

    2

    C116910U_0805_6.3V6M

    1

    2

    +C429

    330U_V_2.5VM

    @

    1

    2

    C117410U_0805_6.3V6M

    1

    2

    C117510U_0805_6.3V6M

    1

    2

    C116010U_0805_6.3V6M

    1

    2

    C185

    0.1U_0402_10V6K

    1

    2

    C117710U_0805_6.3V6M

    1

    2

    C116110U_0805_6.3V6M

    1

    2

    +C207

    330U_V_2.5VM

    1

    2

    C115210U_0805_6.3V6M

    1

    2

    C115010U_0805_6.3V6M

    1

    2

    C115610U_0805_6.3V6M

    1

    2

    C117810U_0805_6.3V6M

    1

    2

    C116710U_0805_6.3V6M

    1

    2

    C115410U_0805_6.3V6M

    1

    2

    C115110U_0805_6.3V6M

    1

    2

    C115510U_0805_6.3V6M

    1

    2

    C116510U_0805_6.3V6M

    1

    2

    C208

    0.1U_0402_10V6K

    1

    2

    C116410U_0805_6.3V6M

    1

    2

    JP2D

    Merom Ball-out Rev 1a .conn@

    VSS[082] P6

    VSS[148] AE11

    VSS[002]A8VSS[003]A11VSS[004]A14VSS[005]A16VSS[006]A19VSS[007]A23VSS[008]AF2VSS[009]B6VSS[010]B8VSS[011]B11VSS[012]B13VSS[013]B16VSS[014]B19VSS[015]B21VSS[016]B24VSS[017]C5VSS[018]C8VSS[019]C11VSS[020]C14VSS[021]C16VSS[022]C19VSS[023]C2VSS[024]C22VSS[025]C25VSS[026]D1VSS[027]D4VSS[028]D8VSS[029]D11VSS[030]D13VSS[031]D16VSS[032]D19VSS[033]D23VSS[034]D26VSS[035]E3VSS[036]E6VSS[037]E8VSS[038]E11VSS[039]E14VSS[040]E16VSS[041]E19VSS[042]E21VSS[043]E24VSS[044]F5VSS[045]F8VSS[046]F11VSS[047]F13VSS[048]F16VSS[049]F19VSS[050]F2VSS[051]F22VSS[052]F25VSS[053]G4VSS[054]G1VSS[055]G23VSS[056]G26VSS[057]H3VSS[058]H6VSS[059]H21VSS[060]H24VSS[061]J2VSS[062]J5VSS[063]J22VSS[064]J25VSS[065]K1VSS[066]K4VSS[067]K23VSS[068]K26VSS[069]L3VSS[070]L6VSS[071]L21VSS[072]L24VSS[073]M2VSS[074]M5VSS[075]M22VSS[076]M25VSS[077]N1VSS[078]N4VSS[079]N23VSS[080]N26VSS[081]P3 VSS[162] A25

    VSS[161] AF21VSS[160] AF19VSS[159] AF16VSS[158] AF13VSS[157] AF11VSS[156] AF8VSS[155] AF6VSS[154] A2VSS[153] AE26VSS[152] AE23VSS[151] AE19

    VSS[083] P21VSS[084] P24VSS[085] R2VSS[086] R5VSS[087] R22VSS[088] R25VSS[089] T1VSS[090] T4VSS[091] T23VSS[092] T26VSS[093] U3VSS[094] U6VSS[095] U21VSS[096] U24VSS[097] V2VSS[098] V5VSS[099] V22VSS[100] V25VSS[101] W1VSS[102] W4VSS[103] W23VSS[104] W26VSS[105] Y3

    VSS[107] Y21VSS[108] Y24VSS[109] AA2VSS[110] AA5VSS[111] AA8VSS[112] AA11VSS[113] AA14VSS[114] AA16VSS[115] AA19VSS[116] AA22VSS[117] AA25VSS[118] AB1VSS[119] AB4VSS[120] AB8VSS[121] AB11VSS[122] AB13VSS[123] AB16VSS[124] AB19VSS[125] AB23VSS[126] AB26VSS[127] AC3VSS[128] AC6VSS[129] AC8VSS[130] AC11VSS[131] AC14VSS[132] AC16VSS[133] AC19VSS[134] AC21VSS[135] AC24VSS[136] AD2VSS[137] AD5VSS[138] AD8VSS[139] AD11VSS[140] AD13VSS[141] AD16VSS[142] AD19VSS[143] AD22VSS[144] AD25VSS[145] AE1VSS[146] AE4

    VSS[106] Y6

    VSS[001]A4

    VSS[149] AE14VSS[150] AE16

    VSS[147] AE8

    VSS[163] AF25

    C116210U_0805_6.3V6M

    1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    H_SWNGH_VREF

    PM_EXTTS#0

    PM_EXTTS#1

    DDR_CKE0_DIMMADDR_CKE1_DIMMA

    DDR_CKE3_DIMMB

    DDR_CS1_DIMMA#

    DDR_CKE2_DIMMB

    DDR_CS0_DIMMA#

    DDR_CS3_DIMMB#DDR_CS2_DIMMB#

    CLK_MCH_3GPLL#CLK_MCH_3GPLL

    PLT_RST# PLT_RST#_R

    M_CLK_DDR3

    M_CLK_DDR#0M_CLK_DDR#1M_CLK_DDR#2

    M_CLK_DDR2

    M_CLK_DDR0M_CLK_DDR1

    SMRCOMP_VOHSMRCOMP_VOL

    M_ODT1

    SMRCOMP#

    M_ODT3

    M_ODT0

    M_ODT2

    SMRCOMP

    +DDR_MCH_REF

    SMRCOMP_VOL

    MCH_SSCDREFCLKMCH_SSCDREFCLK#

    CLK_MCH_DREFCLKCLK_MCH_DREFCLK#

    CFG7

    CFG5

    CFG13

    CFG9

    CFG16

    CFG19

    CFG12

    CFG20

    MCH_CLKSEL0MCH_CLKSEL1MCH_CLKSEL2

    MCH_ICH_SYNC#CLKMCHREQ#

    H_DPRSTP#

    DPRSLPVR

    PM_EXTTS#1

    PM_BMBUSY#

    THERMTRIP#

    PM_EXTTS#0

    PLT_RST#_R

    CL_CLK0CL_DATA0

    CL_RST#

    H_SCOMP#

    H_DSTBP#0

    H_DSTBN#1

    H_D#39

    H_D#37

    H_D#34

    H_D#22

    H_D#12H_D#11

    H_ADSTB#0

    H_A#24

    H_A#10

    H_RS#0

    H_DSTBN#0H_D#58

    H_D#54

    H_D#4

    H_D#13

    H_D#20

    H_ADSTB#1

    H_A#7

    H_A#3

    H_A#11

    H_DSTBP#2

    H_D#6

    H_D#25

    H_D#1

    H_A#16

    H_REQ#0

    H_D#44

    H_A#19

    H_A#17

    H_RCOMP

    H_A#35

    H_DSTBP#1

    H_D#43

    H_D#35

    H_REQ#3

    H_BNR#

    H_A#13

    H_CPUSLP#

    H_SWNG

    H_HITM#

    H_DSTBN#3

    H_DINV#1

    H_D#62

    H_D#57H_D#56

    H_D#60

    H_A#14

    H_RCOMP

    H_VREF

    H_HIT#

    H_D#38

    H_D#17

    H_A#31

    H_DPWR#

    H_D#32

    H_D#50

    H_D#10

    H_A#20

    H_A#12

    H_A#33

    H_DSTBP#3

    H_DINV#3

    H_D#59

    H_D#5

    H_D#33

    H_REQ#4

    H_DEFER#

    H_D#55

    H_D#47

    H_D#45

    H_D#28H_D#27

    H_D#19

    H_D#16

    CLK_MCH_BCLK#

    H_A#9

    H_A#6

    H_D#49

    H_D#15

    H_D#40

    H_REQ#2

    H_D#0

    H_BR0#

    H_A#27

    H_A#22

    H_A#15

    H_A#34

    H_A#32

    H_REQ#1

    H_LOCK#

    H_DRDY#

    H_DINV#0

    H_D#61

    H_D#26

    H_D#23

    H_A#8

    H_A#25

    H_RS#2

    H_D#7

    H_D#14

    H_D#8

    H_D#30

    CLK_MCH_BCLK

    H_A#28

    H_RS#1

    H_TRDY#

    H_DSTBN#2

    H_D#63

    H_D#52

    H_D#48

    H_D#36

    H_D#31

    H_D#29

    H_A#4

    H_A#30H_A#29

    H_DINV#2

    H_D#41

    H_D#24

    H_D#21

    H_D#18

    H_D#9

    H_BPRI#

    H_ADS#

    H_A#5

    H_A#23

    H_D#53

    H_D#46

    H_D#42

    H_DBSY#

    H_A#21

    H_A#18

    H_SCOMP

    H_D#51

    H_D#3H_D#2

    H_A#26

    H_RESET#

    DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

    DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

    DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

    DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

    CL_VREF CL_VREF

    PM_POK_R

    PM_POK_R

    M_PWROK

    SMRCOMP_VOH

    M_CLK_DDR#3

    +DDR_MCH_REF

    CLK_MCH_DREFCLK

    CLK_MCH_DREFCLK#

    MCH_SSCDREFCLK

    MCH_SSCDREFCLK#

    H_D#[0..63]5

    H_CPUSLP#5

    H_DINV#0 5H_DINV#1 5H_DINV#2 5H_DINV#3 5

    H_DSTBN#0 5H_DSTBN#1 5H_DSTBN#2 5H_DSTBN#3 5

    H_DSTBP#0 5H_DSTBP#1 5H_DSTBP#2 5H_DSTBP#3 5

    DDR_CKE0_DIMMA 13DDR_CKE1_DIMMA 13DDR_CKE2_DIMMB 14DDR_CKE3_DIMMB 14

    DDR_CS0_DIMMA# 13DDR_CS1_DIMMA# 13DDR_CS2_DIMMB# 14DDR_CS3_DIMMB# 14

    CLK_MCH_3GPLL 16CLK_MCH_3GPLL# 16

    PLT_RST#17,19,22,24,28,29,34

    H_A#[3..35] 4

    H_ADS# 4

    H_ADSTB#1 4H_ADSTB#0 4

    H_BPRI# 4H_BNR# 4

    H_DEFER# 4H_BR0# 4

    H_DBSY# 4CLK_MCH_BCLK 16CLK_MCH_BCLK# 16H_DPWR# 5H_DRDY# 4H_HIT# 4H_HITM# 4H_LOCK# 4H_TRDY# 4

    M_CLK_DDR0 13M_CLK_DDR1 13M_CLK_DDR2 14M_CLK_DDR3 14

    M_CLK_DDR#0 13M_CLK_DDR#1 13M_CLK_DDR#2 14

    M_ODT0 13M_ODT1 13M_ODT2 14M_ODT3 14

    MCH_SSCDREFCLK 16MCH_SSCDREFCLK# 16

    MCH_CLKSEL016MCH_CLKSEL116MCH_CLKSEL216

    CFG59

    CFG99

    CFG79

    CFG139CFG129

    CFG169

    CFG209CFG199

    DMI_TXP0 19

    DMI_RXN0 19

    DMI_RXP0 19

    DMI_TXN0 19

    CLKMCHREQ# 16MCH_ICH_SYNC# 19

    PM_BMBUSY#19

    DPRSLPVR19,49

    H_DPRSTP#5,18,49PM_EXTTS#013

    CL_CLK0 19CL_DATA0 19

    H_RS#2 4

    H_REQ#3 4

    H_RS#1 4

    H_REQ#2 4

    H_RS#0 4

    H_REQ#1 4

    H_REQ#4 4

    H_REQ#0 4

    DMI_TXN1 19DMI_TXN2 19DMI_TXN3 19

    DMI_TXP1 19DMI_TXP2 19DMI_TXP3 19

    DMI_RXN1 19DMI_RXN2 19DMI_RXN3 19

    DMI_RXP1 19DMI_RXP2 19DMI_RXP3 19

    PM_EXTTS#114

    PM_PWROK19,29

    CFG89

    CLK_MCH_DREFCLK 16CLK_MCH_DREFCLK# 16

    H_THERMTRIP#4,18

    DDR_A_MA1413DDR_B_MA1414

    CL_RST# 19M_PWROK 19

    VGATE19,29,49

    M_CLK_DDR#3 14

    H_RESET#4

    +VCCP+VCCP

    +VCCP

    +3VS

    +1.8V

    +1.8V

    +1.25VM_AXD

    +1.8V

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE(1/6)-AGTL+/DMI/DDR2

    Custom

    7 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Layout Note:H_RCOMP / H_VREF / H_SWNG

    trace width and spacing is 10/20

    NA lead free

    Near B3 pinwithin 100 mils from NB

    layout note: Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

    For Calero: 80.6ohm For Crestline: 20ohm

    12 mil

    Layout Note: +DDR_MCH_REFtrace width andspacing is 20/20.

    close to NB

    Compal Electronics, Inc.

    R77

    20K_0402_5%

    1

    2

    R333

    1K_0402_1%

    1

    2

    R

    3

    2

    3

    1

    0

    0

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R

    3

    2

    5

    5

    4

    .

    9

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R679 0_0402_5% VGA@ 12

    C

    4

    0

    4

    0

    .

    0

    1

    U

    _

    0

    4

    0

    2

    _

    2

    5

    V

    7

    K

    ~

    N

    1

    2

    T16 PAD

    T38PAD

    R111 100_0402_5%

    1 2

    R431K_0402_1%

    1

    2

    C

    3

    9

    8

    2

    .

    2

    U

    _

    0

    6

    0

    3

    _

    1

    0

    6

    K

    1

    2

    T41 PADC

    4

    0

    3

    2

    .

    2

    U

    _

    0

    6

    0

    3

    _

    1

    0

    6

    K

    1

    2

    R84

    0_0402_5%

    1

    2

    R678 0_0402_5% VGA@ 12

    R680 0_0402_5% VGA@ 12

    R3323.01K_0402_1%

    1

    2

    R328 20_0402_1%

    12

    T12 PADT42 PAD

    R681 0_0402_5% VGA@ 12

    R

    4

    5

    1

    K

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R100

    1K_0402_1%

    1

    2

    T39PAD

    R329 20_0402_1%

    12

    R82

    10K_0402_5%

    12

    T37PAD

    R56 0_0402_5%12

    R102 0_0402_5%12

    R

    3

    2

    6

    5

    4

    .

    9

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    T5PAD

    C

    3

    8

    6

    0

    .

    1

    U

    _

    0

    4

    0

    2

    _

    1

    6

    V

    4

    Z

    ~

    N

    1

    2

    R331

    1K_0402_1%

    1

    2

    C

    3

    9

    1

    0.1U_0402_16V4Z~N

    1

    2

    T40PAD

    H

    O

    S

    T

    U4A

    CRESTLINE_1p0 UMA@

    H_A#_10 G17H_A#_11 C14H_A#_12 K16H_A#_13 B13H_A#_14 L16H_A#_15 J17H_A#_16 B14H_A#_17 K19H_A#_18 P15H_A#_19 R17H_A#_20 B16H_A#_21 H20H_A#_22 L19H_A#_23 D17H_A#_24 M17H_A#_25 N16H_A#_26 J19H_A#_27 B18H_A#_28 E19H_A#_29 B17

    H_A#_3 J13

    H_A#_30 B15H_A#_31 E17

    H_A#_4 B11H_A#_5 C11H_A#_6 M11H_A#_7 C15H_A#_8 F16H_A#_9 L13

    H_ADS# G12H_ADSTB#_0 H17H_ADSTB#_1 G20

    H_BNR# C8H_BPRI# E8

    H_BREQ# F12

    HPLL_CLK# AM7

    H_CPURST#B6

    HPLL_CLK AM5

    H_D#_0E2

    H_REQ#_2 A11H_REQ#_3 H13

    H_D#_1G2

    H_D#_10M10

    H_D#_20M3

    H_D#_30W3

    H_D#_40AB2

    H_D#_50AJ14

    H_D#_60AE5

    H_D#_8N8H_D#_9H2

    H_DBSY# C10

    H_D#_11N12H_D#_12N9H_D#_13H5H_D#_14P13H_D#_15K9H_D#_16M2H_D#_17W10H_D#_18Y8H_D#_19V4

    H_D#_2G7

    H_D#_21J1H_D#_22N5H_D#_23N3H_D#_24W6H_D#_25W9H_D#_26N2H_D#_27Y7H_D#_28Y9H_D#_29P4

    H_D#_3M6

    H_D#_31N1H_D#_32AD12H_D#_33AE3H_D#_34AD9H_D#_35AC9H_D#_36AC7H_D#_37AC14H_D#_38AD11H_D#_39AC11

    H_D#_4H7

    H_D#_41AD7H_D#_42AB1H_D#_43Y3H_D#_44AC6H_D#_45AE2H_D#_46AC5H_D#_47AG3H_D#_48AJ9H_D#_49AH8

    H_D#_5H3

    H_D#_51AE9H_D#_52AE11H_D#_53AH12H_D#_54AJ5H_D#_55AH5H_D#_56AJ6H_D#_57AE7H_D#_58AJ7H_D#_59AJ2

    H_D#_6G4

    H_D#_61AJ3H_D#_62AH2H_D#_63AH13

    H_D#_7F3

    H_DEFER# D6

    H_DINV#_0 K5H_DINV#_1 L2H_DINV#_2 AD13H_DINV#_3 AE13

    H_DPWR# H8H_DRDY# K7

    H_DSTBN#_0 M7H_DSTBN#_1 K3H_DSTBN#_2 AD2H_DSTBN#_3 AH11

    H_DSTBP#_0 L7H_DSTBP#_1 K2H_DSTBP#_2 AC2H_DSTBP#_3 AJ10

    H_SCOMPW1

    H_AVREFB9H_DVREFA9

    H_TRDY# B7

    H_HIT# E4H_HITM# C6H_LOCK# G10

    H_REQ#_0 M14H_REQ#_1 E13

    H_REQ#_4 B12

    H_A#_32 C18H_A#_33 A19H_A#_34 B19H_A#_35 N19

    H_SWINGB3

    H_CPUSLP#E5

    H_RCOMPC2

    H_RS#_0 E12H_RS#_1 D7H_RS#_2 D8

    H_SCOMP#W2

    R99392_0402_1%

    1

    2

    R

    4

    6

    2

    K

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    R

    3

    2

    2

    2

    2

    1

    _

    0

    6

    0

    3

    _

    1

    %

    1

    2

    C1810.1U_0402_16V4Z~N

    1

    2

    T10PAD

    R421K_0402_1%

    1

    2

    C

    6

    6

    0

    .

    1

    U

    _

    0

    4

    0

    2

    _

    1

    6

    V

    4

    Z

    ~

    N

    1

    2

    R83

    10K_0402_5%

    12

    T9PADT8PAD

    PM

    M

    I

    S

    C

    NC

    D

    D

    R

    M

    U

    X

    I

    N

    G

    C

    L

    K

    D

    M

    I

    CFGRSVD

    G

    R

    A

    P

    H

    I

    C

    S

    V

    I

    D

    M

    E

    U4B

    CRESTLINE_1p0 UMA@

    SM_CK_0 AV29SM_CK_1 BB23

    RSVD28BF23

    SM_CK_3 BA25

    SM_CK#_0 AW30SM_CK#_1 BA23

    RSVD29BG23

    SM_CK#_3 AW25

    SM_CKE_0 BE29SM_CKE_1 AY32SM_CKE_3 BD39SM_CKE_4 BG37

    SM_CS#_0 BG20SM_CS#_1 BK16SM_CS#_2 BG16SM_CS#_3 BE13

    RSVD34BH39

    SM_ODT_0 BH18SM_ODT_1 BJ15SM_ODT_2 BJ14SM_ODT_3 BE16

    SM_RCOMP BL15SM_RCOMP# BK14

    SM_VREF_0 AR49SM_VREF_1 AW4

    CFG_18L32CFG_19N33

    CFG_2N24

    CFG_0P27CFG_1N27

    CFG_20L35

    CFG_3C21CFG_4C23CFG_5F23CFG_6N23CFG_7G23CFG_8J20CFG_9C20CFG_10R24CFG_11L23CFG_12J23CFG_13E23CFG_14E20CFG_15K23CFG_16M20CFG_17M24

    PM_BM_BUSY#G41

    PM_EXT_TS#_0L36PM_EXT_TS#_1J36PWROKAW49RSTIN#AV20

    DPLL_REF_CLK B42DPLL_REF_CLK# C42

    DPLL_REF_SSCLK H48DPLL_REF_SSCLK# H47

    DMI_RXN_0 AN47DMI_RXN_1 AJ38DMI_RXN_2 AN42DMI_RXN_3 AN46

    DMI_RXP_0 AM47DMI_RXP_1 AJ39DMI_RXP_2 AN41DMI_RXP_3 AN45

    DMI_TXN_0 AJ46DMI_TXN_1 AJ41DMI_TXN_2 AM40DMI_TXN_3 AM44

    DMI_TXP_0 AJ47DMI_TXP_1 AJ42DMI_TXP_2 AM39DMI_TXP_3 AM43

    RSVD10AR37

    RSVD12AL36RSVD11AM36

    RSVD13AM37

    RSVD22BJ20RSVD23BK22RSVD24BF19RSVD25BH20RSVD26BK18

    PM_DPRSTP#L39

    SM_CK_4 AV23

    SM_CK#_4 AW23

    RSVD30BC23RSVD31BD24

    RSVD35AW20RSVD36BK20

    RSVD5AR12RSVD6AR13RSVD7AM12RSVD8AN13

    RSVD1P36RSVD2P37RSVD3R35RSVD4N35

    GFX_VID_0 E35GFX_VID_1 A39GFX_VID_2 C38GFX_VID_3 B39

    GFX_VR_EN E36

    RSVD27BJ18

    SM_RCOMP_VOH BK31SM_RCOMP_VOL BL31

    THERMTRIP#N20DPRSLPVRG36

    RSVD9J12

    CL_CLK AM49CL_DATA AK50

    CL_PWROK AT43CL_RST# AN49CL_VREF AM50

    RSVD37C48RSVD38D47RSVD39B44RSVD40C44

    RSVD32BJ29RSVD33BE24

    RSVD21B51

    NC_1BJ51NC_2BK51NC_3BK50NC_4BL50NC_5BL49NC_6BL3NC_7BL2NC_8BK1NC_9BJ1NC_10E1NC_11A5NC_12C51NC_13B50NC_14A50NC_15A49

    SDVO_CTRL_CLK H35SDVO_CTRL_DATA K36

    CLK_REQ# G39

    RSVD14D20

    ICH_SYNC# G40

    RSVD20H10

    RSVD41A35RSVD42B37RSVD43B36RSVD44B34RSVD45C34

    PEG_CLK# K45PEG_CLK K44

    TEST_1 A37NC_16BK2 TEST_2 R32

    R101 0_0402_5%@12

    R

    3

    2

    4

    2

    4

    .

    9

    _

    0

    4

    0

    2

    _

    1

    %

    1

    2

    T4PAD

    C

    4

    0

    0

    0

    .

    0

    1

    U

    _

    0

    4

    0

    2

    _

    2

    5

    V

    7

    K

    ~

    N

    1

    2

    T11 PAD

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    DDR_B_DQS#6

    DDR_B_D63

    DDR_B_D48

    DDR_A_MA8

    DDR_A_MA5

    DDR_A_DQS#1

    DDR_A_CAS#

    DDR_A_BS0

    DDR_A_D6

    DDR_A_D52

    DDR_A_D35

    DDR_A_D27DDR_A_D26

    DDR_A_D16DDR_B_DQS0

    DDR_B_DM5

    DDR_B_D60

    DDR_B_D53

    DDR_B_D20

    DDR_B_D17

    DDR_B_D11DDR_B_D10

    DDR_A_MA12

    DDR_A_DQS#5

    DDR_A_DM7

    DDR_A_D55

    DDR_A_D5

    DDR_A_D45

    DDR_A_D29

    DDR_A_D1

    DDR_B_DQS7

    DDR_B_CAS#

    DDR_B_D62

    DDR_B_D19

    DDR_A_MA13

    DDR_A_DQS5

    DDR_A_DM6

    DDR_A_BS1

    DDR_A_D48

    DDR_A_D44

    DDR_A_D20

    DDR_A_D14

    DDR_B_MA5

    DDR_B_DQS#0

    DDR_B_BS0

    DDR_B_D50

    DDR_B_D41

    DDR_B_D23

    DDR_A_D47

    DDR_A_D39

    DDR_A_D31

    DDR_B_WE#

    DDR_B_MA1

    DDR_B_DM2

    DDR_B_DM0

    DDR_B_D33

    DDR_B_D24

    DDR_A_MA4

    DDR_A_DQS7

    DDR_A_D40

    DDR_A_D38DDR_A_D37

    DDR_A_D2

    DDR_B_MA7

    DDR_B_MA13

    DDR_B_D55

    DDR_B_D32

    DDR_B_D29DDR_B_D28

    DDR_B_D21

    DDR_A_MA11

    DDR_A_DQS#4

    DDR_A_DQS#0

    DDR_A_DM5

    DDR_A_BS2

    DDR_A_D63

    DDR_A_D50

    DDR_A_D19

    DDR_A_D17

    DDR_B_D8

    DDR_B_D61

    DDR_A_DQS4

    DDR_A_DM4

    DDR_A_D62

    DDR_A_D54

    DDR_A_D36

    DDR_A_D11

    DDR_B_DQS#5

    DDR_B_DQS#3

    DDR_B_DQS4

    DDR_B_BS2

    DDR_B_D54

    DDR_B_D52

    DDR_B_D25

    DDR_A_MA6

    DDR_A_MA2

    DDR_A_D9

    DDR_A_D4

    SB_RCVEN#

    DDR_B_MA8

    DDR_B_DQS6DDR_B_DQS5

    DDR_B_DM4DDR_B_DM3

    DDR_B_D5

    DDR_B_D34

    DDR_B_D14

    DDR_B_D0

    DDR_A_MA3

    DDR_A_MA0

    DDR_A_D34

    DDR_A_D18

    DDR_B_MA2

    DDR_B_MA10DDR_B_D42

    DDR_B_D39DDR_B_D38

    DDR_B_D36

    DDR_A_RAS#

    DDR_A_MA10

    DDR_A_DQS#3

    DDR_A_D60

    DDR_A_D46

    DDR_A_D42

    DDR_A_D28

    DDR_B_MA4

    DDR_B_D7DDR_B_D6

    DDR_B_D46

    DDR_B_D30

    DDR_B_D18DDR_A_DQS3

    DDR_A_DQS0

    DDR_A_DM0

    DDR_A_D59DDR_A_D58

    DDR_A_D15

    DDR_B_DM6

    DDR_B_D57

    DDR_B_D4

    DDR_B_D35

    DDR_B_D27

    DDR_B_D2DDR_B_D1

    DDR_A_MA1

    DDR_A_D43

    DDR_A_D41

    DDR_A_D24

    DDR_B_MA9

    DDR_B_MA12DDR_B_MA11

    DDR_B_DQS3DDR_B_DQS2

    DDR_B_DM1

    DDR_B_D56

    DDR_B_D37

    DDR_B_D16

    DDR_B_D12

    DDR_A_WE#

    DDR_A_DQS1

    DDR_A_D51

    DDR_A_D22

    DDR_A_D12

    DDR_A_D0

    DDR_B_DQS#2DDR_B_DQS#1

    DDR_B_D59

    DDR_B_D51

    DDR_B_D47

    DDR_A_MA9

    DDR_A_DQS#2

    DDR_A_DQS2

    DDR_A_D7

    DDR_A_D61

    DDR_A_D56

    DDR_A_D32

    DDR_A_D30

    DDR_A_D21

    DDR_B_RAS#

    DDR_B_BS1

    DDR_B_D9

    DDR_B_D45

    DDR_B_D43

    DDR_B_D40

    DDR_B_D15

    DDR_A_DQS#6

    DDR_A_DM2

    DDR_A_D53

    DDR_A_D49

    DDR_A_D10

    DDR_B_MA0

    DDR_B_DQS#7

    DDR_B_D58

    DDR_B_D44

    DDR_B_D3

    DDR_B_D13

    DDR_A_MA7

    DDR_A_DQS#7

    DDR_A_DQS6

    DDR_A_DM3

    DDR_A_DM1DDR_A_D8

    DDR_A_D57

    DDR_B_MA6

    DDR_B_MA3

    DDR_B_DQS#4

    DDR_B_DQS1

    DDR_B_DM7

    DDR_B_D49

    DDR_B_D31

    DDR_B_D26

    DDR_B_D22

    SA_RCVEN#

    DDR_A_D33

    DDR_A_D3

    DDR_A_D25

    DDR_A_D23

    DDR_A_D13

    DDR_A_BS#0 13DDR_A_BS#1 13DDR_A_BS#2 13

    DDR_A_DQS[0..7] 13

    DDR_A_DQS#[0..7] 13

    DDR_A_MA[0..13] 13

    DDR_A_RAS# 13

    DDR_A_D[0..63]13

    DDR_B_BS#0 14DDR_B_BS#1 14DDR_B_BS#2 14

    DDR_B_DM[0..7] 14

    DDR_B_DQS[0..7] 14

    DDR_B_DQS#[0..7] 14

    DDR_B_MA[0..13] 14

    DDR_B_RAS# 14

    DDR_B_D[0..63]14

    DDR_A_DM[0..7] 13DDR_A_CAS# 13 DDR_B_CAS# 14

    DDR_A_WE# 13DDR_B_WE# 14

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE((2/6)-DDR2 A/B CH

    Custom

    8 49Thursday, January 10, 2008

    2007/1/15 2008/1/15Compal Electronics, Inc.

    D

    D

    R

    S

    Y

    S

    T

    E

    M

    M

    E

    M

    O

    R

    Y

    A

    U4D

    CRESTLINE_1p0

    SA_DQ_0AR43SA_DQ_1AW44

    SA_DQ_10BG47SA_DQ_11BJ45SA_DQ_12BB47SA_DQ_13BG50SA_DQ_14BH49SA_DQ_15BE45SA_DQ_16AW43SA_DQ_17BE44SA_DQ_18BG42SA_DQ_19BE40

    SA_DQ_2BA45

    SA_DQ_20BF44SA_DQ_21BH45SA_DQ_22BG40SA_DQ_23BF40SA_DQ_24AR40SA_DQ_25AW40SA_DQ_26AT39SA_DQ_27AW36SA_DQ_28AW41SA_DQ_29AY41

    SA_DQ_3AY46

    SA_DQ_30AV38SA_DQ_31AT38SA_DQ_32AV13SA_DQ_33AT13SA_DQ_34AW11SA_DQ_35AV11SA_DQ_36AU15SA_DQ_37AT11SA_DQ_38BA13SA_DQ_39BA11

    SA_DQ_4AR41

    SA_DQ_40BE10SA_DQ_41BD10SA_DQ_42BD8SA_DQ_43AY9SA_DQ_44BG10SA_DQ_45AW9SA_DQ_46BD7SA_DQ_47BB9SA_DQ_48BB5SA_DQ_49AY7

    SA_DQ_5AR45

    SA_DQ_50AT5SA_DQ_51AT7SA_DQ_52AY6SA_DQ_53BB7SA_DQ_54AR5SA_DQ_55AR8SA_DQ_56AR9SA_DQ_57AN3SA_DQ_58AM8SA_DQ_59AN10

    SA_DQ_6AT42

    SA_DQ_60AT9SA_DQ_61AN9SA_DQ_62AM9SA_DQ_63AN11

    SA_DQ_7AW47SA_DQ_8BB45SA_DQ_9BF48

    SA_BS_0 BB19SA_BS_1 BK19SA_BS_2 BF29

    SA_CAS# BL17

    SA_DM_0 AT45SA_DM_1 BD44SA_DM_2 BD42SA_DM_3 AW38SA_DM_4 AW13SA_DM_5 BG8SA_DM_6 AY5

    SA_DQS_0 AT46SA_DQS_1 BE48SA_DQS_2 BB43SA_DQS_3 BC37SA_DQS_4 BB16SA_DQS_5 BH6SA_DQS_6 BB2SA_DQS_7 AP3

    SA_DM_7 AN6

    SA_DQS#_0 AT47SA_DQS#_1 BD47SA_DQS#_2 BC41SA_DQS#_3 BA37SA_DQS#_4 BA16SA_DQS#_5 BH7SA_DQS#_6 BC1SA_DQS#_7 AP2

    SA_MA_0 BJ19SA_MA_1 BD20

    SA_MA_10 BC19SA_MA_11 BE28SA_MA_12 BG30SA_MA_13 BJ16

    SA_MA_2 BK27SA_MA_3 BH28SA_MA_4 BL24SA_MA_5 BK28SA_MA_6 BJ27SA_MA_7 BJ25SA_MA_8 BL28SA_MA_9 BA28

    SA_RAS# BE18SA_RCVEN# AY20

    SA_WE# BA19T6

    T7

    D

    D

    R

    S

    Y

    S

    T

    E

    M

    M

    E

    M

    O

    R

    Y

    B

    U4E

    CRESTLINE_1p0

    SB_DQ_0AP49SB_DQ_1AR51

    SB_DQ_10BA49SB_DQ_11BE50SB_DQ_12BA51SB_DQ_13AY49SB_DQ_14BF50SB_DQ_15BF49SB_DQ_16BJ50SB_DQ_17BJ44SB_DQ_18BJ43SB_DQ_19BL43

    SB_DQ_2AW50

    SB_DQ_20BK47SB_DQ_21BK49SB_DQ_22BK43SB_DQ_23BK42SB_DQ_24BJ41SB_DQ_25BL41SB_DQ_26BJ37SB_DQ_27BJ36SB_DQ_28BK41SB_DQ_29BJ40

    SB_DQ_3AW51

    SB_DQ_30BL35SB_DQ_31BK37SB_DQ_32BK13SB_DQ_33BE11SB_DQ_34BK11SB_DQ_35BC11SB_DQ_36BC13SB_DQ_37BE12SB_DQ_38BC12SB_DQ_39BG12

    SB_DQ_4AN51

    SB_DQ_40BJ10SB_DQ_41BL9SB_DQ_42BK5SB_DQ_43BL5SB_DQ_44BK9SB_DQ_45BK10SB_DQ_46BJ8SB_DQ_47BJ6SB_DQ_48BF4SB_DQ_49BH5

    SB_DQ_5AN50

    SB_DQ_50BG1SB_DQ_51BC2SB_DQ_52BK3SB_DQ_53BE4SB_DQ_54BD3SB_DQ_55BJ2SB_DQ_56BA3SB_DQ_57BB3SB_DQ_58AR1SB_DQ_59AT3

    SB_DQ_6AV50

    SB_DQ_60AY2SB_DQ_61AY3SB_DQ_62AU2SB_DQ_63AT2

    SB_DQ_7AV49SB_DQ_8BA50SB_DQ_9BB50

    SB_BS_0 AY17SB_BS_1 BG18SB_BS_2 BG36

    SB_CAS# BE17

    SB_DM_0 AR50SB_DM_1 BD49SB_DM_2 BK45SB_DM_3 BL39SB_DM_4 BH12SB_DM_5 BJ7SB_DM_6 BF3SB_DM_7 AW2

    SB_DQS_0 AT50SB_DQS_1 BD50SB_DQS_2 BK46SB_DQS_3 BK39SB_DQS_4 BJ12SB_DQS_5 BL7SB_DQS_6 BE2SB_DQS_7 AV2

    SB_DQS#_0 AU50SB_DQS#_1 BC50SB_DQS#_2 BL45SB_DQS#_3 BK38SB_DQS#_4 BK12SB_DQS#_5 BK7SB_DQS#_6 BF2SB_DQS#_7 AV3

    SB_MA_0 BC18SB_MA_1 BG28

    SB_MA_10 BG17SB_MA_11 BE37SB_MA_12 BA39SB_MA_13 BG13

    SB_MA_2 BG25SB_MA_3 AW17SB_MA_4 BF25SB_MA_5 BE25SB_MA_6 BA29SB_MA_7 BC28SB_MA_8 AY28SB_MA_9 BD37

    SB_RAS# AV16SB_RCVEN# AY18

    SB_WE# BC17

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    3VDDCCL3VDDCDA

    BIA_PWMGMCH_ENBKL

    GMCH_LVDDEN

    GMCH_EDID_CLK_LCDGMCH_EDID_DAT_LCD

    PEGCOMPCTRL_CLKCTRL_DATA

    CRT_B

    GMCH_LVDSA1+GMCH_LVDSA2+

    GMCH_LVDSA0+

    GMCH_LVDSA1-GMCH_LVDSA2-

    GMCH_LVDSA0-

    GMCH_LVDSAC-GMCH_LVDSAC+

    CRT_GCRT_R

    CRT_HSYNC

    CRT_VSYNC

    GMCH_EDID_DAT_LCD

    GMCH_EDID_CLK_LCD

    CTRL_CLK

    CTRL_DATA

    PEG_NRX_GTX_P2PEG_NRX_GTX_P3

    PEG_NRX_GTX_P5PEG_NRX_GTX_P6

    PEG_NRX_GTX_P8PEG_NRX_GTX_P9

    PEG_NRX_GTX_P11PEG_NRX_GTX_P12

    PEG_NRX_GTX_P14PEG_NRX_GTX_P15

    PEG_NRX_GTX_P0PEG_NRX_GTX_P1

    PEG_NRX_GTX_P4

    PEG_NRX_GTX_P7

    PEG_NRX_GTX_P10

    PEG_NRX_GTX_P13

    PEG_TXP15PEG_TXP14PEG_TXP13PEG_TXP12

    PEG_TXP8PEG_TXP9

    PEG_TXP4PEG_TXP5PEG_TXP6

    PEG_TXP10PEG_TXP11

    PEG_TXP7

    PEG_TXP0PEG_TXP1PEG_TXP2PEG_TXP3

    PEG_NTX_GRX_P10

    PEG_NTX_GRX_P4PEG_NTX_GRX_P5

    PEG_NTX_GRX_P7

    PEG_NTX_GRX_P2

    PEG_NTX_GRX_P6

    PEG_NTX_GRX_P3

    PEG_NTX_GRX_P11

    PEG_NTX_GRX_P14

    PEG_NTX_GRX_P12

    PEG_NTX_GRX_N4

    PEG_NTX_GRX_P9

    PEG_NTX_GRX_P13

    PEG_NTX_GRX_P1PEG_NTX_GRX_P0

    PEG_NTX_GRX_P8

    PEG_NTX_GRX_N3

    PEG_NTX_GRX_N12

    PEG_NTX_GRX_N10

    PEG_NTX_GRX_N7

    PEG_NTX_GRX_P15

    PEG_NTX_GRX_N9

    PEG_NTX_GRX_N6

    PEG_NTX_GRX_N0PEG_NTX_GRX_N1

    PEG_TXN5

    PEG_NTX_GRX_N15PEG_NTX_GRX_N14

    PEG_NTX_GRX_N2

    PEG_NTX_GRX_N5

    PEG_TXN11 PEG_NTX_GRX_N11PEG_TXN12PEG_TXN13

    PEG_TXN10

    PEG_NTX_GRX_N8

    PEG_NTX_GRX_N13PEG_TXN14

    PEG_TXN4

    PEG_TXN6

    PEG_TXN1PEG_TXN0

    PEG_TXN15

    PEG_TXN7PEG_TXN8

    PEG_TXN2PEG_TXN3

    PEG_TXN9

    PEG_NRX_GTX_N10

    PEG_NRX_GTX_N8

    PEG_NRX_GTX_N2

    PEG_NRX_GTX_N0

    PEG_NRX_GTX_N4

    PEG_NRX_GTX_N9

    PEG_NRX_GTX_N6

    PEG_NRX_GTX_N3

    PEG_NRX_GTX_N12

    PEG_NRX_GTX_N7

    PEG_NRX_GTX_N15

    PEG_NRX_GTX_N13PEG_NRX_GTX_N14

    PEG_NRX_GTX_N1

    PEG_NRX_GTX_N11

    PEG_NRX_GTX_N5

    CFG137

    CFG127

    CFG97

    CFG77

    CFG207

    CFG197

    CFG167

    CFG87

    GMCH_EDID_DAT_LCD15

    CFG57

    BIA_PWM15GMCH_ENBKL15

    GMCH_LVDDEN15

    GMCH_LVDSAC+15

    GMCH_LVDSA0+15GMCH_LVDSA1+15GMCH_LVDSA2+15

    GMCH_LVDSA0-15GMCH_LVDSA1-15GMCH_LVDSA2-15

    GMCH_LVDSAC-15

    CRT_VSYNC15

    CRT_HSYNC15

    GMCH_EDID_CLK_LCD15

    PEG_NRX_GTX_P[0..15] 34

    PEG_NRX_GTX_N[0..15] 34

    PEG_NTX_GRX_N[0..15] 34

    PEG_NTX_GRX_P[0..15] 34

    CRT_B15CRT_G15CRT_R15

    3VDDCCL153VDDCDA15

    +3VS

    +VCCP

    +3VS

    +3VS

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE((3/6)-VGA/LVDS/TV

    Custom

    9 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    CFG9

    0 = Normal mode1 = Low Power mode

    (PCIE Graphics Lane Reversal)

    CFG[2:0] FSB Freq select

    Reserved

    Reserved

    ReservedCFG[15:14]

    Strap Pin Table

    CFG[19:18] have internal pull downCFG[17:3] have internal pull up

    ReservedCFG[18:17]

    (Lane number in Order)

    Others = Reserved011 = FSB 667MHz010 = FSB 800MHz

    11 = Normal Operation10 = All Z Mode Enabled01 = XOR Mode Enabled

    *

    1 = Reverse Lane

    0 = Reverse Lane

    SDVO_CTRLDATA

    1 = Enabled

    1 = SDVO Device Present

    0 = Normal Operation

    0 = No SDVO Device Present

    (Default)

    *

    0 = Disabled

    *

    0 = DMI x 2

    00 = Reserved

    *

    *

    *

    *

    1 = PCIE/SDVO are operating simu.0 = Only PCIE or SDVO is operational. *

    1 = Normal Operation

    1 = DMI x 4

    0 = Reserved1 = Mobile CPU

    CFG5 (DMI select)

    CFG19 (DMI Lane Reversal)

    CFG16 (FSB Dynamic ODT)

    CFG6

    CFG7 (CPU Strap)

    CFG20 (PCIE/SDVO concurrent)

    CFG[11:10]

    CFG[13:12] (XOR/ALLZ)

    CFG8 (Low power PCIE)*

    For Calero: 255ohm For Crestline:1.3kohm

    For Calero: 1.5Kohm For Crestline:2.4kohm PEGCOMP trace widthand spacing is 20/25 mils.

    Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.Compal Electronics, Inc.

    C562 0.1U_0402_16V7KVGA@1 2

    C558 0.1U_0402_16V7KVGA@1 2

    R6575_0402_1%

    1 2

    C563 0.1U_0402_16V7KVGA@1 2

    C567 0.1U_0402_16V7KVGA@1 2

    C548 0.1U_0402_16V7KVGA@1 2

    R58 4.02K_0402_1%@1 2

    R76

    0_0402_5%VGA@

    C539 0.1U_0402_16V7KVGA@1 2

    R81 10K_0402_5%UMA@1 2

    C568 0.1U_0402_16V7KVGA@1 2

    R6820_0402_5%

    VGA@

    1

    2 R6840_0402_5%

    VGA@

    1

    2

    R9524.9_0402_1%

    1 2

    C553 0.1U_0402_16V7KVGA@1 2

    R6875_0402_1%

    1 2

    C555 0.1U_0402_16V7KVGA@1 2

    R6770_0402_5%

    VGA@

    1

    2

    R6750_0402_5%

    VGA@

    1

    2

    C552 0.1U_0402_16V7KVGA@1 2

    R94 2.4K_0402_1% 12

    R483

    2.2K_0402_5%

    UMA@ 1 2

    C545 0.1U_0402_16V7KVGA@1 2

    R80 10K_0402_5%UMA@1 2

    C538 0.1U_0402_16V7KVGA@1 2

    C546 0.1U_0402_16V7KVGA@1 2

    R

    7

    4

    1

    5

    0

    _

    0

    4

    0

    2

    _

    1

    %

    U

    M

    A

    @

    1

    2

    R57 4.02K_0402_1%@1 2

    R59 4.02K_0402_1%@1 2

    C544 0.1U_0402_16V7KVGA@1 2

    C560 0.1U_0402_16V7KVGA@1 2

    C537 0.1U_0402_16V7KVGA@1 2

    R55 4.02K_0402_1%@1 2

    C565 0.1U_0402_16V7KVGA@1 2C566 0.1U_0402_16V7KVGA@1 2

    C561 0.1U_0402_16V7KVGA@1 2

    R6760_0402_5%

    VGA@

    1

    2

    R74

    0_0402_5%VGA@

    R72 4.02K_0402_1%@1 2

    C550 0.1U_0402_16V7KVGA@1 2

    R75

    0_0402_5%VGA@

    C547 0.1U_0402_16V7KVGA@1 2

    R63 4.02K_0402_1%@1 2

    LVDS

    P

    C

    I

    -

    E

    X

    P

    R

    E

    S

    S

    G

    R

    A

    P

    H

    I

    C

    S

    TVVGA

    U4C

    CRESTLINE_1p0

    PEG_COMPI N43PEG_COMPO M43

    PEG_RX#_0 J51PEG_RX#_1 L51PEG_RX#_2 N47PEG_RX#_3 T45PEG_RX#_4 T50PEG_RX#_5 U40PEG_RX#_6 Y44PEG_RX#_7 Y40PEG_RX#_8 AB51PEG_RX#_9 W49

    PEG_RX#_10 AD44PEG_RX#_11 AD40PEG_RX#_12 AG46PEG_RX#_13 AH49PEG_RX#_14 AG45PEG_RX#_15 AG41

    PEG_RX_0 J50PEG_RX_1 L50PEG_RX_2 M47PEG_RX_3 U44PEG_RX_4 T49PEG_RX_5 T41PEG_RX_6 W45PEG_RX_7 W41PEG_RX_8 AB50PEG_RX_9 Y48

    PEG_RX_10 AC45PEG_RX_11 AC41PEG_RX_12 AH47PEG_RX_13 AG49PEG_RX_14 AH45PEG_RX_15 AG42

    PEG_TX#_0 N45

    PEG_TX#_10 AC46

    PEG_TX#_3 N51PEG_TX#_4 R50PEG_TX#_5 T42PEG_TX#_6 Y43PEG_TX#_7 W46PEG_TX#_8 W38PEG_TX#_9 AD39

    PEG_TX#_1 U39

    PEG_TX#_11 AC49PEG_TX#_12 AC42PEG_TX#_13 AH39PEG_TX#_14 AE49PEG_TX#_15 AH44

    PEG_TX#_2 U47

    PEG_TX_0 M45PEG_TX_1 T38PEG_TX_2 T46PEG_TX_3 N50PEG_TX_4 R51PEG_TX_5 U43PEG_TX_6 W42PEG_TX_7 Y47PEG_TX_8 Y39PEG_TX_9 AC38

    PEG_TX_10 AD47PEG_TX_11 AC50PEG_TX_12 AD43PEG_TX_13 AG39PEG_TX_14 AE50PEG_TX_15 AH43

    L_CTRL_CLKE39L_CTRL_DATAE40L_DDC_CLKC37L_DDC_DATAD35L_VDD_ENK40

    LVDS_IBGL41LVDS_VBGL43LVDS_VREFHN41LVDS_VREFLN40LVDSA_CLK#D46LVDSA_CLKC45

    LVDSA_DATA#_0G51LVDSA_DATA#_1E51LVDSA_DATA#_2F49

    LVDSA_DATA_1E50LVDSA_DATA_2F48

    LVDSB_CLK#D44LVDSB_CLKE42

    LVDSB_DATA#_0G44LVDSB_DATA#_1B47LVDSB_DATA#_2B45

    LVDSB_DATA_1A47LVDSB_DATA_2A45

    L_BKLT_ENH39

    TVA_DACE27TVB_DACG27TVC_DACK27

    TVA_RTNF27TVB_RTNJ27TVC_RTNL27

    CRT_BLUEH32CRT_BLUE#G32

    CRT_DDC_CLKK33CRT_DDC_DATAG35

    CRT_GREENK29CRT_GREEN#J29

    CRT_HSYNCF33CRT_TVO_IREFC32

    CRT_REDF29CRT_RED#E29

    CRT_VSYNCE33

    LVDSA_DATA_0G50

    LVDSB_DATA_0E44

    L_BKLT_CTRLJ40

    TV_DCONSEL_0M35TV_DCONSEL_1P33

    R70 4.02K_0402_1%@1 2

    C564 0.1U_0402_16V7KVGA@1 2

    R

    7

    6

    1

    5

    0

    _

    0

    4

    0

    2

    _

    1

    %

    U

    M

    A

    @

    1

    2

    C549 0.1U_0402_16V7KVGA@1 2

    C542 0.1U_0402_16V7KVGA@1 2

    C559 0.1U_0402_16V7KVGA@1 2

    C543 0.1U_0402_16V7KVGA@1 2

    C540 0.1U_0402_16V7KVGA@1 2

    R73 4.02K_0402_1%@1 2

    R6775_0402_1%

    1 2

    C554 0.1U_0402_16V7KVGA@1 2

    R6830_0402_5%

    VGA@

    1

    2

    C557 0.1U_0402_16V7KVGA@1 2C556 0.1U_0402_16V7KVGA@1 2

    C551 0.1U_0402_16V7KVGA@1 2

    C541 0.1U_0402_16V7KVGA@1 2

    R66 4.02K_0402_1%@1 2

    R484

    2.2K_0402_5%

    UMA@1 2

    R334

    1.3K_0402_1%

    1

    2

    R

    7

    5

    1

    5

    0

    _

    0

    4

    0

    2

    _

    1

    %

    U

    M

    A

    @

    1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    +1.25VM_A_SM

    +V1.25VS_AXF

    +1.25VS

    +1.25VS_DMI

    +1.8V_SM_CK

    +3VS_HV

    +VCC_PEG

    +1.25VS_PEGPLL

    +1.25VS

    +1.25VM_AXD

    +1.25VM_A_SM_CK

    +3VS_PEG_BG

    +3VS

    +1.8V_TXLVDS

    +3VS+3VS_DAC_BG

    +3VS+3VS_DAC_CRT

    +3VS+3VS_TVDACA

    +3VS+3VS_TVDACB

    +3VS+3VS_TVDACC

    +1.8V

    +1.8V_LVDS

    +1.5VS

    +3VS_TVDACA

    +3VS_TVDACB

    +3VS_TVDACC

    +1.25VM_HPLL

    +1.5VS_TVDAC

    +1.8V_LVDS

    +1.5VS_QDAC

    +1.8V_TXLVDS

    +1.25VM_MPLL

    +1.25VS_DPLLB

    +1.25VM_HPLL

    +1.25VS_DPLLA

    +3VS_DAC_BG

    VCCSYNC+3VS

    +3VS_DAC_CRT

    +1.8V_TXLVDS

    +1.8V

    +1.25VM_HPLL

    +1.25VS+1.25VM_MPLL

    +1.25VS

    +VCCP

    +1.25VS_PEGPLL +1.25VS

    +1.25VS+V1.25VS_AXF

    +1.25VS+1.25VS_DMI +1.8V+1.8V_SM_CK

    +1.25VS_DPLLA

    +1.25VS_DPLLB

    +1.25VS

    +1.25VS

    +1.5VS+1.5VS_TVDAC

    +VCCP

    +3VS

    +VCCP_D

    +3VS_HV

    +VCC_PEG

    +1.25VS_PEGPLL

    +VCCP

    +1.5VS_QDAC

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE(4/6)-PWR

    Custom

    10 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    20 mils

    40 mils

    20mils

    0317 change value

    Compal Electronics, Inc.

    Take off 0ohm 0805because Layout

    C72

    1U_0603_10V4Z

    1

    2

    POWER

    C

    R

    T

    P

    L

    L

    A

    P

    E

    G

    A

    S

    M

    T

    V

    D

    T

    V

    /

    C

    R

    T

    L

    V

    D

    S

    V

    T

    T

    L

    F

    P

    E

    G

    S

    M

    C

    K

    A

    X

    D

    A

    X

    F

    V

    T

    T

    D

    M

    I

    H

    V

    A

    C

    K

    A

    L

    V

    D

    S

    U4H

    CRESTLINE_1p0 UMA@

    VTT_19 T2VTT_20 R3VTT_21 R2VTT_22 R1

    VCCD_CRTM32

    VCCA_PEG_BGK50

    VCCA_PEG_PLLU51

    VCCA_CRT_DAC_1A33VCCA_CRT_DAC_2B33

    VCCA_DPLLAB49

    VCCA_DPLLBH49

    VCCA_HPLLAL2

    VCCA_LVDSA41

    VCCA_MPLLAM2

    VCCA_TVA_DAC_1C25VCCA_TVA_DAC_2B25VCCA_TVB_DAC_1C27VCCA_TVB_DAC_2B27VCCA_TVC_DAC_1B28VCCA_TVC_DAC_2A28

    VCCD_PEG_PLLU48

    VTT_15 T7VTT_16 T6VTT_17 T5VTT_18 T3

    VTT_12 T11VTT_13 T10VTT_14 T9

    VCCSYNCJ32

    VCCD_HPLLAN2

    VTT_1 U13VTT_2 U12

    VTT_4 U9VTT_5 U8VTT_6 U7VTT_7 U5VTT_8 U3VTT_9 U2

    VTT_10 U1VTT_11 T13

    VTT_3 U11

    VCCA_SM_CK_1BC29VCCA_SM_CK_2BB29

    VCCA_DAC_BGA30

    VCCD_TVDACL29

    VTTLF1 A7VTTLF2 F2VTTLF3 AH1

    VCC_RXR_DMI_1 AH50VCC_RXR_DMI_2 AH51

    VCC_SM_CK_1 BK24VCC_SM_CK_2 BK23VCC_SM_CK_3 BJ24VCC_SM_CK_4 BJ23

    VCCD_LVDS_1J41

    VCCD_QDACN28

    VCC_AXD_2 AU28VCC_AXD_3 AU24

    VCC_AXD_5 AT25

    VCC_AXF_1 B23VCC_AXF_2 B21VCC_AXF_3 A21

    VCCA_SM_1AW18VCCA_SM_2AV19VCCA_SM_3AU19VCCA_SM_4AU18VCCA_SM_5AU17

    VCCA_SM_7AT22VCCA_SM_8AT21VCCA_SM_9AT19

    VCC_DMI AJ50

    VCC_TX_LVDS A43

    VSSA_DAC_BGB32

    VSSA_LVDSB41

    VSSA_PEG_BGK49

    VCC_HV_1 C40VCC_HV_2 B40

    VCC_PEG_1 AD51

    VCCA_SM_10AT18VCCA_SM_11AT17VCCA_SM_NCTF_1AR17VCCA_SM_NCTF_2AR16

    VCCD_LVDS_2H42

    VCC_PEG_2 W50VCC_PEG_3 W51VCC_PEG_4 V49VCC_PEG_5 V50

    VCC_AXD_NCTF AR29

    VCC_AXD_4 AT29

    VCC_AXD_6 AT30

    VCC_AXD_1 AT23

    C

    5

    6

    2.2U_0805_16V

    4Z

    1

    2

    C122

    1U_0603_10V

    4Z

    @

    1

    2

    C399

    0.1U_0402_16V

    4Z~N

    1

    2

    R64

    0_0805_5%

    1 2

    C

    3

    8

    3

    0.47U_0603_10V

    7K

    1

    2

    R109

    0_0603_5%UMA@

    12

    C97

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    C413

    0_0402_5%VGA@

    C98

    0_0402_5%VGA@

    L11

    BLM18PG181SN1D_0603

    UMA@12

    C382

    0.47U_0603_10V

    7K

    1

    2

    D7

    CH751H-40PT_SOD323-2

    2 1

    C380

    0.1U_0402_16V4Z~N

    1

    2

    C

    3

    7

    3

    4.7U_0805_10V

    4Z~N

    1

    2

    C401

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    C187

    10U_0805_10V

    4Z~NU

    MA

    @

    1

    2

    L12BLM18PG121SN1D_0603

    12

    C408

    4.7U_0805_10V

    4Z~N

    UM

    A@

    1

    2

    R53

    0_0603_5%UMA@

    12

    +C68150U_B2_6.3VM_R45M

    1

    2

    R97

    0_0805_5%

    1 2

    C63

    0.1U_0402_16V4Z~N

    1

    2

    C411

    0.1U_0402_16V

    4Z~N

    UM

    A@

    1

    2

    C174

    0.1U_0402_16V

    4Z~N

    UMA@

    1

    2

    C402

    0.1U_0402_16V

    4Z~NU

    MA

    @1

    2

    C123

    0.1U_0402_16V

    4Z~N

    1

    2

    L9

    MBK2012121YZF_0805

    12

    R62

    0_0603_5%UMA@

    12

    C141

    0_0402_5%VGA@

    C1410.1U_0402_16V4Z~N

    UMA@

    1

    2

    C173

    0.1U_0402_16V4Z~N

    UMA@1

    2

    C407

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    C1750.1U_0402_16V4Z~N

    1

    2

    +C370

    330U_V_2.5VM

    1

    2

    L10

    BLM18PG181SN1D_0603

    UMA@12

    C180

    0.1U_0402_16V

    4Z~N

    1

    2

    R71

    0_0603_5%

    12

    C114

    0.1U_0402_16V

    4Z~N

    1

    2

    C385

    0.47U_0603_10V

    7K

    1

    2

    C98

    0.1U_0402_16V

    4Z~NU

    MA

    @

    1

    2

    C406

    0_0402_5%VGA@

    R349

    0_0603_5% UMA@12

    C410

    0.1U_0402_16V

    4Z~N

    1

    2

    C179

    10U_0805_10V

    4Z~N

    1

    2

    +C417

    220U_D

    2_4VY

    _R15M

    1

    2

    R50

    0_0805_5%

    1 2

    C95

    0.1U_0402_16V

    4Z~NU

    MA

    @1

    2

    C407

    0_0402_5%VGA@

    C115

    0.022U_0402_16V

    7K~N

    1

    2

    R3300_0603_5%

    1 2

    C414

    1000P_0402_50V7K~N

    UMA@

    1

    2

    C

    3

    8

    4

    4.7U_0805_10V

    4Z~N

    1

    2

    R92

    0_0603_5%

    UMA@12

    C176

    0.1U_0402_16V

    4Z~N

    1

    2

    C834.7U_0805_6.3V6K

    1

    2

    C104

    22U_0805_6.3V

    4Z

    1

    2

    C413 1000P_0402_50V7K~N

    UMA@

    1

    2

    C113

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    R69

    0_0603_5%UMA@

    12

    C103

    1U_0402_6.3V

    4Z

    @

    1

    2

    +C191

    220U_D

    2_4VY

    _R15M

    UMA@1

    2

    U4

    CRESTLINE_1p0

    VGA@

    L1410U_FLC-453232-100K_0.25A_10%

    UMA@1 2

    C381

    10U_0805_10V4Z~N

    1

    2

    R60

    0_0805_5%

    1 2

    C395

    10U_0603_6.3V

    6M

    1

    2

    C174

    0_0402_5%VGA@

    R54

    0_0603_5%UMA@

    12

    R79

    10_0402_5%

    12

    C96

    0_0402_5%VGA@

    C182

    10U_0805_10V

    4Z~N

    UMA@1

    2

    C405

    0.1U_0402_16V

    4Z~N

    UM

    A@

    1

    2

    R327

    0_0805_5%

    1 2

    C96

    0.1U_0402_16V

    4Z~NU

    MA

    @1

    2

    C173

    0_0402_5%VGA@

    C186

    0_0603_5%VGA@

    L13

    10U_FLC-453232-100K_0.25A_10%

    UMA@1 2

    C416

    10U_0805_10V

    4Z~N

    1

    2

    +C418

    220U_D

    2_4VY

    _R15M

    UMA@

    1

    2

    C116

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    C178

    22U_0805_6.3V

    AM

    UMA@

    1

    2

    R674 0_0402_5%VGA@ 12

    C62

    10U_0805_10V4Z~N

    1

    2

    C8222U_0805_6.3V4Z

    1

    2

    R1030_0603_5%

    1 2

    R93

    0_0402_5%

    12

    R673 0_0402_5% UMA@ 12

    C394

    10U_0805_10V

    4Z~N

    1

    2

    C402

    0_0402_5%VGA@

    L29

    MBK2012121YZF_0805

    12

    C65

    0.47U_0603_10V

    7K

    1

    2

    C186

    1U_0603_10V

    4Z

    UM

    A@

    1

    2

    C397

    1U_0603_10V

    4Z

    1

    2

    C95

    0_0402_5%VGA@

    C406

    0.022U_0402_16V

    7K~N

    UM

    A@

    1

    2

    C87

    1U_0603_10V

    4Z

    1

    2

    C396

    22U_0805_6.3V

    4Z

    1

    2

    C88

    10U_0805_10V

    4Z~N

    1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    VCCSM_LF1

    VCCSM_LF7

    VCCSM_LF2VCCSM_LF3

    VCCSM_LF6

    VCCSM_LF4VCCSM_LF5

    +VCCP

    +VCCP

    +1.8V

    +VCCP

    +VCCP

    +VCCP

    +VCCP

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE((5/6)-PWR/GND

    Custom

    11 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    370mil

    160mil

    Compal Electronics, Inc.

    C102

    0.1U_0402_16V4Z~N

    1

    2

    C144

    0.22U_0402_10V4Z~N

    1

    2

    +C57

    330U_V_2.5VM

    UMA@

    1

    2

    C146

    0.47U_0402_6.3V6K

    1

    2

    C86

    0.22U_0402_10V4Z~N

    UMA@

    1

    2

    C117

    0.1U_0402_16V4Z~N

    1

    2

    C142

    0.1U_0402_16V4Z~N

    1

    2

    C164

    0.01U_0402_16V7K~N

    1

    2

    C100

    10U_0805_10V4Z~N

    UMA@

    1

    2

    +C148

    3

    3

    0

    U

    _

    V

    _

    2

    .

    5

    V

    M

    1

    2

    POWER

    V

    C

    C

    C

    O

    R

    E

    V

    C

    C

    S

    M

    V

    C

    C

    G

    F

    X

    V

    C

    C

    G

    F

    X

    N

    C

    T

    F

    V

    C

    C

    S

    M

    L

    F

    U4G

    CRESTLINE_1p0 UMA@

    VCC_5AC32

    VCC_6AK32VCC_7AJ31VCC_8AJ28VCC_9AH32VCC_10AH31VCC_11AH29VCC_12AF32

    VCC_2AT34

    VCC_4AC31

    VCC_SM_10BA35

    VCC_SM_20BF33

    VCC_SM_30BJ34

    VCC_SM_6AW35VCC_SM_7AY35VCC_SM_8BA32VCC_SM_9BA33

    VCC_SM_11BB33VCC_SM_12BC32VCC_SM_13BC33VCC_SM_14BC35VCC_SM_15BD32VCC_SM_16BD35VCC_SM_17BE32VCC_SM_18BE33VCC_SM_19BE35

    VCC_SM_2AU33

    VCC_SM_21BF34VCC_SM_22BG32VCC_SM_23BG33VCC_SM_24BG35VCC_SM_25BH32VCC_SM_26BH34VCC_SM_27BH35VCC_SM_28BJ32VCC_SM_29BJ33

    VCC_SM_3AU35

    VCC_SM_31BK32VCC_SM_32BK33VCC_SM_33BK34VCC_SM_34BK35

    VCC_AXG_NCTF_10 U17VCC_AXG_NCTF_11 U19VCC_AXG_NCTF_12 U20VCC_AXG_NCTF_13 U21VCC_AXG_NCTF_14 U23VCC_AXG_NCTF_15 U26VCC_AXG_NCTF_16 V16VCC_AXG_NCTF_17 V17VCC_AXG_NCTF_18 V19VCC_AXG_NCTF_19 V20

    VCC_AXG_NCTF_2 T18

    VCC_AXG_NCTF_20 V21VCC_AXG_NCTF_21 V23VCC_AXG_NCTF_22 V24VCC_AXG_NCTF_23 Y15VCC_AXG_NCTF_24 Y16VCC_AXG_NCTF_25 Y17VCC_AXG_NCTF_26 Y19VCC_AXG_NCTF_27 Y20VCC_AXG_NCTF_28 Y21VCC_AXG_NCTF_29 Y23

    VCC_AXG_NCTF_3 T19

    VCC_AXG_NCTF_30 Y24VCC_AXG_NCTF_31 Y26VCC_AXG_NCTF_32 Y28VCC_AXG_NCTF_33 Y29VCC_AXG_NCTF_34 AA16VCC_AXG_NCTF_35 AA17VCC_AXG_NCTF_36 AB16VCC_AXG_NCTF_37 AB19VCC_AXG_NCTF_38 AC16VCC_AXG_NCTF_39 AC17

    VCC_AXG_NCTF_4 T21

    VCC_AXG_NCTF_40 AC19VCC_AXG_NCTF_41 AD15VCC_AXG_NCTF_42 AD16VCC_AXG_NCTF_43 AD17VCC_AXG_NCTF_44 AF16VCC_AXG_NCTF_45 AF19VCC_AXG_NCTF_46 AH15VCC_AXG_NCTF_47 AH16VCC_AXG_NCTF_48 AH17VCC_AXG_NCTF_49 AH19

    VCC_AXG_NCTF_5 T22

    VCC_AXG_NCTF_50 AJ16VCC_AXG_NCTF_51 AJ17VCC_AXG_NCTF_52 AJ19VCC_AXG_NCTF_53 AK16VCC_AXG_NCTF_54 AK19VCC_AXG_NCTF_55 AL16VCC_AXG_NCTF_56 AL17VCC_AXG_NCTF_57 AL19VCC_AXG_NCTF_58 AL20VCC_AXG_NCTF_59 AL21

    VCC_AXG_NCTF_6 T23

    VCC_AXG_NCTF_60 AL23VCC_AXG_NCTF_61 AM15VCC_AXG_NCTF_62 AM16VCC_AXG_NCTF_63 AM19

    VCC_AXG_NCTF_65 AM21VCC_AXG_NCTF_66 AM23VCC_AXG_NCTF_67 AP15VCC_AXG_NCTF_68 AP16VCC_AXG_NCTF_69 AP17

    VCC_AXG_NCTF_7 T25

    VCC_AXG_NCTF_70 AP19VCC_AXG_NCTF_71 AP20VCC_AXG_NCTF_72 AP21

    VCC_AXG_NCTF_8 U15VCC_AXG_NCTF_9 U16

    VCC_SM_35BL33

    VCC_SM_4AV33VCC_SM_5AW33

    VCC_AXG_NCTF_1 T17VCC_1AT35

    VCC_SM_1AU32

    VCC_AXG_1R20VCC_AXG_2T14VCC_AXG_3W13VCC_AXG_4W14VCC_AXG_5Y12VCC_AXG_6AA20VCC_AXG_7AA23VCC_AXG_8AA26VCC_AXG_9AA28VCC_AXG_10AB21VCC_AXG_11AB24VCC_AXG_12AB29VCC_AXG_13AC20VCC_AXG_14AC21VCC_AXG_15AC23VCC_AXG_16AC24VCC_AXG_17AC26VCC_AXG_18AC28VCC_AXG_19AC29VCC_AXG_20AD20VCC_AXG_21AD23VCC_AXG_22AD24VCC_AXG_23AD28VCC_AXG_24AF21VCC_AXG_25AF26

    VCC_AXG_27AH20VCC_AXG_28AH21VCC_AXG_29AH23VCC_AXG_30AH24

    VCC_AXG_NCTF_73 AP23VCC_AXG_NCTF_74 AP24VCC_AXG_NCTF_75 AR20VCC_AXG_NCTF_76 AR21VCC_AXG_NCTF_77 AR23VCC_AXG_NCTF_78 AR24VCC_AXG_NCTF_79 AR26

    VCC_13R30

    VCC_AXG_31AH26

    VCC_AXG_33AJ20VCC_AXG_34AN14

    VCC_SM_LF1 AW45VCC_SM_LF2 BC39VCC_SM_LF3 BE39VCC_SM_LF4 BD17VCC_SM_LF5 BD4VCC_SM_LF6 AW8VCC_SM_LF7 AT6

    VCC_AXG_26AA31

    VCC_AXG_32AD31

    VCC_3AH28

    VCC_AXG_NCTF_64 AM20

    VCC_SM_36AU30

    VCC_AXG_NCTF_80 V26VCC_AXG_NCTF_81 V28VCC_AXG_NCTF_82 V29VCC_AXG_NCTF_83 Y31

    C81

    0.22U_0603_10V7K~N

    1

    2

    C147

    22U_0805_6.3V4Z

    1

    2

    C120

    0.1U_0402_16V4Z~N

    1

    2

    C118

    22U_0805_6.3V4Z

    1

    2

    C67

    0.22U_0603_10V7K~N

    1

    2

    C121

    10U_0805_10V4Z~N

    1

    2

    C78

    1U_0603_10V4ZUMA@

    1

    2

    C79

    10U_0805_10V4Z~N

    UMA@

    1

    2

    +C374

    220U_D

    2_4VY_R15M

    1

    2

    C101

    0.47U_0603_10V7K

    UMA@

    1

    2

    C143

    0.22U_0402_10V4Z~N

    1

    2

    C161

    0.22U_0402_10V4Z~N

    1

    2

    C80

    0.1U_0402_16V4Z~N

    UMA@

    1

    2

    C163

    1U_0603_10V4Z

    1

    2

    C162

    10U_0805_10V4Z~N

    1

    2

    POWERV

    C

    C

    N

    C

    T

    F

    V

    S

    S

    N

    C

    T

    F

    V

    S

    S

    S

    C

    B

    V

    C

    C

    A

    X

    M

    V

    C

    C

    A

    X

    M

    N

    C

    T

    F

    U4F

    CRESTLINE_1p0 UMA@

    VCC_NCTF_1AB33

    VCC_NCTF_20AK37

    VCC_NCTF_29AP35

    VCC_NCTF_42U31

    VCC_NCTF_9AF33VCC_NCTF_10AF36VCC_NCTF_11AH33VCC_NCTF_12AH35VCC_NCTF_13AH36VCC_NCTF_14AH37VCC_NCTF_15AJ33

    VCC_NCTF_17AK33VCC_NCTF_18AK35VCC_NCTF_19AK36

    VCC_NCTF_2AB36

    VCC_NCTF_24AL33VCC_NCTF_25AL35

    VCC_NCTF_3AB37

    VCC_NCTF_30AP36VCC_NCTF_31AR35VCC_NCTF_32AR36

    VCC_NCTF_38T30VCC_NCTF_39T34VCC_NCTF_40T35VCC_NCTF_41U29

    VCC_NCTF_4AC33

    VCC_NCTF_43U32VCC_NCTF_44U33VCC_NCTF_45U35VCC_NCTF_46U36

    VCC_NCTF_48V33VCC_NCTF_49V36VCC_NCTF_50V37

    VCC_NCTF_5AC35VCC_NCTF_6AC36VCC_NCTF_7AD35

    VSS_NCTF_1 T27VSS_NCTF_2 T37VSS_NCTF_3 U24VSS_NCTF_4 U28VSS_NCTF_5 V31VSS_NCTF_6 V35

    VSS_NCTF_8 AB17VSS_NCTF_9 AB35

    VSS_NCTF_10 AD19

    VCC_NCTF_8AD36

    VSS_NCTF_7 AA19

    VSS_NCTF_11 AD37VSS_NCTF_12 AF17

    VSS_NCTF_14 AK17

    VSS_NCTF_16 AM24VSS_NCTF_17 AP26

    VSS_NCTF_19 AR15VSS_NCTF_20 AR19VSS_NCTF_21 AR28

    VCC_NCTF_33Y32

    VCC_AXM_4 AK24VCC_AXM_5 AK23VCC_AXM_6 AJ26VCC_AXM_7 AJ23

    VCC_AXM_NCTF_1AL24VCC_AXM_NCTF_2AL26VCC_AXM_NCTF_3AL28VCC_AXM_NCTF_4AM26VCC_AXM_NCTF_5AM28VCC_AXM_NCTF_6AM29VCC_AXM_NCTF_7AM31

    VCC_AXM_NCTF_10AP29VCC_AXM_NCTF_11AP31

    VCC_AXM_NCTF_17AR31

    VCC_NCTF_34Y33VCC_NCTF_35Y35VCC_NCTF_36Y36VCC_NCTF_37Y37 VSS_SCB1 A3

    VSS_SCB2 B2VSS_SCB3 C1VSS_SCB4 BL1VSS_SCB5 BL51VSS_SCB6 A51

    VCC_NCTF_26AA33VCC_NCTF_27AA35VCC_NCTF_28AA36

    VCC_NCTF_16AJ35

    VCC_NCTF_21AD33

    VSS_NCTF_13 AF35

    VCC_NCTF_22AJ36

    VCC_AXM_3 AK29

    VCC_AXM_NCTF_14AL29VCC_AXM_NCTF_15AL31VCC_AXM_NCTF_16AL32

    VSS_NCTF_15 AM17

    VCC_AXM_NCTF_8AM32VCC_AXM_NCTF_9AM33

    VCC_NCTF_23AM35

    VSS_NCTF_18 AP28

    VCC_AXM_NCTF_12AP32VCC_AXM_NCTF_13AP33

    VCC_AXM_NCTF_18AR32VCC_AXM_NCTF_19AR33

    VCC_AXM_2 AT31VCC_AXM_1 AT33

    VCC_NCTF_47V32

    C145

    1U_0603_10V4Z

    1

    2

    C71

    0.1U_0402_16V4Z~N

    1

    2

    C165

    22U_0805_6.3V4Z

    1

    2

    R78

    0_0603_5%

    1 2

    C99

    0.1U_0402_16V4Z~N

    UMA@

    1

    2

    C70

    0.1U_0402_16V4Z~N

    1

    2

    C119

    0.22U_0402_10V4Z~N

    1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1CRESTLINE((6/6)-PWR/GND

    Custom

    12 49Thursday, January 10, 2008

    2007/1/15 2008/1/15Compal Electronics, Inc.

    VSS

    U4J

    CRESTLINE_1p0 UMA@

    VSS_199C46VSS_200C50VSS_201C7VSS_202D13VSS_203D24VSS_204D3VSS_205D32VSS_206D39VSS_207D45VSS_208D49VSS_209E10VSS_210E16VSS_211E24VSS_212E28VSS_213E32VSS_214E47VSS_215F19VSS_216F36VSS_217F4VSS_218F40VSS_219F50VSS_220G1VSS_221G13VSS_222G16VSS_223G19VSS_224G24VSS_225G28VSS_226G29VSS_227G33VSS_228G42VSS_229G45VSS_230G48VSS_231G8VSS_232H24VSS_233H28VSS_234H4VSS_235H45VSS_236J11VSS_237J16VSS_238J2VSS_239J24VSS_240J28VSS_241J33VSS_242J35VSS_243J39

    VSS_245K12VSS_246K47VSS_247K8VSS_248L1VSS_249L17VSS_250L20VSS_251L24VSS_252L28VSS_253L3VSS_254L33VSS_255L49VSS_256M28VSS_257M42VSS_258M46VSS_259M49VSS_260M5VSS_261M50VSS_262M9VSS_263N11VSS_264N14VSS_265N17VSS_266N29VSS_267N32VSS_268N36VSS_269N39VSS_270N44VSS_271N49VSS_272N7VSS_273P19VSS_274P2VSS_275P23VSS_276P3VSS_277P50VSS_278R49VSS_279T39VSS_280T43VSS_281T47VSS_282U41VSS_283U45VSS_284U50

    VSS_287 W11VSS_288 W39VSS_289 W43VSS_290 W47VSS_291 W5VSS_292 W7VSS_293 Y13VSS_294 Y2VSS_295 Y41

    VSS_285V2VSS_286V3

    VSS_296 Y45VSS_297 Y49VSS_298 Y5VSS_299 Y50VSS_300 Y11VSS_301 P29VSS_302 T29VSS_303 T31VSS_304 T33VSS_305 R28

    VSS_306 AA32VSS_307 AB32VSS_308 AD32VSS_309 AF28VSS_310 AF29VSS_311 AT27VSS_312 AV25VSS_313 H50

    VSS

    U4I

    CRESTLINE_1p0 UMA@

    VSS_1A13

    VSS_198 C41

    VSS_2A15VSS_3A17VSS_4A24VSS_5AA21VSS_6AA24VSS_7AA29VSS_8AB20VSS_9AB23VSS_10AB26VSS_11AB28VSS_12AB31VSS_13AC10VSS_14AC13VSS_15AC3VSS_16AC39VSS_17AC43

    VSS_19AD1VSS_20AD21VSS_21AD26VSS_22AD29VSS_23AD3VSS_24AD41VSS_25AD45VSS_26AD49VSS_27AD5VSS_28AD50VSS_29AD8VSS_30AE10VSS_31AE14VSS_32AE6VSS_33AF20VSS_34AF23VSS_35AF24VSS_36AF31VSS_37AG2VSS_38AG38VSS_39AG43VSS_40AG47VSS_41AG50VSS_42AH3VSS_43AH40VSS_44AH41VSS_45AH7VSS_46AH9VSS_47AJ11VSS_48AJ13VSS_49AJ21VSS_50AJ24VSS_51AJ29VSS_52AJ32VSS_53AJ43VSS_54AJ45VSS_55AJ49VSS_56AK20VSS_57AK21VSS_58AK26VSS_59AK28VSS_60AK31VSS_61AK51VSS_62AL1VSS_63AM11VSS_64AM13VSS_65AM3VSS_66AM4VSS_67AM41VSS_68AM45VSS_69AN1VSS_70AN38VSS_71AN39VSS_72AN43VSS_73AN5VSS_74AN7VSS_75AP4VSS_76AP48VSS_77AP50VSS_78AR11VSS_79AR2VSS_80AR39VSS_81AR44VSS_82AR47VSS_83AR7VSS_84AT10VSS_85AT14VSS_86AT41VSS_87AT49

    VSS_97AW1

    VSS_100 AW24VSS_101 AW29VSS_102 AW32VSS_103 AW5VSS_104 AW7VSS_105 AY10VSS_106 AY24VSS_107 AY37VSS_108 AY42VSS_109 AY43VSS_110 AY45VSS_111 AY47VSS_112 AY50VSS_113 B10VSS_114 B20VSS_115 B24VSS_116 B29VSS_117 B30VSS_118 B35VSS_119 B38VSS_120 B43VSS_121 B46VSS_122 B5VSS_123 B8VSS_124 BA1VSS_125 BA17VSS_126 BA18VSS_127 BA2VSS_128 BA24VSS_129 BB12VSS_130 BB25VSS_131 BB40VSS_132 BB44VSS_133 BB49VSS_134 BB8VSS_135 BC16VSS_136 BC24VSS_137 BC25VSS_138 BC36VSS_139 BC40VSS_140 BC51VSS_141 BD13VSS_142 BD2VSS_143 BD28VSS_144 BD45VSS_145 BD48VSS_146 BD5VSS_147 BE1VSS_148 BE19VSS_149 BE23VSS_150 BE30VSS_151 BE42VSS_152 BE51VSS_153 BE8VSS_154 BF12VSS_155 BF16VSS_156 BF36VSS_157 BG19VSS_158 BG2VSS_159 BG24VSS_160 BG29VSS_161 BG39VSS_162 BG48VSS_163 BG5VSS_164 BG51VSS_165 BH17VSS_166 BH30VSS_167 BH44VSS_168 BH46VSS_169 BH8VSS_170 BJ11VSS_171 BJ13VSS_172 BJ38VSS_173 BJ4VSS_174 BJ42VSS_175 BJ46VSS_176 BK15VSS_177 BK17VSS_178 BK25VSS_179 BK29

    VSS_88AU1VSS_89AU23VSS_90AU29VSS_91AU3VSS_92AU36VSS_93AU49VSS_94AU51VSS_95AV39VSS_96AV48

    VSS_99AW16VSS_98AW12

    VSS_180 BK36

    VSS_182 BK44

    VSS_184 BK8

    VSS_186 BL13

    VSS_188 BL22

    VSS_18AC47

    VSS_191 C12

    VSS_193 C19

    VSS_195 C29

    VSS_197 C36

    VSS_181 BK40

    VSS_183 BK6

    VSS_185 BL11

    VSS_187 BL19

    VSS_189 BL37VSS_190 BL47

    VSS_192 C16

    VSS_194 C28

    VSS_196 C33

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    DDR_A_D1

    DDR_A_D49

    DDR_A_D23DDR_A_D22

    DDR_A_D48

    M_CLK_DDR#1

    M_CLK_DDR#0

    M_CLK_DDR1

    M_CLK_DDR0

    DDR_CKE1_DIMMA

    DDR_A_MA3

    DDR_A_MA10

    DDR_A_MA1

    ICH_SM_CLK

    DDR_CS0_DIMMA#DDR_A_WE#

    DDR_A_MA5

    DDR_A_MA12DDR_A_MA7DDR_A_MA9

    DDR_A_DQS1

    DDR_A_D26DDR_A_D27

    DDR_A_D16DDR_A_D17

    DDR_A_D8

    DDR_A_DM2

    DDR_A_DM1

    DDR_A_DM3

    DDR_A_DQS2

    DDR_A_DQS0

    ICH_SM_DA

    DDR_A_DQS7

    DDR_A_DQS6

    DDR_A_DQS4

    DDR_A_DM0

    DDR_CS1_DIMMA#

    DDR_A_MA8

    DDR_CKE0_DIMMA

    DDR_A_MA6

    DDR_A_MA4

    DDR_A_MA0DDR_A_MA2

    DDR_A_MA11

    DDR_A_D53

    DDR_A_D21DDR_A_D20

    DDR_A_RAS#DDR_A_BS#1

    DDR_A_CAS#

    DDR_A_D3

    DDR_A_DM4

    DDR_A_DM6

    DDR_A_D55

    DDR_A_D52

    DDR_A_DQS5

    DDR_A_MA13

    DDR_A_DM7

    DDR_A_DM5

    DDR_A_D2

    DDR_A_BS#2

    DDR_A_BS#0

    DDR_A_DQS#4

    DDR_A_DQS#3DDR_A_DQS3

    DDR_A_DQS#2

    DDR_A_DQS#1

    DDR_A_DQS#0

    DDR_A_DQS#7

    DDR_A_DQS#6

    DDR_A_DQS#5

    DDR_A_BS#1DDR_A_MA0

    DDR_A_RAS#

    DDR_A_MA5

    M_ODT1

    DDR_CS0_DIMMA#

    DDR_A_MA8

    M_ODT1

    DDR_CS1_DIMMA#DDR_A_MA13M_ODT0

    DDR_A_VM_ODT0

    DDR_A_D19DDR_A_D18

    DDR_A_D60DDR_A_D61

    DDR_A_D35

    DDR_A_D57

    DDR_A_D25

    DDR_A_D13DDR_A_D12

    +DDR_MCH_REF1

    DDR_A_D56

    DDR_A_D9

    DDR_A_D51

    DDR_A_D63

    DDR_A_D36

    DDR_A_D58

    DDR_A_D42

    DDR_A_D37

    DDR_A_D54DDR_A_D50

    DDR_A_D5

    DDR_A_D4

    DDR_A_D14

    DDR_A_D11DDR_A_D10DDR_A_D15

    DDR_A_D28

    DDR_A_D30DDR_A_D31

    DDR_A_D7

    DDR_A_D6

    DDR_A_D45DDR_A_D40DDR_A_D44

    DDR_A_D24DDR_A_D29

    DDR_A_D62DDR_A_D59

    DDR_A_D47DDR_A_D46

    DDR_A_D43

    DDR_A_D41

    DDR_A_D0

    DDR_A_BS#2

    DDR_CKE0_DIMMA

    DDR_A_MA7

    DDR_A_MA12

    DDR_A_MA9

    DDR_A_MA4DDR_A_MA2

    DDR_CKE1_DIMMA

    DDR_A_MA1DDR_A_MA3

    DDR_A_MA10DDR_A_BS#0

    DDR_A_CAS#DDR_A_WE#

    DDR_A_MA6

    DDR_A_D38DDR_A_D39

    DDR_A_D34

    DDR_A_D33DDR_A_D32

    DDR_A_MA14

    DDR_A_MA14

    D

    D

    R

    _

    A

    _

    V

    +DDR_MCH_REF1

    DDR_A_MA11

    DDR_A_DQS[0..7]8

    DDR_A_DQS#[0..7]8

    DDR_A_DM[0..7]8

    DDR_A_D[0..63]8

    DDR_CKE0_DIMMA7

    DDR_A_MA[0..13]8

    DDR_A_BS#08

    DDR_A_BS#28

    DDR_A_CAS#8

    DDR_A_WE#8

    DDR_CS1_DIMMA#7

    M_ODT17

    M_CLK_DDR#0 7M_CLK_DDR0 7

    DDR_A_BS#1 8

    DDR_CKE1_DIMMA 7

    DDR_CS0_DIMMA# 7DDR_A_RAS# 8

    M_ODT0 7

    M_CLK_DDR#1 7

    ICH_SM_DA14,16,19,24

    M_CLK_DDR1 7

    ICH_SM_CLK14,16,19,24

    PM_EXTTS#0 7

    DDR_A_MA14 7

    +DDR_MCH_REF114

    +3VS

    +1.8V

    +0.9VS

    +1.8V

    +1.8V

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1DDR2 SO-DIMM I

    Custom

    13 49Thursday, January 10, 2008

    2007/1/15 2008/1/15

    Close to VREF pins of SO-DIMM

    Layout Note:Place these resistorclosely JP41,alltrace length Max=1.5"

    Layout Note:Place near JDIM1

    Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V

    SO-DIMM AREVERSEBottom side

    Layout Note: +DDR_MCH_REFtrace width andspacing is 20/20.

    close to connector

    Compal Electronics, Inc.

    RP6

    56_0404_4P2R_5%

    1 42 3

    RP13

    56_0404_4P2R_5%

    1 42 3

    R

    3

    2

    1

    0

    K

    _

    0

    4

    0

    2

    _

    5

    %

    1

    2

    C220

    0.1U_0402_16V4Z

    1

    2

    C169

    2.2U_0603_6.3V6K

    1

    2

    RP5

    56_0404_4P2R_5%

    1 42 3

    C107

    0.1U_0402_16V4Z

    1

    2C151

    0.1U_0402_16V4Z

    1

    2

    RP23 56_0404_4P2R_5%1423

    RP17 56_0404_4P2R_5%1423

    C106

    0.1U_0402_16V4Z

    1

    2

    RP8 56_0404_4P2R_5%1423

    R96 56_0402_5%

    1 2

    C125

    0.1U_0402_16V4Z

    1

    2 C128

    0.1U_0402_16V4Z

    1

    2 C168

    0.1U_0402_16V4Z

    1

    2

    JDIM2

    FOX_ASOA426-M2RN-7F

    VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39

    VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199

    VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18

    DQ12 20DQ13 22

    VSS 24DM1 26VSS 28CK0 30

    CK0# 32VSS 34

    DQ14 36DQ15 38

    VSS 40

    VSS 42DQ20 44DQ21 46

    VSS 48NC 50

    DM2 52VSS 54

    DQ22 56DQ23 58

    VSS 60DQ28 62DQ29 64

    VSS 66DQS3# 68

    DQS3 70VSS 72

    DQ30 74DQ31 76

    VSS 78NC/CKE1 80

    VDD 82NC/A15 84NC/A14 86

    VDD 88A11 90

    A7 92A6 94

    VDD 96A4 98A2 100A0 102

    VDD 104BA1 106

    RAS# 108S0# 110

    VDD 112ODT0 114

    NC/A13 116VDD 118

    NC 120VSS 122

    DQ36 124DQ37 126

    VSS 128DM4 130VSS 132

    DQ38 134DQ39 136

    VSS 138DQ44 140DQ45 142

    VSS 144DQS5# 146

    DQS5 148VSS 150

    DQ46 152DQ47 154

    VSS 156DQ52 158DQ53 160

    VSS 162CK1 164

    CK1# 166VSS 168DM6 170VSS 172

    DQ54 174DQ55 176

    VSS 178DQ60 180DQ61 182

    VSS 184DQS7# 186

    DQS7 188VSS 190

    DQ62 192DQ63 194

    VSS 196SA0 198SA1 200

    RP22 56_0404_4P2R_5%1423

    RP1

    56_0404_4P2R_5%

    1 42 3

    C166

    2.2U_0603_6.3V6K

    1

    2

    RP16 56_0404_4P2R_5%1423

    C105

    2.2U_0603_6.3V6K

    1

    2

    C153

    0.1U_0402_16V4Z

    1

    2C127

    0.1U_0402_16V4Z

    1

    2

    C149

    2.2U_0603_6.3V6K

    1

    2

    C58

    0.1U_0402_16V4Z

    1

    2

    C201

    2.2U_0805_16V4Z

    1

    2

    RP14

    56_0404_4P2R_5%

    1 42 3

    RP15 56_0404_4P2R_5%1423

    RP2 56_0404_4P2R_5%1423

    RP7

    56_0404_4P2R_5%

    1 42 3

    C167

    0.1U_0402_16V4Z

    1

    2

    R

    3

    1

    1

    0

    K

    _

    0

    4

    0

    2

    _

    5

    %

    1

    2

    C129

    0.1U_0402_16V4Z

    1

    2

    R1441K_0402_1%

    1

    2

    C154

    0.1U_0402_16V4Z

    1

    2

    C130

    0.1U_0402_16V4Z

    1

    2

    R1431K_0402_1%

    1

    2

    C59

    2.2U_0603_6.3V6K

    1

    2

    C126

    0.1U_0402_16V4Z

    1

    2

    C124

    2.2U_0603_6.3V6K

    1

    2

    C

    2

    0

    6

    0

    .

    1

    U

    _

    0

    4

    0

    2

    _

    1

    6

    V

    4

    Z

    ~

    N

    1

    2

    C150

    0.1U_0402_16V4Z

    1

    2

    + C84

    330U 2.5V Y D

    2

    @

    1

    2

    C108

    0.1U_0402_16V4Z

    1

    2

    C131

    0.1U_0402_16V4Z

    1

    2

    C152

    0.1U_0402_16V4Z

    1

    2

  • 55

    4

    4

    3

    3

    2

    2

    1

    1

    D D

    C C

    B B

    A A

    DDR_B_RAS#DDR_CS2_DIMMB#

    DDR_B_MA11

    DDR_CKE3_DIMMB

    DDR_B_MA2DDR_B_MA4

    DDR_B_BS#1DDR_B_MA0

    DDR_B_MA6DDR_B_MA7

    M_ODT3DDR_CS3_DIMMB#

    DDR_B_WE#

    DDR_B_MA5DDR_B_MA8

    DDR_B_V

    DDR_B_MA1

    DDR_B_CAS#

    DDR_B_MA3

    DDR_B_BS#0DDR_B_MA10

    DDR_B_MA9DDR_B_MA12

    DDR_CKE2_DIMMB

    DDR_B_MA14

    D

    D

    R

    _

    B

    _

    V

    DDR_B_BS#2

    DDR_B_D60

    DDR_B_DM5

    DDR_B_D45

    DDR_B_DM2

    DDR_B_D21

    DDR_B_D40

    DDR_B_CAS#

    DDR_B_D11

    DDR_B_D62

    DDR_B_MA4

    DDR_B_D27

    DDR_B_DQS2

    DDR_B_D10

    DDR_B_DQS1

    DDR_B_D0

    DDR_B_D55

    DDR_B_BS#1

    DDR_B_MA7DDR_B_MA11

    DDR_CKE3_DIMMB

    DDR_B_D24

    DDR_B_D22

    DDR_B_D7DDR_B_D6

    DDR_B_D30

    DDR_B_D1

    DDR_B_D47

    DDR_B_MA6

    DDR_B_D26

    M_CLK_DDR2

    DDR_B_D12

    DDR_B_DM0

    DDR_B_D28

    DDR_B_DQS0

    DDR_B_DM6

    DDR_B_D5

    DDR_B_D3

    DDR_B_DQS3

    M_CLK_DDR#2

    DDR_B_D41

    M_ODT3

    DDR_B_WE#

    DDR_B_D8

    DDR_B_D2

    DDR_B_D57

    DDR_B_D50

    DDR_B_D37

    DDR_B_D29

    DDR_B_D14

    DDR_B_MA5

    DDR_B_D51

    DDR_B_D42

    DDR_B_D38

    DDR_B_MA0

    DDR_B_D32

    DDR_B_MA3

    DDR_B_D46

    DDR_B_DQS5

    DDR_B_BS#0

    DDR_B_MA9

    DDR_B_D31

    ICH_SM_CLK

    DDR_B_D58

    DDR_B_D43

    DDR_B_D34

    DDR_B_MA12

    DDR_CKE2_DIMMB

    DDR_B_D25

    DDR_B_DQS6

    DDR_B_D49DDR_B_D48

    DDR_CS2_DIMMB#

    DDR_B_MA2

    DDR_B_D16

    DDR_B_D4

    DDR_CS3_DIMMB#

    DDR_B_BS#2

    DDR_B_DM3

    DDR_B_DQS7

    M_CLK_DDR#3

    DDR_B_D53

    DDR_B_D59

    DDR_B_D23

    DDR_B_D33

    DDR_B_DQS#1

    DDR_B_D36

    DDR_B_MA14

    DDR_B_DQS4DDR_B_DQS#4

    DDR_B_DQS#0

    ICH_SM_DA

    DDR_B_DM7

    DDR_B_D61

    DDR_B_D39

    DDR_B_MA13M_ODT2

    DDR_B_D35

    DDR_B_MA10

    DDR_B_D19

    DDR_B_DQS#2

    +DDR_MCH_REF1

    DDR_B_D63

    M_CLK_DDR3

    DDR_B_D56

    DDR_B_DQS#6

    DDR_B_DM4

    DDR_B_RAS#

    DDR_B_DQS#3

    DDR_B_MA8

    DDR_B_D18

    DDR_B_D20

    DDR_B_D9

    DDR_B_D54

    DDR_B_D52

    DDR_B_DQS#5

    DDR_B_D15

    DDR_B_DM1

    DDR_B_DQS#7

    DDR_B_D44

    DDR_B_D13

    DDR_B_MA1

    DDR_B_D17

    M_ODT2DDR_B_MA13

    DDR_B_DQS#[0..7]8

    DDR_B_DQS[0..7]8

    DDR_B_D[0..63]8

    DDR_B_MA[0..13]8

    DDR_B_DM[0..7]8

    DDR_CKE3_DIMMB 7

    DDR_CS2_DIMMB# 7

    +DDR_MCH_REF1 13

    DDR_B_WE#8

    DDR_B_BS#1 8DDR_B_RAS# 8

    DDR_B_CAS#8

    M_ODT37

    DDR_CKE2_DIMMB7

    DDR_CS3_DIMMB#7

    DDR_B_BS#28

    DDR_B_BS#08

    M_ODT2 7

    M_CLK_DDR3 7M_CLK_DDR#3 7

    M_CLK_DDR2 7M_CLK_DDR#2 7

    PM_EXTTS#1 7

    ICH_SM_DA13,16,19,24ICH_SM_CLK13,16,19,24

    DDR_B_MA14 7

    +3VS+3VS

    +1.8V

    +0.9VS

    +1.8V

    Title

    Size Document Number Rev

    Date: Sheet of

    Security Classification Compal Secret Data

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    Issued Date Deciphered Date

    LA-4231P 0.1DDR2 SO-DIMM II

    Custom

    14 49Thursday, January 10, 2008

    2007/1/15 2008/1/15