Design and Analysis of Multi Phase DLL-Based Frequency Multipliers

Design and Analysis of Multiphase DLL-based Frequency Multipliers

By Shu-Ming Chang

A dissertation submitted in partial satisfaction of the requirements for the degree of

Master of Science In Electrical Engineering In the GRADUATE DIVISION Of the NATIONAL CENTRAL UNIVERSITY Taiwan, Republic of China

Professor Kuo-Hsing Cheng

June 2005

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92521035 94 7

16

1. 2. 3.

(Delay-Locked Loop) (Phase-Locked Loop) TSMC 0.18m 1P6M CMOS Process 1.8V 1.28GHz 220MHz~320MHz 1x2x 4x 2x 4x 220MHz ~ 320MHz (1 )440MHz ~ 640MHz (2 )880MHz ~ 1.28GHz (4 ) 1.0GHz 32.7ps 54.49ps 67.16mW

I

Design and Analysis of Multiphase DLL-based Frequency MultipliersBy Shu-Ming Chang Department of Electrical Engineering National Central University

AbstractDelay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as local oscillator and clock generator where only used with PLL in the past and are employed DLLs. So, the DLLs will be more significant in the near future. The main object of this thesis is the description and discussion in Delay-Locked Loop, multiphase edge combiner and fully differential edge combiner; uses TSMC 0.18m 1P6M CMOS process to design a 1.28GHz DLL-based frequency multiplier and the supply voltage is 1.8V. The operate frequency range of DLL is 220MHz to 329MHz; the multiple factor of the multiphase edge combiner can easily use with digital control code and the multiple factor is 1x, 2x and 4x. Besides, the fully differential edge combiner can directly synthesize the 2x and 4x output signals. The synthesized frequencies of the DLL-based frequency multiplier are 220MHz to 320MHz (multiply-by-1), 440MHz to 640MHz (multiply-by-2) and 880MHz to 1.28GHz (multiply-by-4). The power dissipation and peak-to-peak jitters are 67.16mW and 32.7ps, 54.49ps at 1.0GHz output clock frequency.

2005 7

Table of ContentsChapter 1 Introduction ................................................................................................1 1.1 Motivation........................................................................................................1 1.2 Research Goals.................................................................................................2 1.3 Thesis Organization .........................................................................................3 Chapter 2 Background of Frequency Synthesizer ......................................................5 2.1 Architecture of Frequency Synthesizer............................................................5 2.1.1 Direct Digital Frequency Synthesis ......................................................5 2.1.2 PLL-based Frequency Synthesizer .......................................................6 2.1.3 DLL-based Frequency Synthesizer.......................................................8 2.2 Phase-Locked Loop .........................................................................................9 2.2.1 Phase-Locked Loop Fundamental.......................................................10 2.2.2 Linear Model Analysis of PLL ...........................................................11 2.3 Delay-Locked Loop .......................................................................................12 2.3.1 Delay-Locked Loop Fundamental ......................................................13 2.3.1.1 Phase Detector .........................................................................14 2.3.1.2 Charge Pump (CP) and Loop Filter (LF).................................15 2.3.1.3 Voltage-Controlled Delay Line (VCDL)..................................16 2.3.2 Stability Analysis of Delay-Locked Loop...........................................17 2.3.3 Design Consideration of the Delay-Locked Loop ..............................18 2.3.4 Applications of DLL-based Frequency Synthesizer ...........................20 2.3.4.1 Frequency Multiplier for RF Front End...................................20 2.3.4.2 Frequency Multiplier for High Speed Serial Link ...................21 2.4 The Comparison of PLL/DLL-based Frequency Synthesizer .......................22 2.4.1 The basic of DLL-based Frequency Multiplier...................................23 2.4.1.1 Operation of DLL-based Frequency Multiplier.......................23 2.4.2 Timing Jitter Accumulation.................................................................25 Chapter 3 The Analysis of DLL-based Frequency Multiplier...................................28 3.1 Introduction....................................................................................................28 3.2 Performance Analysis ....................................................................................28 3.2.1 Phase Noise.........................................................................................29 3.2.1.1 Timing Jitter Accumulation......................................................30 3.2.1.2 Power Spectral Density of Timing Error Random Process......33 3.2.2 Spurious Tones....................................................................................35 3.2.2.1 Delay Mismatch .......................................................................35 IV

3.2.2.2 Static Phase Error.....................................................................36 3.3 Performance Implications for Communication Systems ...............................38 3.3.1 Phase Noise.........................................................................................38 3.3.2 Spurious Tones....................................................................................40 3.4 The Development of DLL-based Frequency Multiplier ................................41 3.4.1 Local Oscillator for PCS Applications................................................42 3.4.2 Frequency Multiplier for Clock Multiplication ..................................43 3.4.3 DLL-based Clock Synthesizer and Tunable Oscillator.......................44 3.4.4 Programmable DLL-based Frequency Multiplier...............................46 3.4.5 Low Power Small Area DLL-based Clock Generator ........................48 Chapter 4 The Programmable DLL-based Frequency Multiplier.............................50 4.1 Introduction....................................................................................................50 4.2 The Programmable Multiphase DLL-based Frequency Multiplier in High Speed Serial Link Application .............................................................................50 4.2.1 The Basic Idea of Programmable Multiphase DLL-based Frequency Multiplier .....................................................................................................52 4.3 Architecture of Programmable Multiphase DLL-based Frequency Multiplier ..............................................................................................................................55 4.3.1 Phase Selector and Multiphase Edge Combiner .................................56 4.3.2 Phase Detector ....................................................................................57 4.3.3 Charge Pump and Loop Filter.............................................................59 4.3.4 Voltage-Controlled Delay Line ...........................................................61 4.4 Simulation Results .........................................................................................63 4.5 Conclusion .....................................................................................................64 Chapter 5 The Fully Differential DLL-based Frequency Multiplier ........................66 5.1 Introduction....................................................................................................66 5.2 The Fully Differential DLL-based Frequency Multiplier in Wireless Communication System Application ...................................................................67 5.2.1 The Theory of Fully Differential DLL-based Frequency Multiplier ..68 5.3 Architecture of Fully Differential DLL-based Frequency Multiplier ............70 5.3.1 Fully Differential Edge Combiner and Duty Cycle Corrector............71 5.3.2 Phase Detector ....................................................................................73 5.3.3 Charge Pump and Loop Filter.............................................................74 5.3.4 Voltage-Controlled Delay Line...........................................................75 5.4 Simulation Results .........................................................................................79 5.5 Conclusion .....................................................................................................81 V

Chapter 6 Chip Implementationt...............................................................................83 6.1 Introduction....................................................................................................83 6.2 The Concept of Signal Integrity.....................................................................83 6.2.1 Termination .........................................................................................84 6.2.2 The Output Interface of LVDS Driver ................................................86 6.2.2.1 Single-Ended Trans-Impedance Amplifier (TIA) ....................86 6.2.2.2 Digitalize LVDS Driver ...........................................................87 6.3 Chip Overview ...............................................................................................89 6.4 Experimental results.......................................................................................91 Chapter 7 Conclusion................................................................................................95 References....................................................................................................................97

VI

List of FiguresFig. 2-1 Implementation of direct digital frequency synthesis ......................................6 Fig. 2-2 Frequency synthesis by phase-locked loop ......................................................8 Fig. 2-3 The block diagram of DLL-based frequency synthesizer ................................8 Fig. 2-4 Output frequency is synthesized by (a) N is odd (b) N is even........................9 Fig. 2-5 The architecture of phase-locked loop ...........................................................10 Fig. 2-6 Linear PLL model ..........................................................................................12 Fig. 2-7 Block diagram of the conventional analog DLL............................................14 Fig. 2-8 Definition of phase detector ...........................................................................14 Fig. 2-9 EXOR gate as phase detector .........................................................................14 Fig. 2-10 A simplified diagram of Charge Pump with Loop Filter..............................16 Fig. 2-11 A simplified Voltage-controlled delay line ...................................................16 Fig. 2-12 Small signal AC model of the conventional analog DLL ............................17 Fig. 2-13 The linear model of DLL with input noise NI(s)..........................................19 Fig. 2-14 The Bode plot of Eq. 2-14 ............................................................................19 Fig. 2-15 The linear model of DLL with supply and substrate noise Ns(s).................19 Fig. 2-16 The Bode plot of Eq. 2-15 ............................................................................20 Fig. 2-17 RF section of superheterodyne receiver .......................................................21 Fig. 2-18 Basic block diagram of a high-speed serial I/O ...........................................22 Fig. 2-19 The concept of DLL-based frequency multiplier .........................................23 Fig. 2-20 Operation for DLL-based frequency multiplier ...........................................24 Fig. 2-21 Timing jitter accumulation for ring oscillator vs. delay chain .....................26 Fig. 3-1 Timing uncertainties in a sinusoidal waveform..............................................29 Fig. 3-2 Timing error accumulation for 5-stage delay chain .......................................31 Fig. 3-3 Autocorrelation operation of random process X (nT ) ......................................34 VII

Fig. 3-4 Autocorrelation of timing error random process for 5-stage delay chain ......35 Fig. 3-5 Spurious tone with mismatch in delay stage ..................................................36 Fig. 3-6 Spurious tone with static phase error .............................................................37 Fig. 3-7 Phase noise plot for synthesized delay output................................................40 Fig. 3-8 Spurious tones locations.................................................................................41 Fig. 3-9 Blcok diagram of DLL-based frequency multiplier for PSC application ......42 Fig. 3-10 The schematic of edge combiner..................................................................43 Fig. 3-11 The schematic for 4x clock multiplier..........................................................44 Fig. 3-12 Optimized AND-OR block diagram.............................................................45 Fig. 3-13 The schematic of clock generation...............................................................46 Fig. 3-14 The schematic of VCDTL ............................................................................47 Fig. 3-15 The schematic of positive edge combiner ....................................................47 Fig. 3-16 The schematic of clock generator.................................................................48 Fig. 3-17 The schematic of frequency multiplier.........................................................48 Fig. 4-1 System architecture of the transceiver ...........................................................51 Fig. 4-2 Block diagram of the I/O link ........................................................................53 Fig. 4-3 Timing chart of I/O link .................................................................................53 Fig. 4-4 (a) The conventional frequency multiplier (b) the proposed..........................54 Fig. 4-5 The waveform of (a) phases evenly spaced (b) generated for 1x clock (c) generated for 2x clock (d) generated for4x clock..................................................55 Fig. 4-6 Block diagram of proposed DLL-based frequency multiplier .......................56 Fig. 4-7 The schematic of (a) phase selector and (b) multiphase edge combiner........57 Fig. 4-8 The characteristic of a J-K flip-flop PD .........................................................58 Fig. 4-9 The schematic and timing diagram of the dynamic phase detector ...............58 Fig. 4-10 The concept of charge pump circuit .............................................................59 Fig. 4-11 The schematic of charge pump and loop filter .............................................60 VIII

Fig. 4-12 Clock feed-through effect.............................................................................61 Fig. 4-13 Switch of the charge pump...........................................................................61 Fig. 4-14 (a) Schematic of delay and bias stage (b) Block diagram of eight delay stage ......................................................................................................................................62 Fig. 4-15 DLL phase equally distribution @ 250MHz ................................................63 Fig. 4-16 Output clocks @ 250MHz for 1x reference clock .......................................63 Fig. 4-17 Output clocks @ 500MHz for 2x reference clock .......................................64 Fig. 4-18 Output clock @ 1GHz for 4x reference clock..............................................64 Fig. 5-1 Functional block diagram of transceiver........................................................67 Fig. 5-2 The block diagram of double conversion transmitter.....................................68 Fig. 5-3 The block diagram of double quadrature transmitter .....................................68 Fig. 5-4 (a) The example of frequency synthesis (b) The simple schematic of conventional frequency multiplier..............................................................................69 Fig. 5-5 (a) (b) The main idea in synthesizing the frequency (c) the simple circuit of frequency multiplier....................................................................................................70 Fig. 5-6 The proposed DLL-based frequency multiplier .............................................71 Fig. 5-7 (a) The schematic of edge combiner (b) The circular walking chart .............72 Fig. 5-8 The schematic of duty cycle corrector ...........................................................73 Fig. 5-9 The schematic of phase detector ....................................................................74 Fig. 5-10 The state diagram of the three-state PD .......................................................74 Fig. 5-11 Schematic of the charge pump .....................................................................75 Fig. 5-12 (a) Voltage to current converter (b) delay element of VCDL (c) block diagram of eight delay stage .......................................................................................76 Fig. 5-13 Half-circuit of the delay cell for small signal analysis.................................76 Fig. 5-14 A schematic of duty-cycle corrector ............................................................78 Fig. 5-15 The characteristic transfer curve of bias circuit ...........................................79 IX

Fig. 5-16 The transfer curve of VCDL ........................................................................79 Fig. 5-17 (a) (b) Input and output waveform of DLL @ 250MHz ..............................80 Fig. 5-18 Fully differential output clocks @ 500MHz for 2x reference......................80 Fig. 5-19 Fully differential output clocks @ 1GHz for 4x reference ..........................81 Fig. 6-1 Package and channel model ...........................................................................83 Fig. 6-2 (a) Series termination (b) shunt termination ..................................................84 Fig. 6-3 Double termination and AC coupling.............................................................85 Fig. 6-4 (a) Block diagram and (b) schematic view of trans-impedance amplifier .....87 Fig. 6-5 Output interface with package model and AC-coupling ................................87 Fig. 6-6 Driver operations with (a) positive and (b) negative period ..........................88 Fig. 6-7 Output interface with package model and termination ..................................89 Fig. 6-8 Chip implementation block diagram ..............................................................89 Fig. 6-9 Layout for frequency multiplier .....................................................................90 Fig. 6-10 The photograph of the physical PCB ...........................................................92 Fig. 6-11 (a) Output waveforms of ext_out+ and out8+ in DLL (b) jitter histogram when DLL operate at 235MHz ......................................................................92 Fig. 6-12 (a) Output waveform with multiply-by-1 in type1 (b) jitter histogram........93 Fig. 6-13 DLL output and type2 2x output ..................................................................93 Fig. 6-14 (a) Output waveform with multiply-by-2 in type2 (b) jitter histogram........93 Fig. 6-15 (a) Output waveform with multiply-by-2 in type2 (b) jitter histogram........94

X

List of Tables

Table 2-1 Comparison of PLL and DLL ......................................................................27 Table 4-1 The relation of output phases and control signals........................................57 Table 4-2 The performance of frequency multiplier characteristics ............................64 Table 5-1 Performance summary of the VCDL ...........................................................79 Table 5-2 Performance table of frequency multiplier ..................................................81 Table 6-1 Performance summary of frequency multiplier ...........................................91 Table 6-2 Measurement results of frequency multiplier ..............................................94 Table 7-1 Comparison of DLL-based frequency multiplier.........................................96

XI

Chapter 1:

Introduction

Chapter 1

Introduction

1.1 MotivationWith the evolution of CMOS process technology, the demand of high speed and high integration density VLSI systems have exponential growth recently. However, the synchronous problem between IC modules is undoubtedly important and becomes one of the bottlenecks for high performance systems. CMOS phase-locked loop (PLL) and delay-locked loop (DLL) are designed and implemented to solve the problem of clock synchronization. Due to the difference of their configuration, the DLL is more stable than higher order PLLs and needs only one capacitor in its loop filter. Additionally, a DLL offers better jitter performance than a PLL because noise in the voltage controlled delay line (VCDL) do not accumulate over many clock cycles. As a consequence, the DLL is frequently used in clock synchronous. The applications for DLLs are not limited to clock synchronization. We can see DLL in many places such as RF frequency synthesis and high-speed serial link. The information is modulated and transmitted at a higher frequency than the signal bandwidth by the carrier frequency in most wireless communication systems. A precise frequency synthesizer usually implemented with a Phase-Locked Loop (PLL) to generate the carrier frequency. In order to maximize the usage and performance within the available bandwidth, we have to minimize the timing uncertainties. Conventionally, the Voltage-Controlled Oscillator (VCO) is implemented with an 1

Chapter 1:

Introduction

external component such as LC-tank in a PLL. However, it becomes more complex in circuit reduction and integration of the external component and the phase noise requirement of systems are generally more difficult to achieve, integrated VCOs and synthesizers may not be useful for RF frequency synthesis without new design techniques that improve their performance.

1.2 Research GoalsThis research addresses the issues regarding the local oscillator integration in CMOS for wired and wireless applications, and investigates the use of a DLL-Based frequency multiplier as a local oscillator to avoid the timing jitter accumulation in oscillators. Detailed design and analysis is given to estimate the phase noise performance of the DLL-based frequency multiplier; in addition, CMOS design techniques of the local oscillator are also presented.

The key contributions of this work are:

1.

A DLL-based frequency multiplier whose timing jitter does not accumulate from cycle-to-cycle, and whose noise performance is independent of the low quality factor of on-chip spiral inductors.

2.

An analytical model that describes the timing jitters and phase noise performance of CMOS differential source-coupled delay cells with PMOS triode-region loads.

3.

The applications of the DLL-based frequency multiplier analysis to a monolithic CMOS low-phase-noise local oscillator for RF front end and high-speed serial link applications.

2

Chapter 1:

Introduction

1.3 Thesis OrganizationThis thesis includes six chapters in which two DLL-based frequency multipliers concentrated on multiphase and fully differential output operation are proposed. Chapter 2 begins with a brief review of frequency synthesizer architecture. It will introduce the digital and PLL/DLL based frequency synthesis and focus on analog-type PLL and DLL including the stability analysis and design considerations. Finally, the comparison of PLL/DLL based synthesizer will be demonstrated. Chapter 3 introduces the analysis of the DLL-based frequency multiplier and the concept to achieve low phase noise performance. In this chapter, the main topic is in phase noise and spurious tone discussion. Phase noise occurs in delay cells caused by thermal noise induced timing error and a mathematical model that characterizes the noise behavior is presented. Spurious tones mainly due to mismatch in design delay cell. In the final section, it will briefly introduce the development of the DLL-based frequency multiplier in the recent years Chapter 4 presents the design of programmable multiphase DLL-based frequency multiplier by using programmable frequency multiplier circuit. We first briefly describe the multiphase DLL-based frequency multiplier in high-speed serial link system application. As followed by a detail description of delay-locked loop, phase selector and edge combiner design. In the last, the multiphase output waveform will be demonstrated. Chapter 5 first describes local oscillator in RF frond end, and then represents fully differential DLL-based frequency multiplier in wireless communication. A source coupled delay element is used to achieve low power consumption and good supply noise rejection simultaneously. Besides, the edge combiner is implemented by using a current mode logic topology to achieve a high bandwidth and high noise

3

Chapter 1:

Introduction

immunity. Finally, it will represent the fully differential waveform in the edge combiner. Chapter 6 presents the measurement results from the test prototype fabricated in a TSMC 0.18-m CMOS technology. The experimental setup is first described. We then present measure the power consumption and jitter histogram of DLL, multiphase edge combiner and differential edge combiner. In final section concludes this thesis.

4

Chapter 2: Architecture and Applications of Frequency Synthesizer

Chapter 2

Background of Frequency Synthesizer Systems

2.1 Architecture of Frequency SynthesizerThere are many different types of wireless communication systems on the market today, ranging from cordless and cellular phones for voice to wireless local area network for data. Although these systems (i.e. AMPS, IS-54, GSM, 802.11) differ from each other in many different ways (i.e. carrier frequency, channel spacing, modulation format, etc.), they all contain a RF functional block to modulate and demodulate the transmitted and received signals. Frequency synthesizer is similar to a local oscillator, which can produce one or more clock frequency from a lower reference clock frequency. The role of frequency synthesizer in receiver regards as a local oscillator to generate an accurate RF signal used for frequency translation and channel selection. There are many performance tradeoffs in design frequency synthesizer of wireless communications, for example, synthesized frequency range, power consumption, performance of phase noise and spurious tones. For this reason, this is very important in choosing suitable synthesizer architecture and will limit the accomplishment of the performance of the designed synthesizer.

2.1.1 Direct Digital Frequency SynthesisOne of the popular frequency synthesis techniques is direct digital frequency synthesis (DDFS). The fundamental structure is shown in Fig. 2-1. The accumulator 5

Chapter 2: Architecture and Applications of Frequency Synthesizer operates as a memory address that can be mapped to sine wave through a lookup table function block. Then a digital-to-analog converter (DAC) changes the digital signal into analog domain and finally filtered by a low pass filter to generate the desired output frequency. To generate a sine wave with lowest frequency, it takes 2N clock cycles for an output frequency fref/2N. Having a large number of N. Theoretically can increase the frequency resolution, the resolution can be infinitely small at the expense of higher hardware cost and DDFS has the advantage of rapid switching because of its open loop characteristics.

Fig. 2-1 Implementation of direct digital frequency synthesis On the other hand, the digital circuit and especially the DAC limit the upper frequency. Only several hundreds of MHz can be attained by the DDFS. In order to apply to the RF frequency, up-conversion of the DDFS output with integrated mixer in radio frequency can overcome its speed drawback [1]. Spurious tone is another problem due to imperfect DAC. Inevitable large power and large hardware costs make it hard to become the mainstream in the design of RF synthesizer.

2.1.2 PLL-based Frequency SynthesizerPhase-locked loop is one of the building blocks of PLL-based frequency synthesizer [2] and both of them are characterized by its feedback property. Dissimilar to direct synthesis techniques such as DDFS, PLL-based frequency synthesizer uses negative feedback to trace the reference clock frequency. Fig. 2-2 6

Chapter 2: Architecture and Applications of Frequency Synthesizer shows a frequency synthesizer that contains a linear phase-locked loop and this type PLL also can be represented as a linear model. In order to show this feedback loop working, first we have to assuming the reference clock and feedback signal to be

Vref (t ) = A1 sin(2f c1t + 1 ) V fb (t ) = A2 cos(2f c 2t + 2 )

(2-1) (2-2)

where fc1 and fc2 are the carrier frequency of reference signal Vref(t) and feedback signal Vfb(t), 1 and2 are their corresponding phase. After combining Vref(t) and Vfb(t) through signal multiplication. Finally, signal Vmul(t) imports into the loop filter and can be written asVmul (t ) = Vref (t ) V fb (t ) = Vref (t ) = A1 sin(2f c1t + 1 ) V fb (t ) = A2 cos(2f c 2t + 2 ) =

1 A1 A2 [sin(2 ( f c1 f c 2 )t + (1 2 )) 2 + sin(2 ( f c1 + f c 2 )t + (1 + 2 ))]

(2-3)

The low pass filter can filter the high frequency term and cancel the phase difference in this term. When the loop is locked, the phase difference between reference and feedback signal is approach zero. Then Vmul(t) can be rewritten as1 A1 A2 (1 2 ) and is also proportional to the phase difference between Vref(t) and 2 Vfb(t) (when 1, then sin) directly. The output frequency from voltagecontrolled oscillator (VCO) and the feedback frequency will rise when Vmul(t) is positive. In the same way, when Vmul(t) is a negative value, the feedback frequency from VCO will decrease. This forms a negative feedback process that will become stable at an output frequency such as that fout=Nfref. In general, the multiplier is replaced by phase frequency detector. Note that the phase frequency detector has a linear phase error to voltage response even with large phase error. The PLL, which contains a phase frequency detector and a charge pump, is called charge pump PLL. In next section, each one component of frequency7


synthesizer will be introduced.Vmul V fb VCO LPF fout

Vref

N

Fig. 2-2 Frequency synthesis by phase-locked loop

2.1.3 DLL-based Frequency Synthesizer

Fig. 2-3 The block diagram of DLL-based frequency synthesizer Another type of frequency synthesizer is usually called DLL-based frequency synthesizer. Delay-locked loop (DLL) is widely used in high-speed digital circuit such as I/O interface, clock data recovery, timing deskew circuit and clock generator [3]. A DLL is a PLL, which uses voltage-controlled delay line (VCDL) to replace VCO. Fig. 2-3 shows the simplified block diagram of DLL-based frequency synthesizer. When the loop is locked, the output phases of every delay stage are evenly spaced one reference clock period Tref. Each phase difference of two delay stage has a delay of Tref/N and the edge combiner can generates a transition for each phase output transition, hence the output frequency is the N times the reference frequency fref. The benefit of DLL-based frequency synthesizer is that used VCDL and the jitter8


do not accumulate from cycle to cycle as in the VCO. For this reason, it represents a good performance for phase noise and spurious tone at close-in frequency. The main drawback in DLL-based frequency synthesizer is that the edge combiner just can synthesize a fixed number of output frequencies by the number of the delay stage in the delay line. The following equations can be written as the output frequency is N-times of the DLL-based frequency synthesizer. Fout = N Fref , when N is odd Fout = N Fref , when N is even 2 (2-4) (2-5)

In Eq. 2-4, the reason of the multiple factor is N is the edge combiner synthesize each phases which are not coincide in the rising and falling transitions of the intermediate waveforms. In the same way when N is even number of the delay chain, the output waveforms coincide in the rising and falling transitions (as shown in Fig. 2-4). As these results, it is not suitable in applications where frequency tuning is required.

Fig. 2-4 Output frequency is synthesized by (a) N is odd (b) N is even

2.2 Phase-Locked LoopFrom the survey of frequency synthesizer architectures in the previous section, it is apparent that the DDFS architecture is not applicable for high-speed receiver with low power consumption. The operating frequencies of nowadays frequency9


synthesizer architecture almost approach GHz and DLL-based frequency synthesizer approach seems attractive for fixed-frequency applications, hence, fixed frequency is not suitable for the wireless communication applications. Therefore, we will focus solely on the PLL-based frequency synthesizer in the following section.

2.2.1 Phase-Locked Loop FundamentalA PLL circuit is essentially a negative feedback control system as shown in Fig. 2-5, it shows the circuit block diagram of the charge pump PLL that consists a voltage-controlled oscillator (VCO), a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), and a frequency divider (FD).

Fig. 2-5 The architecture of phase-locked loop The internal feedback signal fback from the divider is compared to external reference signal fin by the PFD, which generates two compared results UP and DN. When the reference waveform fin falls behind the feedback waveform fback, the UP becomes high. On the contrary, when the reference waveform fin takes the lead the feedback waveform fback, the DN becomes high. According to the signals of UP and DN, the charge pump will charge or discharge loop filter to vary VCO output frequency. In this system, a loop filter is used to filter out the high frequency part from the PFD. The loop filter always composed by one resistor and two capacitors to become 2nd order low pass filter, it

10


should be designed to stabilize the feedback loop of PLL by introducing zeros and poles. Finally, the feedback signal can be adjusted according to the synchronous the input reference signal. Generally, when the loop is locked the output frequency fout from VCO will become Nfin.

2.2.2 Linear Model Analysis of PLLThe PLL is a highly non-linear system. However, it can be described with a linear model if the loop is in lock. The loop is in lock when the phase error signal produced by the phase frequency detector settles on a constant value. This implies that the output signal has the same frequency as the input reference signal. A phase difference between the reference and feedback signal may exist depending on the type of PLL used. However, this phase difference remains constant while the loop is in lock. If the PLL is used as a frequency synthesizer, the output waveform will have frequency N times the reference frequency. The building blocks of Fig. 2-6 are taken as basis for the mathematical model of a PLL in lock. A loop division factor, N, is included in this model. N can be considered equal to one for PLLs with no frequency dividers [4]. With the linear model of the PLL, the PLL transfer function is equal to the following:H (s) = K PD KVCO F ( s ) out ( s ) = Ext ( s) s + K PD KVCO F ( s) N (2-6)

The phase error transfer function can be written as

e (s) s = Ext ( s) s + K PD KVCO F ( s )N And, the VCO control voltage transfer function is equal to the following

(2-7)

11


Vc ( s ) sK PD F ( s ) = Ext ( s) s + K PD KVCO F ( s ) N

(2-8)

As shown in Eq. 2-6, the PLL transfer function has a low-pass characteristic with a gain of N. This means that for slow (low frequency) variation in reference phase, the loop will basically track the input signal and produce as output phase that is N times larger. Thus the output frequency is N times the input reference frequency. The phase error transfer function, given in Eq. 2-7, has a high-pass characteristic [4].

EXT

e

out

Int

Fig. 2-6 Linear PLL model

2.3 Delay-Locked Loop [11]For high-performance microprocessors and memory ICs, the use of phaselocked loops (PLLs) or delay-locked loops (DLLs) is essential to minimize the negative effects caused by skews and jitters of clock signals. In applications where the frequency multiplication is not required, a DLL is a natural choice since it is free from the jitter accumulation problem of an oscillator-based PLL. Conventional DLLs, however, suffer from the problem of their limited delay range since DLLs adjust only the phase, not the frequency. While the phase error of PLLs is accumulated and persists for a long time in a noisy environment, that of DLLs is not accumulated, and thus, the clock generated from DLLs has lower jitter. Therefore, DLLs offer a good alternative to PLLs in cases where the reference clock comes from a low-jitter source,

12


although their usage is excluded in applications where frequency tracking is required, such as frequency synthesis and clock recovery from an input signal. However, the main problem of conventional DLLs is that they are very difficult to design to work over process, voltage, temperature and loading (PVTL) variations. Since DLLs adjust only phase, not frequency, the operating frequency range is severely limited. Conventional DLLs may suffer from harmonic locking over wide operating range. Therefore, various wide-range DLL architectures are proposed to overcome the problem of false locking. They are described as follows. In [7], an all-analog DLL uses the replica delay line to solve the narrow frequency range problem of a conventional DLL, which can increase the frequency range of voltage-controlled delay line. However, the analog DLLs are more influenced by the process variation. Thus, the digital DLLs [6] [8] have been proposed for better process portability. In [6], the self-correcting scheme is proposed to solve the problem of false locking. The DLLs of dual-loop architectures [5] [10] are also proposed to overcome the problem of a limited delay range by using multiple voltage-controlled delay lines. Besides, in [9], this DLL uses a phase selector circuit and a start-controlled circuit to solve false locking problems and keep the latency of one clock cycle.

2.3.1 Delay-Locked Loop FundamentalA simplified block diagram of the conventional analog DLL is illustrated in Fig. 2-7. This circuit contains a voltage-controlled delay line (VCDL), a phase detector, a charge pump, and a first order loop filter. The input reference clock, ref_clk, drives the delay line, consisting of cascaded variable delay stages. The output of the delay line, out_clk and the ref_clk are compared by the phase detector to detect the phase error. The phase detector output is integrated by the charge pump and loop filter capacitor to generate the control voltage, vctrl, of the delay stages.

13


Fig. 2-7 Block diagram of the conventional analog DLL

2.3.1.1 Phase DetectorA phase detector is a circuit whose average output, Vout , is linearly proportional to the phase difference, , between its two inputs is shown in Fig. 2-8. in the ideal case, the relationship between Vout and is linear, crossing the origin for =0. Called the "gain" of the PD, the slope of the line, KPD, is expressed in V/rad. A familiar example of phase detector is the EXOR gate. As shown in Fig. 2-9, as the phase difference between the inputs varies, so does the width of the output pulses, thereby providing a dc level proportional to . While the EXOR circuit produces error pulses on both rising and falling edges, other types of PD may respond only to positive or negative transitions.

Fig. 2-8 Definition of phase detectorV1(t) V1(t) V2(t)

Vout(t)

V2(t)

Vout(t)

Fig. 2-9 EXOR gate as phase detector

14


2.3.1.2 Charge Pump (CP) and Loop Filter (LF)The simplified diagram of charge pump with loop filter is shown in Fig. 2-10. It consists in two switched current sources driving a capacitor. Switching is realized by means of a three-state PD. When the output clock (out_clk) of the delay line lags after the input reference clock (ref_clk), the up signal is high and down signal is low. The up signal turns on the upper switch and charges the output node Vctrl. On the other hand, when the output clock (out_clk) of the delay line leads before the input reference clock (ref_clk), the up signal is low and down signal is high. The down signal turns on the lower switch and discharges the output node Vctrl. Finally, when ref_clk and out_clk are equal, both up signal and down signal are low, the net current is zero and output node Vctrl remains constant. To design charge pump we will consider with the non-ideal effects, such as leakage current, the mismatch, clock feed-through, charge sharing from current switches, the dead zone in the PD and so forth. These problems should be paid attention to carefully. Assuming the phase detector generates equal duration up and down signal at the locked state, the generated up and down current difference is given by follow Eq. 2-9. Q = (I up I down ) = (I down + I I down ) Ts = I Ts (2-9)

Where I is the difference current between up and down caused by the channel length modulation or mismatch of the charge pump, and Ts is the width of the up and down pulses at steady state when DLL locked. Q will cause the state phase error and should be as small as possible. Thus, minimizing Ts and I is reasonable. With non-feedback architecture of phase detector, Ts could be extremely short. To minimize channel modulation, we can increase the length of MOS or using high swing cascade circuit.

15

Chapter 2: Architecture and Applications of Frequency SynthesizerVdd up Icp up ref_clk Phase Detector out_clk down Icp Loop Filter Vctrl Vctrl down Icp

Fig. 2-10 A simplified diagram of Charge Pump with Loop Filter

2.3.1.3 Voltage-Controlled Delay Line (VCDL)Delay elements are widely used in digital systems and are essential parts for self-timed operation in high speed VLSI and phase modulation such as delay-locked loop (DLLs) or phase-locked loop (PLLs). Inverter chain and RC delay method have been the most common delay elements in those applications. Both of them are simple and easy to design. However, the characteristics of the delay elements are sensitive to environmental conditions such as supply voltage and ambient temperature. Attempts to find a delay element less sensitive to supply voltage and temperature variations have been made. A simplified voltage-controlled delay line is shown in Fig. 2-11.Vctrl ref_clk Single Delay Path out_clk

Fig. 2-11 A simplified Voltage-controlled delay line A differential stage chain provides stable characteristics but consumes static power, requires a complex biasing circuitry for delay variation, and in general, is not feasible to implement a large delay value with differential stages. Biasing techniques with feedback mechanism can enhance the figure of sensitivity. But such approaches cannot enhance such high frequency perturbation as the power line noise, which cause

16


metastability in synchronous systems.

2.3.2 Stability Analysis of Delay-Locked LoopBefore starting the stability analysis of ADLL, the small signal AC model shall be introduced first. This is shown in Fig. 2-12 where summer stands for phase detector, Icp is the charge pump current, TREF is the period of input reference clock, C is the capacitor value in loop filter, and KVCDL is the gain of VCDL. When loop is in steady-state locked condition, the s-domain transfer function from input to output isDI (S )

I CP Tref

1 SC

KVCDL

DO (S )

Fig. 2-12 Small signal AC model of the conventional analog DLLDO ( S ) 1 = DI ( S ) 1 + s where (2-10)

N

N =

I CP KVCDL TREF C

(2-11)

From Eq. 2-10, we can easily find that the DLL is a first order system that is inherently stable. Unlike the small-signal AC model for a typical PLL, a minimum of a second order transfer function is required. Since the transfer function is inherently stable, a wider loop bandwidth can be used. This allows a fast acquisition time, as well as the use of small loop filter capacitors facilitating integration. However, the small-signal AC model is only valid when the loop bandwidth, that is N, is much smaller than the phase detector comparison frequency (generally 10:1). Therefore, the following equation should be

17


satisfied for stability consideration.

1 N I K = CP VCDL REF 2 C 10 Where 2 TREF

(2-12)

N =

(2-13)

2.3.3 Design Consideration of the Delay-Locked LoopTo design a suitable DLL, some considerations have to satisfy by designer such as lock time, jitter performance and bandwidth requirement. The lock time and jitter performance are two major concerns when we design the DLL. The lock time describes how fast a DLL can lock from initial unlock state. Intuitively, if the loop bandwidth is wider then the lock time is shorter. On the contrary, if the loop bandwidth is narrow then the lock time is longer. Therefore, if we want lock time shorter, the loop bandwidth should set wider. We discuss about jitter performance versus bandwidth of DLL, when the DLL is in locked state, the output signal is not ideal. Due to existing of noise source in the circuits, there would be some vibration on the clock edges. Therefore, for the noise in the reference frequency, the linear model of DLL can be redrawn as shown on Fig. 2-13. The transfer function from output to input noise is Do ( s ) n = N I (S ) s + n (2-14)

From Bode diagram shown in Fig. 2-14, we can find that the DLL characteristic has a low-pass nature characteristic for the external noise. Therefore, if we want to eliminate output jitter produced by input noise, the loop bandwidth should set as small as possible.

18

Chapter 2: Architecture and Applications of Frequency SynthesizerN I (S )

DI (S )

I CP Tref

1 SC

KVCDL

DO (S )

Fig. 2-13 The linear model of DLL with input noise NI(s)

N

Fig. 2-14 The Bode plot of Eq. 2-14 Moreover, for the noise from supply and substrate, the linear model of DLL can be redrawn as shown in Fig. 2-15. The transfer function from output to supply and substrate noise is Do ( s) s = N s (S ) s + n (2-15)

From Bode diagram shown in Fig. 2-16, we can find that the DLL characteristic has a high-pass nature characteristic for the internal noise. Therefore, if we want to minimize output jitter due to internal delay line noise, the loop bandwidth should be made as wide as possible.N S (S )

DI (S )

+

_

I CP Tref

1 SC

KVCDL

+

+

DO (S )

Fig. 2-15 The linear model of DLL with supply and substrate noise Ns(s)

19

Chapter 2: Architecture and Applications of Frequency SynthesizerdB 0

N

Fig. 2-16 The Bode plot of Eq. 2-15

2.3.4 Applications of DLL-based Frequency SynthesizerIn this section, two applications for DLL-based frequency synthesizer will be simplified introduced. The DLL-based frequency synthesizer is applied into a local oscillator for frequency synthesis will be first introduced and next is applied into high-speed serial link application.

2.3.4.1 Frequency Multiplier for RF Front End [12]The market for wireless communication has undergone a tremendous growth in recent years. Such a design is implemented and intended integrated in a CMOS RF transceiver; the mismatch of the CMOS components will deteriorate the phase noise. The key to have a clean LO signal is take advantage of a high quality reference clock. Most clock generators in high performance wireless communication system employ a phase-locked loop (PLL), which includes a voltage-controlled oscillator (VCO) and its output timing uncertainty accumulates over multiple oscillation cycles. The high frequency circuits operate under increasingly more noisy conditions and suffer from the delay variation due to significant power supply/substrate noises. These delay variations cant be corrected instantaneously by the PLL. Delay-locked loop (DLL)-based clock multipliers have several advantages over conventional PLL-based clock multipliers.

20


Fig. 2-17 RF section of superheterodyne receiver The role of a DLL-based frequency multiplier is to provide a reference frequency for the frequency translation function. Fig. 2-17 shows the RF section of a conventional superheterodyne architecture. The received signal is amplified by a LVA and filtered by the IR filter. In this structure, we can employ the DLL-based frequency multiplier to replace the crystal oscillator.

2.3.4.2 Frequency Multiplier for High Speed Serial Link [13]The increasing speed of microprocessor, optical transmission links, intelligent hubs and routers, etc. is pushing the off-chip data rate into the gigabits-per-second range. Today, most CMOS chips drive unterminated lines with full-swing CMOS transmitter and use CMOS gates as receivers. There are many components in high-speed serial link like a multiplexer, a demultiplexer, a PLL and a Driver. Recently, high-speed I/O circuits have increased the absolute bandwidth. More importantly, the bandwidth of I/O circuits on the semiconductor technology-scaling curve, by the transmitter signaling with the incident wave. To achieve incident-wave signaling, these circuits use point-to-point interconnect over terminated transmission lines. Differential current-mode signaling is often used to reject common mode noise, minimize EMI, reduce power/ground bounce, isolate the system from noisy environment, and double the slew rate. In high-speed serial link technique, precision timing circuits and clock generator21


are based on PLLs or DLLs. PLL-based clock generator is difficult to design because PLL is a higher order system. DLL-based frequency multipliers have several disadvantages over PLL-based ones such as the difficulty of multiplication by using a VCDL.

Fig. 2-18 Basic block diagram of a high-speed serial I/O Fig. 2-18 shows the high-level diagram of high speed serial I/O consisting of a serializing transmitter, a channel, and a deserializing receiver. To operate with a bit period that is small compared to the time-of-flight over the channel, high-speed I/O circuits are typically terminated with a matched impendence at either or both ends to achieve incident-wave signaling and recover the clock phases from the data arriving at the receiver. A major timing noise contributor in high-speed I/O systems is the clock multiplier, which takes a low frequency and in most case, accurate reference clock and synthesizes a high frequency timing reference for the bit stream. In conventional systems, the clock multiplier is typically implemented as a PLL or using DLL frequency multiplier.

2.4 The Comparison of PLL/DLL-based Frequency Synthesizer [12]This section first introduces the basics of the DLL-based frequency multiplier. The approach to achieving low-phase-noise and operation are described. This is followed by a detailed noise analysis that predicts the phase noise performance for the frequency multiplier.22

Deserializer

Serializer


2.4.1 The basic of DLL-based Frequency Multiplier

Fig. 2-19 The concept of DLL-based frequency multiplier The DLL-based frequency multiplier approach takes advantage of the inherently low jitter of a low-frequency crystal oscillator reference to produce a low-phase-noise clock signal. This is accomplished by taking each relatively jitter-free but infrequent edge of the crystal oscillator output, and from that generating a burst of well-controlled evenly spaced edges that span one period of the crystal oscillator. These evenly spaced edges are combined to form a pattern of higher-frequency transitions and eventually generate the desired clock signal. Therefore, the phase noise in the bands of interest is closely related to that of the reference clock. This concept is illustrated in Fig. 2-19. Unlike conventional PLL-based frequency synthesizers, thermal noise induced timing edge uncertainties accumulate within one period of the crystal oscillator, consequently the phase noise does not increase within the crystal frequency. Given the extremely high quality and consequently very low phase noise of crystal oscillators, the overall phase noise of the clock output signal for this approach can be much lower than that of typical synthesizers using integrated VCOs.

2.4.1.1 Operation of DLL-based Frequency MultiplierTo generate the well-controlled and evenly spaced edges shown in Fig. 2-17, a delay-locked loop (DLL) with identical delay stages is needed. On the left of Fig. 2-18 is a conceptual block diagram of the DLL-based frequency multiplier. The23


reference clock frequency is the input delay chain. Each delay element produces a delayed version of the reference clock waveform. The phase detector senses the phase difference between the input and output of the delay chain and generates an error signal. This error signal controls a charge pump, whose output is filtered by the loop filter. The filter output is the control voltage that varies the time delay of each delay stage to minimize the phase error. When the loop is in the locked state, the input and output of the delay chain are in-phase. The outputs of delay elements generate waveforms with edges that are evenly spaced within one period of the reference clock.Phase Detector Tref Vin

Charge Pump

I

II Loop Filter

III

Voltage Controlled Delay Line

IV V V

Vin

I

II

III

IV

Edge Combiner

Xout Time

Fig. 2-20 Operation for DLL-based frequency multiplier For the five-delay stage example in Fig. 2-20, the output waveform of the first stage is delay 1/5Tp from the external reference clock waveform, where Tp is the external reference clock period. The output waveform of the second delay stage os delayed 1/5Tp from the previous output, and so on. When the loop is in the lock condition, the output of last delay stage is in-phase with the reference clock signal.

24


The output of the DLL equally divides the reference period by 5, and the sum of the time delays from all delay stages is precisely one period of the reference oscillation, Tp. To generate the clock signal, the edge combiner block produces oscillations in the local oscillator output from each rising edge in the DLL outputs. When the end of the delay chain is reached, since the last DLL output is in-phase with the input reference clock, the next edge to trigger the LO output is from the low jitter reference clock input. Repetitions of this process generate the LO waveform. Hence, the local oscillator output for this example is 5 times the reference frequency, or in a general case, N times the reference frequency, where N is the number of delay stages.

2.4.2 Timing Jitter AccumulationA DLL-based frequency using a voltage-controlled delay chain has an inherent advantage over a PLL using a voltage-controlled oscillator. Fig. 2-21 shows timing jitter accumulation for an oscillator compared with that of a DLL-based frequency multiplier. In an oscillator, random timing errors accumulate because the timing jitter at the end of each oscillation is the starting point of the next. The random timing error of the output signal is the sum of the timing errors of all previous oscillations. This translates to a poor long-term jitter performance, or, equivalently, poor close in phase noise. Fig. 2-21 shows the random timing uncertainty for a ring oscillator increase as a function of time. In contrast, for a finite length delay line in the DLL-based frequency multiplier, the random timing error accumulates only within a single delay chain cycle. The timing error in one cycle of the delay chain does not affect the next cycle, because the waveform that triggers the next output oscillation is the reference clock waveform.

25


This provides excellent long-term jitter performance, or, equivalently, a low close-in phase noise.

Fig. 2-21 Timing jitter accumulation for ring oscillator vs. delay chain The different phase noise signatures of a PLL with a VCO and a DLL-based frequency multiplier can also be understood by examining the source of synthesized output waveform. In a PLL, the output signal is taken directly from a VCO whose timing uncertainties accumulate over many oscillation cycles, limited by the time response of the PLL in which it is embedded. However, the PLL bandwidth is constrained by practical considerations to a value several orders of magnitude lower than the output frequency. In contrast, each output edge from the DLL only contains the timing uncertainties accumulated from the previous delay stages within the same reference oscillation period. Limited jitter accumulation gives a flat phase noise profile for offset frequencies less than fref. The long-term timing error accumulation, equivalent to the close-in phase noise, is much lower than that of a typical VCO. In Table 2-1, it summarizes the characteristics of PLL and DLL.

26


Table 2-1 Comparison of PLL and DLL

27

Chapter 3: The Analysis of DLL-based Frequency Multiplier

Chapter 3

The Analysis of DLL-based Frequency Multiplier

3.1 IntroductionChapter 2 described the most commonly used frequency synthesizer architecture such as PLL. The loop equation suggests that for a conventional PLL design with discrete VCOs, phase noise performance largely depends on the VCO phase noise due to the small loop bandwidth. However, the phase noise performance with a wide loop bandwidth PLL is still inadequate for narrow channel wireless communication systems. This chapter will introduce the performance parameter of the DLL-based frequency multiplier and these approaches to achieving low phase noise of DLL are described. This is followed by a detail noise analysis that predicts the phase noise performance for the frequency multiplier. In this chapter, it concludes the implications and applications of this DLL-based frequency multiplier.

3.2 Performance Analysis [12]The performance parameter such as phase noise and spurious tone makes huge influence in nowadays wireless communication systems. In this section, we will detail introduce and analyze the phase noise and spurious tone characteristics and performance of the DLL-based frequency multiplier. The analysis includes results from previous published research [14] ~ [16] and random process theory [17] ~ [20].

28


3.2.1 Phase NoiseThe most important performance specification for a frequency synthesizer is the phase noise. Phase noise is the random timing fluctuation in an oscillator period. Fig. 3-1 shows a sinusoidal waveform with timing uncertainties. Assuming the random timing error of the waveform occurs at the zero crossing point and can be defined as the discrete-time random process, X(t), the sinusoidal waveform can be written as, S (t ) = A(t ) cos{2f c [t X (t )]} (3-1)

Where A(t) is the amplitude, fc is the carrier frequency in Hertz (Hz). By applying a trigonometric identity, Eq. 3-1 can be re-written, S (t ) = A(t ) cos(2f c t ) cos[2f c X (t )] + A(t ) sin(2f c t ) sin[ 2f c X (t )] (3-2)

the random timing error is generally much smaller than the oscillation period, X(t) can be approximated with a discrete-time impulse function,X (t ) X ( nT ) n I

(3-3)

where T is the period of the carrier frequency, or

1 ; and fc

cos[2f c X (nT )] 1, and sin[2f c X (nT )] 2f c X (nT ) n IEq. 3-2 can then be approximated by

(3-4)

S (t ) A(t ) cos(2f c t ) + A(t ) [2f c X (nT )] sin(2f ct )

(3-5)

Fig. 3-1 Timing uncertainties in a sinusoidal waveform in which the carrier power and noise power are clearly separated into two terms. The 29

Chapter 3: The Analysis of DLL-based Frequency Multiplier phase noise term is a low frequency noise component modulated up to the carrier frequency by sin(2fct). Phase noise is typically measured as the power spectral density of the noise as a function of frequency compared to the carrier power at the carrier frequency; specified in dBc/Hz. In most cases, due to the circuit limiting effect, the oscillation amplitude is constant, A. Phase noise can be written as 1 ( A 2f c ) 2 [ S X ( nT ) ( f )] Noise Power = 2 = (2f c ) 2 [ S X ( nT ) ( f )] 1 2 Carrier Power A 2

(3-6)

where the carrier signal is a deterministic signal with power is A2/2. For noise power, since X ( nT ) is a random process, the power spectral density, ST ( t ) ( f ) , is used to find its power. Therefore, the noise power is ( A 2f c ) 2 [ S X ( nT ) ( f )] / 2 . Eq. 3-6 suggests that, in order to estimate the phase noise for this waveform, the power spectral density (PSD) of the random process, X ( nT ) , needs to be estimated. The phase noise performance of a DLL-based frequency multiplier is limited by the inherent phase noise of the input reference clock and the timing jitter contributed by the delay chain and edge combiner. Reference clock phase noise is very important, since the jitter noise power associated with each reference edge propagates into the delayed edges generate from it. However, due to the extremely high Q of available input reference clock signal, this source of noise is not an important contributor in this application of interest.

3.2.1.1 Timing Jitter AccumulationTo find the power spectral density, S X ( nT ) ( f ) , the random process X ( nT ) can

30

Chapter 3: The Analysis of DLL-based Frequency Multiplier be further defined according to the jitter accumulation pattern of the DLL-based frequency multiplier. As described earlier in this chapter, the output waveform of each delay stage in the DLL-based frequency multiplier triggers an oscillation in the final output. Assuming the edge combiner is noiseless, the random timing error associated with the output waveform of each delay stage directly shows up in the final output waveform as random timing error. T(t) is the random process that describes the random timing error of the final output waveform due to the delay stages as a function of time. Although the analytical equations below describe a general case, to help illustrating the analysis, a 5-stage delay line is shown in Fig. 3-2. For simplicity, the following assumptions are made. The delay chain is driven by a perfect crystal reference with no timing jitter. The random variable yij is the random timing error associated with a delay stage. The index i, 1 i 5 , indicates the specific delay stage.

Fig. 3-2 Timing error accumulation for 5-stage delay chain In the DLL-based frequency multiplier, the timing jitter accumulates within one cycle of the delay chain but does not affect the next cycle. Therefore, it is necessary to have the second index j , which denotes the specific number of delay chain cycles.

31

Chapter 3: The Analysis of DLL-based Frequency Multiplier Random variable, yij , is independent from random timing errors of other delay stages, zero mean and Gaussian distributed with variance 2 .2 E[ yij ] = 0, E[ yij ] = 2

(3-7)

With the above definitions and assumptions, X ( nT ) can now be written according to the random timing error of delay stages. In Fig. 3-2, the first output oscillation is triggered by the input reference clock. Assuming the reference clock has no timing error, the first term X (0) = 0 . The next output oscillation is triggered by the output of the delay stage 1, hence the timing error uncertainty is associated with the delay stage 1. Because this is the first pass through the delay chain, the random process X (1 T ) = y11 . The different shades of gray in Fig. 3-2 indicate the correspondence between delay stage and the random variable, yij . The next output oscillation is triggered by the output of the delay stage 2 and its timing error isX ( 2 T ) = y11 + y21 , which is the sum of random timing error variables associated

with delay stage 1 and 2. Similarly, the timing errors for following two oscillations are found to be X (3 T ) = y11 + y21 + y31 and X (4 T ) = y11 + y21 + y31 + y41 . The general expression for the random process up to this point isX ( n T ) = yi1 , for n < 5i =1 n

(3-8)

When the end of the delay chain is reached, the next oscillation is triggered by the next incoming reference clock edge and hence has no timing error: X (5 T ) = 0 The following oscillation is again triggered by the delay stage 1; however, the timing error for the second delay chain cycle is independent of that of the first cycle, therefore, X (6 T ) = y12 . In the same way, X (7 T ) = y12 + y22 and so on. In Fig.

32

Chapter 3: The Analysis of DLL-based Frequency Multiplier 3-2, a different fill pattern is used to denote the second cycle. The general expression for X ( nT ) is

X (nT , j ) =

n ( j 1) N

yi =1

ij

(3-9)

where N is the number of delay stages in the delay chain, and n is positive integer less than N. The graph in Fig. 3-2 represents the random process of timing jitter at different points in time as a function of random timing error variable associated with each delay stage. It also captures the independence of random timing error between different delay chain cycles.

3.2.1.2 Power Spectral Density of Timing Error Random ProcessOne way to find the power spectral density (PSD) of the timing error random process is to find the Fourier Transform of autocorrelation functionR XX ( ) = E[ X ( nT ) X ( nT )]

(3-10)

when = 0 , the autocorrelation equals the variance of the random process. For

N = 5,1 RXX (0) = E[ X ( nT ) X ( nT )] = (0 + 2 + 2 2 + 3 2 + 4 2 ) = 2 2 5

(3-11)

This is shown on the left side of Fig. 3-3. The factor of 1/5 comes from the autocorrelation function. When =1, the autocorrelation function is the expected value of the random process multiplied by a shifted version of itself and summed,RXX (1) = E[ X ( nT ) X ((n 1)T )] = 1 (0 + 2 + 2 2 + 3 2 + 0) = 1.2 2 5

(3-12)

When =2, the random timing error of first cycle overlap with that of the second cycle in the shifted version. However, since the timing errors are independent from cycle to cycle, the correlation for the overlapped section is zero. Therefore,

33

Chapter 3: The Analysis of DLL-based Frequency MultiplierRXX (2) = E[ X ( nT ) X ((n 2)T )] = 1 (0 + 2 + 2 2 + 0 + 0) = 0.6 2 5

(3-13)

The same approach gives RXX ( ) other values of . Fig. 3-4 shows the autocorrelation function for the 5-stage example. The general expression for the autocorrelation function isR XX ( ) = 1 NN 2 k =( N 2)

[ ( k )

N 1 l =1

l

2

]

(3-14)

where N is the number of delay stages in the delay line.X (nT ) X (nT )

X (nT t )

X(nT t)

Fig. 3-3 Autocorrelation operation of random process X ( nT )R XX ( ) / 2

Fig. 3-4 Autocorrelation of timing error random process for 5-stage delay chain If, previously assumed, the random timing error per stage is much smaller than the oscillation period, a Discrete-Time Fourier Transform (DTFT) can be applied to 34

Chapter 3: The Analysis of DLL-based Frequency Multiplier the above autocorrelation function, Eq. 3-14, to approximate the power spectral density (PSD). The result isS X ( ) =

n =

R

XX

(n) e jn

(3-15)

Combining Eq. 3-14 and Eq. 3-15, the general expression for the PSD becomesS XX () =

n =

{

N 2 1 [ (n k ) N k = ( N 2)

N n 1 l =1

l

2

]} e jn

(3-16)

where 2 is the variance of the random timing error per stage, and is a circuit dependent parameter. For 5-delay-stage exampleS X () = [ 2 + 12 6 3 cos() + cos( 2) + cos(3)] 2 5 5 5

(3-17)

3.2.2 Spurious TonesThe other key performance specification for a frequency synthesizer is its spurious tone level. Spurious tones can be defined as systematic timing fluctuations in oscillation periods. In the time domain, the presence of systematic fluctuations in an oscillation waveform represents periodic timing errors. In the frequency domain, this manifests as undesired components in the frequency spectrum. There are two major sources of spurious tones in a DLL-based frequency multiplier, first is a delay stage mismatch and second is a static phase error.

3.2.2.1 Delay MismatchWhen the DLL is in a perfect locked condition, the output waveforms of the DLL are evenly spaced within the reference period and the period of oscillation in the synthesized output waveform is identical. In the frequency domain, the output spectrum is a single tone with phase noise around the center frequency. However, if one of the delay stages has a mismatch (i.e., extra capacitance due to

35

Chapter 3: The Analysis of DLL-based Frequency Multiplier process variation or layout error), this causes the delay of this particular stage to be longer or shorter depending on the type of mismatch. As shown in Fig. 3-5, the delay stage 2 has a mismatch that causes its delay to be slightly shorter or longer than others. The effect of this mismatch on the output waveform is that the output edge corresponding to the second DLL is shifted forward or backward by the same amount in time. Since the DLL is locked to one period, and this mismatch also occurs at the same frequency,f ref , in the output waveform. Therefore, these systematic

mismatches in the frequency multiplier output waveform give rise to spurious tones atf ref and harmonics of f ref . The closest spurious tones to f c are located at f ref

away.

SX ( f )

f

Fig. 3-5 Spurious tone with mismatch in delay stage Mismatches in other parts of DLL-based frequency multiplier can also cause spurious tones similar to the one mentioned above. For example, mismatches at the inputs of the edge combiner also have a similar spurious tone effect.

36


3.2.2.2 Static Phase ErrorIn a DLL, the phase detector senses the phase difference between input and output of the delay chain and generates a pair of UP/DN signals to control the charge pump output current. This charge pump output signal is filtered by the loop filter to create a control voltage for delay line. If the DC gain from the phase detector to the loop filter is finite, a phase difference at inputs of the phase detector is required to sustain the desired control voltage. This phase difference is generally known as the static phase error, as shown in ! . In the DLL-based frequency multiplier, the delay chain input and output waveforms should ideally be in phase. The static phase error in a DLL represents a phase difference between input and output of the delay chain in a locked state. For example, ! shows the output waveform, fback, leads the input waveform by a small margin. Because the synthesized output oscillations are triggered by the DLL output waveforms, an extended "blank" period is found at the end of each delay chain cycle where the last oscillation completes and before the reference clock starts the next cycle. This is commonly referred as the deadzone.

Fig. 3-6 Spurious tone with static phase error 37

Chapter 3: The Analysis of DLL-based Frequency Multiplier The rate of occurrence for the deadzone is precisely, fref; hence similar to the delay-stage mismatch case, the static phase error also causes spurious tones to occur at fref and harmonics of fref where the closest spurious tones to fc are located at fref away. A common way to minimize the static phase error is to make the DC loop gain as large as possible. This can be achieved by properly selecting the loop filter topology such as placing a pole at the origin. However, mismatches between UP/DN currents of charge pump and other non-idealities still cause static phase error. Fortunately, the spurious tones generated by the static phase error have the same characteristics as the delay cell mismatch case. The conventional Phase-Locked Loop design also generates static phase error. Although there exist a slight phase difference between the input reference clock and VCO output in a PLL, since the desired output is the carrier frequency, its exact phase relationship to the reference clock is not critical for most wireless communication applications.

3.3 Performance Implications for Communication Systems [12]The previous section analyzed the two key performance measures, phase noise and spurious tones, for the DLL-based frequency multiplier. In the analysis, key contributors to the phase noise and spurious tones were described and their performance characteristics have been determined. In this section, a study of the phase noise and spurious tone performance characteristic is presented and their implications for the communication systems are discussed.

38


3.3.1 Phase NoiseIn Section 3.2.1, an extensive analysis was given to calculate the phase noise of the DLL-based frequency multiplier caused by the random timing errors in each delay stage. Because the random timing error for one delay stage is independent of other delay stages and does not accumulate from one delay chain cycle to the next, the correlation of timing error random process suggests a particular phase noise profile. The general equation for N-stage DLL was also given in Eq. 3-16. Recall from Eq. 3-5, that the phase noise is low frequency noise modulated up to RF frequency by the carrier frequency. Therefore, for low-frequency phase noise, it corresponds to the phase noise near the carrier frequency. In the 5-stage DLL example, the cosine terms in Eq. 3-17 equal to 1 for low frequencies; therefore, the phase noise is a constant near the carrier. As the offset frequency increases, the cosine terms start taking effect and the phase noise begins to decrease. This phase noise profile agrees well with intuition. For the timing error correlation of two distant timing incidences (corresponding to a low frequency), since the random timing error doesnt carry over one delay chain cycle, the worst case random timing error accumulation is one delay chain worth. This is shown as the flat region of the phase noise plot (case1 in Fig. 3-7). As the two timing incidences approach each other, the worst-case random timing error accumulation remains unchanged until the time difference between the two timing incidences becomes smaller than the period of the reference clock. At this point, the random timing error accumulation becomes less and less as the two timing incidences approach each other within the period of the reference clock frequency (equivalent to increasing the offset frequency). This can be seen as the phase noise roll-off at higher offset frequencies (case2 in Fig. 3-7). A noticeable difference between the phase noise curves of the DLL

39

Chapter 3: The Analysis of DLL-based Frequency Multiplier approach compared with that of a conventional oscillator is the flat region close to the carrier frequency vs. the typical oscillator phase noise shape. From the analysis in the previous section and discussion above, the long term jitter performance for the DLL-based frequency multiplier is excellent due to the non-cyclical nature of random timing error accumulation. In addition, its phase noise only depends on the random timing error of the delay stage. Thus a DLL-based frequency multiplier provides with excellent close-in phase noise performance not attainable with a monolithic PLL implementation for narrow-channel cellular applications.

Fig. 3-7 Phase noise plot for synthesized delay output

3.3.2 Spurious TonesSection 3.2.2 describes the two main contributors to spurious tones for the DLL-based frequency multiplier, namely delay stage mismatch and static phase error. Due to the periodic nature of the delay chain, both contributors result in the same

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Chapter 3: The Analysis of DLL-based Frequency Multiplier spurious tone characteristic where the closest spurious tones to the carrier, f c , are located at f c f ref . The system can only generate spurious tones at the integer multiples of the reference clock frequency. This is because the functional blocks performing the frequency division do not exist in this architecture. Fig. 3-8 is a graphical representation of the spurious tone positions relative to the other features of the output frequency spectrum.

SX ( f )

f

Fig. 3-8 Spurious tones locations Although mismatches are always present in an integrated circuit manufacture process due to lithography, process gradient, etc., by carefully choosing f ref , the spurious tones for this approach can be placed strategically at frequencies that do not affect the radio standards all reside in a narrow RF frequency band compared with the carrier frequency. In almost all transceivers available today, a RF filter close to the antenna rejects signals outside of the frequency band for the receiver and/or filter the PA output to avoid the spurious emission in a transmitter. When the spurious tones are

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Chapter 3: The Analysis of DLL-based Frequency Multiplier located outside of the frequency band, the blocking requirement for receiver and spectral emission for transmitter are both greatly reduced.

3.4 The Development of DLL-based Frequency MultiplierMost of the current communication system applications implement a frequency synthesizer with a PLL-based architecture typically. Today low cost radio frequency CMOS technology becomes the challenger of its conventional discrete counterpart and the solution for local oscillator has been demanded to process better phase noise and power consumption. This section will introduce and discuss the architectures the last DLL-based frequency multipliers that are presented.

3.4.1 Local Oscillator for PCS Applications [21]The DLL-based frequency multiplier consist a DLL and an edge combiner and is illustrated in Fig. 3-9; the objective of the DLL-based frequency multiplier is to produce a low phase noise carrier signal. In this figure, it shows a block diagram of the experimental prototype. The reference clock signal is first amplified and drives the delay line. The delay chain is composed by nine-stage delay elements and is locked to half of the reference clock period. A phase detector, charge pump and loop filter are used to generate the control voltage to the delay line. The edge combiner composed all the output phase from DLL and creates the multiplied frequency. The edge combiner consisting nine NMOS input differential pairs and a pair of LC-tanks and similar to the folding amplifier and shown in Fig. 3-10. The DLL having an odd number of delay element and there is a single current is modulated back and forth between the LC-tanks and creates the multiplied frequency. The LC-tank edge combiner used at the output is only to enhance the load impedance at

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Chapter 3: The Analysis of DLL-based Frequency Multiplier the resonance frequency. Since the quality factor of the inductor is low, the LC-tanks do not affect the close-in phase noise of the output signal. However, the low quality inductor translates to a large tail current to achieve the required output swing.

Fig. 3-9 Blcok diagram of DLL-based frequency multiplier for PSC application

Fig. 3-10 The schematic of edge combiner

3.4.2 Frequency Multiplier for Clock Multiplication [22]Clock multiplication is frequent in digital system. This is due to interconnection problems, which impair widespread distribution of the high clock frequencies available inside current chips. Traditional strategies use high frequency local clocks synchronized with lower frequency global clocks. For simplicity, it will discuss the kernel technique in terms of a basic model for a 43

Chapter 3: The Analysis of DLL-based Frequency Multiplier four tines multiplication factor. Fig. 3-11 schematically shows an example of the proposed multiplication technique. For a general idea, the multiplication factor is four, the circuit uses a SR-latch, some auxiliary digital logic (transition detector) and DLL with eight delay stages.

Fig. 3-11 The schematic for 4x clock multiplier The DLL synchronizes in such a way that presents a total delay of one clock cycle. Thus these delay stage can be considered as divide the delay time of 1/8 period between each two delay element. These output phases from delay elements are import into transition detectors to two different OR gates, in an alternate fashion (all odd stages are connected to one of the OR gate, and all the even stages are connect to the other OR gate). These create two impulse sequences with four times the clock frequency, with the sequences separated by 1/8 of the reference clock period. These clock pulses drive the SR latch, then forcing the pulse transitions. Thus the latch will switch states at twice the multiplication factor, creating the desired output clock. Generally, this multiplication mechanism can be easily implemented by choosing a 44

Chapter 3: The Analysis of DLL-based Frequency Multiplier multiplication factor.

3.4.3 DLL-based Clock Synthesizer and Tunable Oscillator [23]Traditionally, PLLs have been employed in clock frequency synthesis for a long time. A DLL is more stable than higher order PLLs because of DLL only needs one capacitor in its first order filter. On the other hand, the loop filter in PLL generally used more complex second order filter. This filter usually used larger components that may need to be off chip. Furthermore, a DLL offers better jitter performance than a PLL because phase errors induced by supply or substrate noise do not accumulate over many clock cycles. The clock synthesizer generates a differential output clock running at nine times the input reference clock. The clock synthesizer employs the DLL structure to generate the multiple clock phases that are then combined to produce the output clock. There are two steps in the generation of the output clock.

Fig. 3-12 Optimized AND-OR block diagram 1. The nine DLL output phases, (1 : 9) , to generate three clock signals such as ck1, ck2 and ck3. The 1 , 4 , and 7 output phases are combined in an optimized AND-OR structure (as shown in Fig. 3-12) with symmetrical to generate the clock ck1. For this reason, the 2 , 5 , and 8 phases produce ck2 and 3 , 6 , and 45


9 phases produce ck3.2. The synthesized output clock is to combined these three clocks (ck1, ck2 and ck3) in another AND-OR structure to produce a differential output clock, ck+ and ck, which is nine times of the reference clock. In Fig. 3-13, it represented the new AND-OR structure that high bandwidth available at the chip outputs is utilized (determined by the external pull-up resistor and load capacitance) to produce the output clock. The AND function of the clock generation is performed in the chip core and the analog OR function is performed in the I/O ring. External pull-up resistors set the output swing and match the output impedance to that of the outside equipment. Damping resistors are included to avoid any oscillations resulting from the combination of the lead and pin inductance and load capacitance.

Fig. 3-13 The schematic of clock generation

3.4.4 Programmable DLL-based Frequency Multiplier [24]Most of the current wireless systems utilize a PLL-based synthesis approach typically implemented with a VCO. If such a design is implemented and intended integrated in a CMOS RF transceiver, the low quality of the CMOS components will deteriorate the phase noise. The key to have a clean LO signal is take advantage of 46

Chapter 3: The Analysis of DLL-based Frequency Multiplier high quality reference clock from a crystal clock source, such that the close-in VCO phase noise will be suppressed. A CMOS local oscillator using a programmable DLL-based is present in this section. The frequency of the output clock is 8x to 10x of an input reference clock. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. VCDTL: It comprises a plurality of cascaded stages. One stage is composed of one delay cell and one demultiplexer (DEMUX). Such a serial of cascaded stages is called the tap line. The first stage of the tap line is driven by the external reference clock ,fref, which is assumed to be crystally clean. At the output node of each stage, different clocks with different phase shift are generated, which is named 1, , 2n. The DEMUXs are controlled by external signals, S[1:n], to determine the feedback path to PD from VCDTL (as shown in Fig. 3-14).

Fig. 3-14 The schematic of VCDTL Positive Edge Combiner (PEC): This circuit monitors the rising edges of these phases from VCDTL. As soon as one rising edges is detected, a corresponding low pulse is triggered as named as PULSE2, PULSE4, , PULSE2n. The low pulse train, PULSE2 that is the corresponding rise edge, is convinced by two adjacent generated clocks, i.e., 1 and 2. Its major operation is to catch the rising edges of the generated 47

Chapter 3: The Analysis of DLL-based Frequency Multiplier clocks and then produce corresponding low pulse trains. In Fig. 3-15 shows a four stage of positive edge combiner.

Fig. 3-15 The schematic of positive edge combiner Clock Generator: This circuit is in charge of generating the desired frequency by reading the external selection signal, S[1:n]. The output signal, PULSE2 PULSE2n, of PEC will be the strobe source of fout. Low pulse trains generate by PEC cells cannot be used directly as an ideal clock source apparently. A pseudo-N logic is utilized to realize such a generator as shown in Fig. 3-16.

fout

PULSE2

PULSE 2n

S[1]

Fig. 3-16 The schematic of clock generator

3.4.5 Low Power Small Area DLL-based Clock Generator [25]Most clock generators in high performance systems all use a PLL, which includes a VCO and a 2nd order loop filter. The PLL is a higher order system and is difficult to design. In the PLL, the VCO output timing uncertainty accumulates over

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Chapter 3: The Analysis of DLL-based Frequency Multiplier multiple oscillation cycles and is limited by the time response of the PLL. Compare with PLL-based frequency synthesizer, DLL-based clock multipliers have several inherent advantages over conventional PLL-based. The DLL is a 1st order system and is always stable and easier to design.Vreg Vreg Qbd

Qb Qbd A1 A2 AN Clk

Qbd

Fig. 3-17 The schematic of frequency multiplier A schematic diagram of the proposed frequency multiplier is shown in Fig. 3-17. Regulated power supply Vreg is used for the frequency multiplier. N in

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Design and Analysis of Multi Phase DLL-Based Frequency Multipliers