Design and Application of SiC Power MOSFET

Author

Linewih, Handoko

Published

2003

Thesis Type

Thesis (PhD Doctorate)

School

School of Microelectronic Engineering

DOI

https://doi.org/10.25904/1912/2574

Copyright Statement

The author owns the copyright in this thesis, unless stated otherwise.

Downloaded from

http://hdl.handle.net/10072/367638

Griffith Research Online

https://research-repository.griffith.edu.au

DESIGN AND APPLICATION OF

SiC POWER MOSFET

A thesis

Submitted to the Faculty

of

Engineering and Information Technology

Griffith University

by

Handoko Linewih

in Fulfilment of the Requirements for the Degree

of

Doctor of Philosophy

October 2002

ii

STATEMENT OF ORIGINALITY

This work has not previously been submitted for a degree or diploma in any university.

To the best of my knowledge and belief, the thesis contains no material previously

published or written by another person except where due reference is made in the

thesis itself.

……………………………..

Handoko Linewih

iii

ACKNOWLEDGMENTS

I would like to thank my principal supervisor, Prof. Sima Dimitrijev, for

taking me on as a student, providing challenging problems to work on and the

resources needed to tackle them. This interaction made my research a fulfilling and

enjoyable experience. This thesis would not be accomplished without his guidance,

encouragement, and his constructive criticism. I would also like to thank my associate

supervisor, Prof. Barry Harrison, and Dr. Chuck Weitzel for some very informative

and thought-provoking discussions.

Among fellow students, in chronological order of acquaintance, I would like

to thank Philippe Jamet, Takeharu Suzuki, Oliver Powel, and Kuan Yew Cheong.

Thanks also go to Dr. Ji Sheng Han for his collaboration and discussion on the

technical issues related to the fabrication of SiC MOSFET.

I will also take this opportunity to acknowledge the Australian Research

Council and Motorola Semiconductor Product Sector (AZ, USA) for their financial

support throughout this research project. I would like also to thank Dr Reinhold

Schörner and his colleagues from SiCED, Germany, for their collaboration in the

MOSFET fabrication and for providing the presented experimental results used in this

manuscript.

Finally, I would like to thank my wife Chiaki, for her understanding and

belief in my work and me.

iv

TABLE OF CONTENTS

STATEMENT OF ORIGINALITY ii ACKNOWLEDGMENTS iii LIST OF FIGURES vi LIST OF TABLES ix LIST OF PUBLICATIONS x ABSTRACT xi

1. INTRODUCTION 1-1

1.1. Material Advantages of SiC for Power Electronic Devices 1-1 1.2. Need for Suitable MOSFET Structure in SiC 1-3 1.3. Thesis Outline 1-5 1.4. Thesis Contribution 1-6 References 1-7

2. MODELS AND PARAMETERS OF 4H SiC FOR DEVICE SIMULATION 2-1

2.1. Introduction 2-1 2.2. MEDICI Device Simulator 2-3 2.3. 4H SiC Bulk Parameters 2-4

2.3.1. Intrinsic Carrier Concentration and Energy Gap 2-4 2.3.2. Impact Ionization 2-7 2.3.3. Mobility Models 2-11

2.3.3.1. Low Field Mobility 2-11 2.3.3.2. High Field Effect 2-13 2.3.3.3. Anisotropy in Mobility 2-15

2.4. Channel-Carrier Mobility Parameters Extraction in 4H SiC MOSFET 2-15 2.4.1. 4H SiC MOSFETs 2-16 2.4.2. MEDICI Channel Mobility Model 2-17 2.4.3. MEDICI Channel Mobility Parameters Extraction 2-20

2.4.3.1. Interface-Trap Density 2-21 2.4.3.2. Discussion on Model Parameters Extraction 2-22

2.4.4. SPICE Mobility Model 2-26 2.4.5. SPICE Parameters Extraction 2-26

2.5. Summary 2-29 References 2-31

v

3. NOVEL SiC ACCUMULATION-MODE POWER MOSFET 3-1

3.1. Introduction 3-1 3.2. Power MOSFETs in SiC 3-3

3.2.1. Material Advantages of 4H SiC for Power Devices 3-4 3.2.2. Trends in SiC Power MOSFETs 3-10 3.2.3. Review of Existing ACCUFET Structures 3-14

3.3. SiC Novel ACCUFET: Device Structure and Operation 3-20 3.4. Analysis and Optimization of Device Parameters 3-21

3.4.1. Simulation Parameters and Models 3-21 3.4.2. Peak Trench Region Concentration 3-22 3.4.3. P-base Layer Thickness 3-25 3.4.4. Thickness and Concentration of N-Channel Epilayer 3-27

3.5. Comparison-Based Evaluation of the Novel Structure 3-29 3.5.1. Electrical Performance 3-29 3.5.2. Discussion on the Device Structures 3-30 3.5.3. Device Processing Considerations 3-32

3.6. Summary 3-34 References 3-36

4. NOVEL ACCUFET IN SWITCH-MODE POWER SUPPLY SYSTEM 4-1

4.1. Introduction 4-1 4.2. Characteristics of SiC ACCUFET and Si VDD MOSFET 4-3

4.2.1. Device Structures 4-3 4.2.2. Device Parameters 4-5

4.3. Circuit Simulation 4-7 4.3.1. Circuit Topology 4-7 4.3.2. Circuit Simulation Results 4-9

4.4. System Benefits 4-14 4.4.1. Circuit Size Reduction 4-14 4.4.2. Superior Thermal Management 4-15

4.5. Summary 4-18 References 4-19

5. CONCLUSIONS AND RECOMMENDATIONS 5-1

5.1. Conclusions 5-1 5.2. Suggestion for Further Research 5-3

vi

APPENDIX A: FUNDAMENTALS OF SiC DEVICE PROCESSING AND PROPOSED PROCESS FOR THE FABRICATION OF NOVEL ACCUFET A-1

A.1. Introduction A-1 A.2. General Properties of SiC A-2

A.2.1. Polytypism in SiC A-2 A.2.2. SiC Bulk Crystal and Epitaxial Growth A-4

A.3. Process Technology Related Issues in SiC Device Fabrication A-5 A.3.1. Selective Doping of SiC A-6 A.3.2. SiC Etching A-6 A.3.3. Oxidation of SiC A-7

A.4. Proposed Fabrication of Novel ACCUFET A-8 A.4.1. Novel ACCUFET Structure Device Design A-9 A.4.2. Novel ACCUFET Proposed Run Sheet A-10 A.4.3. Novel ACCUFET Self-Aligned Proposed Process Steps A-12

References A-16

vii

LIST OF FIGURES

Figure Page 2-1 Intrinsic free-carrier concentration in 4H SiC and Si as a function of

temperature. ................................................................................................................ 2-6

2-2 Temperature dependence of the coefficients ap and bp for 4H and 6H SiC [15]. ..... 2-9

2-3 Comparison of the breakdown voltages, critical field, and depletion width

obtained from analytical equations to the values obtained from MEDICI

simulations for a Schottky diode 4H and parallel plane 6H SiC [15]..................... 2-10

2-4 Low field electron mobility as function of doping concentration in 4H SiC

(perpendicular to the c-axis, T=300 K). The empirical best fit as shown in solid

line is generated using Eq. 2.15 with parameter values given in Table 2-I [28]. ... 2-12

2-5 Drift velocity of electron (at 23 °C and 320 °C) in 4H SiC as functions of the

applied field. An empirical best fit to these curves as shown in solid lines are

generated using Eq. 2.17 with parameter values given in Table 2-II [29].............. 2-14

2-6 Measured transfer characteristic at VDS=50mV (a) and the inversion-layer

mobility (b) of 4H SiC n-channel MOSFET with Ldesign/Wdesign=10µm/800µm.... 2-18

2-7 N-channel MOSFET structure generated with MEDICI......................................... 2-21

2-8 Plots of the interface traps distribution used in numerical simulation (filled

rectangles) and of the measured data (blank circles)............................................... 2-22

2-9 Comparison of (a) transfer characteristics and (b) mobility between the

experimental data and simulation with the extracted parameter values listed in

Table 2-III. ................................................................................................................ 2-25

2-10 Comparison of (a) transfer characteristic and (b) mobility between the

experimental data and SPICE simulation with µ0=48.8 cm2/Vs, Vt =0.5 V, and

θ=0.034 V-1. .............................................................................................................. 2-28

2-11 Subthreshold characteristics of the MOSFET and from SPICE simulations. ........ 2-29

viii

3-1 Calculated specific on-resistance of 4H SiC power MOSFET using channel

mobilities ranging from 50 to 200 cm2/Vs and ideal case of Si power

MOSFET..................................................................................................................... 3-8

3-2 Inversion-type power SiC MOSFET structures....................................................... 3-13

3-3 (a) Cross section of basic structure accumulation-mode MOSFET, (b)

schematic conduction band profiles in the channel of MOS below threshold,

illustrating the barrier between the source and drain at zero drain bias. The

barrier heights shown are proportional to the energy gap for Si and 4H SiC,

respectively. .............................................................................................................. 3-15

3-4 Cross section of (a) Planar ACCUFET and (b) UMOS ACCUFET....................... 3-17

3-5 Specific on-resistance and breakdown voltage for SiC power MOSFET

reported to date. ........................................................................................................ 3-19

3-6 Novel SiC ACCUFET structure............................................................................... 3-20

3-7 Effects of peak trench-region concentration (Npeak) on maximum operating

voltage, on-resistance, and BFOM. WN=0.4 µm, ND=1x1016 cm-3. ....................... 3-24

3-8 Effects of P-base thickness (WP) on maximum operating voltage, on-resistance,

and BFOM. The difference between Npeak and P-base concentration is set to

4x1016 cm-3; WN=0.4 µm and ND=1x1016 cm-3, NA=1x1017 cm-3........................... 3-26

3-9 Effects of Nepi-channel concentration and thickness (WN) on maximum

operating voltage, on-resistance, and BFOM. WP=2.0 µm, ND=1x1016 cm-3,

NA=1x1017 cm-3. ....................................................................................................... 3-28

3-10 Comparison of simulated transfer characteristics.................................................... 3-31

4-1 Cross-sections of (a) VDD MOSFET and (b) novel ACCUFET. ............................ 4-4

4-2 Transfer characteristics of Si VDD MOSFET (a), and 4H SiC ACCUFET (b)....... 4-6

4-3 Basic configuration of a distributed power system [7].............................................. 4-8

4-4 The simplified boost PFC circuit. .............................................................................. 4-9

4-5 (a) Basic gate charge waveform; (b) variation in CGD capacitance with VDS [9].... 4-10

4-6 Waveforms of the circuit from Fig. 4-4 with Si VDD MOSFET. .......................... 4-11

4-7 Waveforms of the circuit from Fig. 4-4 with SiC ACCUFET................................ 4-12

4-8 Average power losses. .............................................................................................. 4-13

ix

4-9 Efficiency of the boost converter as a function of frequency.................................. 4-14

4-10 Example of thermal model of power electronic package scheme........................... 4-16

A-1 Crystal structure of 3C SiC (a), 4H SiC (b), and 6H SiC (c). .................................. A-3

A-2 Novel ACCUFET layout and cross section. ............................................................. A-9

x

LIST OF TABLES

Table Page 1-I Material properties of Si, 3C SiC, 6H SiC, and 4H SiC at 300 K............................. 1-3

2-I Parameters of low field mobility (Eq. 2.15) for 4H SiC at 300K [28].................... 2-12

2-II Parameters of the velocity field Eq. 2.17 for 4H SiC at two temperatures [29]. .... 2-14

2-III Parameters for 4H SiC MOSFET mobility models................................................. 2-24

2-IV Parameters for 4H SiC used in device simulation. .................................................. 2-30

3-I Values of doping concentration, electron mobility, drift layer thickness, and

specific on-resistance as a function of breakdown voltage for ideal 4H SiC and

Si power MOSFETs at room temperature condition................................................. 3-7

3-II Normalized figures of merit of polytypism in SiC material for high voltage

power devices [17]...................................................................................................... 3-9

3-III Summary of best-reported performances for inversion-type power SiC

MOSFETs. ................................................................................................................ 3-14

3-IV Summary of best-reported performances for accumulation-type power SiC

MOSFETs. ................................................................................................................ 3-18

3-V Comparison of ACCUFET structures...................................................................... 3-31

4-I Summary of device parameters for Si VDD MOSFET and 4H SiC ACCUFET

having the same device rating. ................................................................................... 4-7

A-I Wafer description for fabrication of novel ACCUFET device. ............................... A-8

xi

LIST OF PUBLICATIONS

Journal Papers

H. Linewih, S. Dimitrijev, C. E. Weitzel, and H. B. Harrison, “SiC ACCUFET for

Improved Performance of High Voltage Power Supply”, submitted to IEEE

Transactions on Power Electronics, 2002.

H. Linewih, S. Dimitrijev, and K. Y. Cheong, “Channel-Carrier Mobility Parameters

for 4H SiC MOSFETs”, Microelectronics Reliability, vol. 43, pp. 405-411, 2003.

H. Linewih, S. Dimitrijev, C. E. Weitzel, and H. B. Harrison, “Novel SiC

Accumulation-Mode Power MOSFET”, IEEE Transactions on Electron Devices, vol.

48, pp. 1711-1717, 2001.

Conference Papers

H. Linewih, S. Dimitrijev, and H. B. Harrison, “Development of Power

Accumulation-Type SiC MOSFET”, in Design, Characterization, and Packaging for

MEMS and Microelectronics, B. Courtois, S. Demidenko, Editors, Proceedings of

SPIE, vol. 3893, pp. 160-168, 1999.

H. Linewih and S. Dimitrijev, “Channel-Carrier Mobility Parameters for 4H SiC

MOSFETs”, Invited Paper in Proceedings of 23rd International Conference on

Microelectronics (MIEL 2002), pp. 425-430, Nis, Yugoslavia, 12-15 May, 2002.

xii

ABSTRACT

This thesis focuses on the design of high voltage MOSFET on SiC and its application

in power electronic systems. Parameters extraction for 4H SiC MOS devices is the

main focus of the first topic developed in this thesis. Calibration of two-dimensional

(2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC

MOSFETs data are performed, which includes the mobility parameter extraction. The

experimental data were obtained from lateral N-channel 4H SiC MOSFETs with

nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The

presence of increasing interface-trap density (Dit) toward the edge of the conduction

band is included during the 2-D device simulation. Using measured distribution of

interface-trap density for simulation of the transfer characteristics leads to good

agreement with the experimental transfer characteristic. The results demonstrate that

both MEDICI and SPICE simulators can be used for design and optimization of 4H

SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of

SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET

(ACCUFET) designed to address most of the open issues related to MOS interface is

proposed. Detailed analysis of the important design parameters of the novel structure is

performed using MEDICI with the parameter set used in the calibration process. The

novel structure was also compared to alternative ACCUFET approaches, specifically

planar and trench-gate ACCUFETs. The comparison shows that the novel structure

provides the highest figure of merit for power devices. The analysis of circuit

advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis.

The results from circuit simulation show that by utilizing the novel SiC ACCUFET the

operating frequency of the circuit can be increased 10 times for the same power

efficiency of the system. This leads to dramatic improvements in size, weight, cost and

thermal management of power electronic systems.

1-1

INTRODUCTION

The purpose of this introductory chapter is to present the motivation, the outline,

and the contributions of the work done in this thesis. A more in-depth introduction is given

in each of the main chapters of this thesis.

1.1. Material Advantages of SiC for Power Electronic Devices

Silicon carbide is a wide energy gap semiconductor that possesses a combination of

parameters that make it ideal for various applications in the electronic industry. Its physical

properties such as high electric field strength, high saturation drift velocity, and high thermal

conductivity, has made SiC at the center of a renewed focus of semiconductor material and

device research amongst the other wide energy gap semiconductors [1]. Vis-à-vis with other

wide energy gap semiconductors such as the III/V Nitrides [2], SiC has tremendous

advantages because of rapidly maturing technology for making single crystal substrates [3].

In addition, the ability to form a layer of thermal SiO2 on SiC in a similar way to silicon

provides the fabrication of SiC MOS-based electronic devices. Thus, given the superiority

and success of MOS-based devices in applications like high power/temperature electronics

[4], and storage (nonvolatile memories) devices [5], SiC is perceived to be the

semiconductor of choice with potential to revolutionize the way the electronic systems are

designed.

In view of the research in power switching devices, by far the largest effort has

concentrated on unipolar devices [6]. These include Field Effect Transistors (FETs) that exist

in many types, JFET, MOSFET, and MESFET. In low power electronic applications that

Chapter

1-2

require high switching speed, the Si MOSFETs have become the dominant technology for

many reasons [6]. The relatively low breakdown field in Si and the resistance of the drift

region that increases rapidly with increasing blocking voltage generally limit the use of Si

MOSFETs to 500 V and below. The advantages of SiC material properties, in particular the

high breakdown field, makes SiC MOSFETs a very promising candidate for high power

switching devices. The specific on-resistance of a SiC power device is expected to be 100-

200 times lower than a similarly rated silicon device [7]. Its much lower thermal minority

carrier generation implies lower leakage currents and device operation at higher

temperatures, arising from self-heating due to power dissipation, is more tolerable.

Moreover, the thermal conductivity of SiC is three times higher than Si and even higher than

copper at room temperature, also implying a higher efficiency of heat extraction from the

device and a further reduction in the requirements for device cooling.

Of the numerous polytypic forms of SiC, initial work focused on 3C material due to

the superior transport properties. However, the unavailable technology for growing 3C SiC

bulk crystals and the poor material quality of 3C SiC heteroepitaxially grown on Si, hinders

the advancement in 3C SiC devices. The availability and quality of reproducible single

crystal wafers in 4H and 6H SiC, make these polytypes the most promising materials for

electronic devices. The physical and electrical properties at room temperature for these three

common polytypes and Si (for reference) are listed in Table 1-I. 4H SiC’s substantially

higher carrier mobility compared to 6H SiC [8] should make it the polytype of choice for

most SiC electronic devices. Furthermore, the inherent mobility anisotropy that degrades

conduction parallel to the crystallographic c-axis in 6H SiC [8, 9] will particularly favor 4H

SiC for vertical power devices. The emergence of higher mobility 4H SiC has largely

overshadowed significant progress made in obtaining greatly improved 3C SiC through

heteroepitaxy on low-tilt-angle 6H SiC substrates [10, 11]. The higher mobility and more

isotropic nature of 4H SiC properties compared to 6H SiC has made 4H SiC the polytype of

choice and much of the current device research activity, including the study in this thesis, has

been done on 4H SiC.

1-3

Table 1-I Material properties of Si, 3C SiC, 6H SiC, and 4H SiC at 300 K.

1.2. Need for Suitable MOSFET Structure in SiC

Despite the superiority of SiC, device fabrication of SiC MOS devices presents

unique problems many of which are not yet totally resolved. When the background work on

this thesis was first undertaken, the issues related to the fabrication of SiC MOS-based

devices could be summarized as follows:

• The dependency in quality of oxide grown on the crystal orientation of SiC epilayers

[12, 13].

• The resultant surface roughness in the trench surface due to the RIE technique used in

formation of the SiC trench structure.

• Unique problems in the activation of P-type implants and its effect on SiC N-MOSFET

interface properties [14, 15].

• Inversion layer mobilities obtained to date in 6H SiC MOSFETs were about 10 – 50

cm2/Vs [16, 17], even lower in the case of 4H SiC MOSFETs [18, 19].

Property Si 3C SiC 6H SiC 4H SiC

Dielectric constant, ε 11.8 9.7 9.7 9.7 Energy gap, Eg (eV) 1.12 2.39 3.03 3.26 Critical Field, Ec (MV/cm)

0.3 1.5 3.2 3

Electron mobility, µn (cm2/Vs)

1400 750 3701 8001

Hole mobility, µp

(cm2/Vs) 600 40 90 115

Electron drift velocity, vsat (x107 cm/s)

1 2.5 2 2

Thermal conductivity, θk (W/cm K)

1.5 5 4.9 4.9

1: perpendicular to c-axis

1-4

In spite of these problems, the performance advantages of SiC devices have

motivated a number of groups to begin device development in parallel with the more

fundamental work on materials and processing issues. The following points summarize the

state of the art of SiC MOSFETs at the start of this research:

• The UMOS structure was identified by other groups as the power MOSFET structure

of choice for SiC. However, due to the process-related issues pointed out above and

severe enhancement in high-field stressing in the gate oxides at the bottom of the

etched trench [20], poor inversion channel mobility and low blocking voltage

capability in SiC UMOS-based devices was revealed.

• The DIMOS (Double Implanted Metal Oxide Semiconductor) type structures showed

promising results in terms of their blocking voltage. However, DIMOS-based devices

exhibited not only poor inversion channel mobility but also uncontrollable threshold

voltages, due to unique problems in the activation of P-type implants that are part of

their gate structure and its effect on interface properties [14, 15].

• The utilization of power accumulation-mode MOSFET (ACCUFET) on SiC [21]

showed as an encouraging way to overcome the problems associated with the poor

inversion layer mobilities.

The introduction of SiC ACCUFET [21] as an encouraging way to overcome the

problems associated with the poor inversion layer mobilities in the channels of the SiC

DMOS and UMOS structures was lead to significant activity in accumulation-mode SiC

MOSFETs [22, 23, 24, 25]. This has resulted in considerable progress in understanding and

improving the ACCUFET structure, although more progress is needed.

Based on this background work, it is concluded that the introduction of new device

structures that are designed to overcome the key (technological as well as structural)

problems is one of the factors needed to advance the current status of SiC MOSFETs and

forms the main thrust of this research work.

1-5

1.3. Thesis Outline

The research described in this thesis seeks to address the key problems in

developing MOSFET power devices in SiC. A novel structure of accumulation-mode

MOSFET (ACCUFET) for high power applications is proposed. The thesis includes the

design of the ACCUFET and a suggested application, as follows.

Chapter 2 begins with the introduction of the two-dimensional device simulator,

MEDICI, which is used throughout this thesis. It is then followed by the compilation of

important material/model parameter set for 4H SiC device simulation from literature.

Calibration of 2-D device and SPICE circuit simulator with state-of-the-art 4H SiC

MOSFETs data are also performed, which includes the first mobility parameter extraction

with the inclusion of decaying interface-trap density in the case of 2-D device simulation.

Chapter 3 starts with general analysis of 4H SiC as compared to Si power

MOSFET, followed by reviews of the state-of-the-art SiC power MOSFETs. The key

problems associated with the reviewed SiC MOSFETs are also addressed. The novel

ACCUFET structure is then proposed and analyzed. Simulation based evaluation of the

novel ACCUFET as compared to two alternative ACCUFET approaches are also given in

terms of their electrical performances as well as from a device processing point of view.

Chapter 4 emphasizes the system advantages gained from the implementation of

SiC MOSFET as a power switch. A case in which the performances of Si and the novel SiC

MOSFETs in a typical switch-mode power circuit are analyzed and compared. The results in

system advantages are finally given with respect to the circuit simulation results and material

properties.

Finally, the conclusions of this thesis are drawn in Chapter 5 and some

recommendations for future work are suggested.

1-6

1.4. Thesis Contribution

The original contribution of this thesis is summarized through the following points:

• Calibration of device simulator (MEDICI) with state-of-the-art 4H SiC MOSFET data,

which includes the mobility parameter extraction [26, 27].

• Critical review of SiC power MOSFETs.

• Design and analysis of a novel ACCUFET with superior figure of merit [28, 29].

• Analysis of circuit advantages provided by the novel ACCUFET [30].

1-7

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1-8

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Brandt, “1.1 kV 4H-SiC power UMOSFET’s,” IEEE Elect. Dev. Lett., vol. 18, p. 586,

1997.

[19] B. J. Baliga, “Prospects for SiC power devices”, in Int. Conf. on Silicon Carbide and

Rel. Mat., Abstr. MoA-I-1, p. 3, 1995.

[20] J. B. Casady, A. K. Agarwal, L. B. Rowland, W. F. Valek, and C. D. Brandt, “900 V

DMOS and 1100 V UMOS 4H-SiC power FET’s”, in Dev. Res. Conf., p. 32, 1997.

[21] P. M. Shenoy and B. J. Baliga, “The Planar 6H-SiC ACCUFET: A new high-voltage

power MOSFET structure,” IEEE Elect. Dev. Lett., vol. 18, p. 589, 1997.

1-9

[22] Y. Wang, C. Weitzel and M. Bhatnagar, “Design issues of SiC accumulation channel

power MOSFET”, Mat. Sci. Forum, vols. 338-342, p. 1287, 2000.

[23] R. Kumar, J. Kozima, and T. Yamamoto, “A novel diffusion resistant P-base region

implantation for accumulation mode 4H-SiC epi-channel field effect transistor,” Jpn. J.

Appl. Phys, vol. 39, p.2001, 2000.

[24] K. Hara, “Vital issues for SiC power devices”, Mat. Sci. Forum, vols. 264-268, p. 901,

1998.

[25] http://www.ecn.purdue.edu/WBG/Data_Bank/Best_Performance.html.

[26] H. Linewih, S. Dimitrijev, and K. Y. Cheong “Channel-carrier mobility parameters for

4H SiC MOSFETs”, Microelectronics Reliability, vol. 43, p. 405, 2003.

[27] H. Linewih and S. Dimitrijev, “Channel-carrier mobility parameters for 4H SiC

MOSFETs”, Invited Paper in Proceedings of 23rd International Conference on

Microelectronics (MIEL 2002), p. 425, Nis, Yugoslavia, 12-15 May, 2002.

[28] H. Linewih, S. Dimitrijev, and H. B. Harrison, “Development of power accumulation-

type SiC MOSFET”, in Design, Characterization, and Packaging for MEMS and

Microelectronics, B. Courtois, S. Demidenko, Editors, Proceedings of SPIE, vol. 3893,

p. 160, 1999.

[29] H. Linewih, S. Dimitrijev, C. E. Weitzel, and H. B. Harrison, “Novel SiC accumulation-

mode power MOSFET”, IEEE Trans. Elect. Dev., vol. 48, p. 1711, 2001.

[30] H. Linewih, S. Dimitrijev, C. E. Weitzel, and H. B. Harrison, “SiC ACCUFET for

improved performance of high voltage power supply”, submitted to IEEE Trans. Power

Elect., 2002.

2-1

MODELS AND PARAMETERS OF 4H SiC FOR DEVICE SIMULATION

2.1. Introduction 2-1 2.2. MEDICI Device Simulator 2-3 2.3. 4H SiC Bulk Parameters 2-4

2.3.1. Intrinsic Carrier Concentration and Energy Gap 2-4 2.3.2. Impact Ionization 2-7 2.3.3. Mobility Models 2-11

2.3.3.1. Low Field Mobility 2-11 2.3.3.2. High Field Effect 2-13 2.3.3.3. Anisotropy in Mobility 2-15

2.4. Channel-Carrier Mobility Parameters Extraction in 4H SiC MOSFET 2-15 2.4.1. 4H SiC MOSFETs 2-16 2.4.2. MEDICI Channel Mobility Model 2-17 2.4.3. MEDICI Channel Mobility Parameter Extraction 2-20

2.4.3.1. Interface-Trap Density 2-21 2.4.3.2. Discussion on Model Parameters Extraction 2-22

2.4.4. SPICE Mobility Model 2-26 2.4.5. SPICE Parameters Extraction 2-26

2.5. Summary 2-29 References 2-31

2.1. Introduction

Numerical device modeling and simulation are essential for analyzing and

developing semiconductor devices. They help a design engineer, not only gain an increased

understanding of the device operation, but also provide the ability to predict electrical

characteristics, behavior, and parameter-effects influence of the device. With this knowledge

Chapter

2-2

and abilities the designer can design a better structure, estimate device performance, perform

worst case analysis, and optimize device parameters to yield an optimize device

performance.

The increasing complexity of the structure models demonstrates that more accurate

modeling generally leads to increased computational difficulties. To consider additional

features that important in device design (such as non-uniform dopant profiles), numerical

approach simulation with the help of computers is almost a necessity. Even without these

added complications, computer aided simulation is especially helpful for the analysis of a

device in which two- and three-dimensional effects can have practical significance. The

increased availability of low-cost, high performance computing has made device simulation

widely accessible, e.g. MEDICI [1], BREAKDOWN [2], PISCES [3], MINIMOS [4],

ATLAS [5], and MICROTEC [6].

As in any device simulator, any quantitative, or even qualitative, simulation of a

device relies heavily on applicable device models and their parameter values. Although

several models with their default parameters are available in many commercial simulators,

some of their default parameters do not provide realistic characteristics of some

semiconductor materials; especially in SiC material, which exists in a host of polytypes.

It is the aim of this chapter to analyze the applicability of 4H SiC material

parameters from the literature and to implement them into the two-dimensional program

MEDICI as a way to calibrate the simulation process with the real device characteristics. It

starts with a brief introduction of MEDICI, followed by reviews of recently published

material concerning bulk parameters of 4H SiC that are applicable to MEDICI. Finally,

channel mobility parameters for the case of 4H SiC MOSFET results were extracted and

implemented in MEDICI and SPICE circuit simulator [7] with the inclusion of the effects of

interface-trap density on the model parameters.

2-3

2.2. MEDICI Device Simulator

MEDICI is a two-dimensional device simulator which solves numerically the

following five basic semiconductor device equations:

• the Poisson equation,

( ) SAD NNnpq ρψε −−+−−=∇ −+2 Eq. 2.1

• the electron and hole continuity equations,

nUqt

n −•∇=∂∂

nJ1 Eq. 2.2

pUqt

p −•∇=∂∂

pJ1 Eq. 2.3

• and the electron and hole current equations

nnnq φµ ∇−=nJ Eq. 2.4

pp pq φµ ∇−=pJ Eq. 2.5

where ε is the dielectric permittivity, ψ is the electrostatic potential, n and p are the electron

and hole concentrations, N+D and N-

A are the ionized donor and acceptor impurity

concentrations, ρS is the surface charge density which may be present due to the fixed charge

in insulating materials or charge interface states, Jn and Jp are vectors of the electron and

hole current density, Un and Up are the electron and hole net recombination rates, µn and µp

are the electron and hole mobilities, and φn and φp are the electron and hole quasi-Fermi

potentials.

The numerical algorithms used in MEDICI to solve the five basic device equations

are based on the finite element method, which discretized these equations on a simulation

2-4

grid. This discretization process yields a set of coupled nonlinear algebraic equations which

represent a number of grid points, for the unknown potentials and free-carrier concentrations.

This set of coupled nonlinear algebraic equations in return must be solved by a nonlinear

iteration method. Two iteration approaches, Gummel’s and Newton’s method are available

in MEDICI. Regardless which iteration method used, the solutions are carried out over the

entire grid until a self-consistent potential (ψ) and free-carrier concentrations (n, p) are

obtained. Once the potentials (ψ) and free-carrier concentrations (n, p) have been calculated

at a given bias, it is possible to determine the quasi-Fermi levels (φ) and the hole and electron

currents (Jn and Jp) from Eq. 2.4 – 2.5.

The results of device simulations depend critically on the physical models and

parameters used. A number of physical models are incorporated in MEDICI for accurate

simulations, including models for recombination, photogeneration, impact ionization, energy

gap narrowing, band-to-band tunneling, mobility, and lifetime [1]. Furthermore MEDICI

also supports a variety of semiconductor materials including SiC. All models and material

parameters can be modified on a region-to-region basis through statements in the input file.

2.3. 4H SiC Bulk Parameters

The modeling of 6H SiC has been reported in [8]. Since 6H SiC and 4H SiC are

different polytypes, their physical and electrical parameters are different as shown in Table

1-I. Special care has to be taken to account for these differences when modeling the 4H SiC

device. The following sub-sections described the important bulk models and parameters of

4H SiC in unipolar devices: intrinsic carrier, energy gap narrowing, impact ionization, and

carrier mobility.

2.3.1. Intrinsic Carrier Concentration and Energy Gap

The intrinsic carrier concentration ni is determined by the fundamental energy gap

Eg and the effective density of states NC and NV in the conduction and valence bands,

respectively. Neglecting bandgap narrowing, the intrinsic carrier concentration is defined as:

2-5

)2

exp()(kTE

NNTn gVCi

−= Eq. 2.6

where NC and NV are defined as

23

300)(

= TTNC NC300 Eq. 2.7

23

300)(

= TTNV NV300 Eq. 2.8

NC300 and NV300 are user-specified parameters used in MEDICI (shown in capital and

boldface letters throughout this chapter), which can be modified from their default values on

the material statement.

Sridhara et al [9] determined the energy gap of 4H SiC by absorption

measurements. The obtained value of 3.267 eV at 2 K seems in good agreement with the

previous value obtained from Ivanov et al [10]. The temperature dependency of energy gap

in MEDICI can be expressed as

+−

++=

EGBETAEGBETAEGALPHEG300

TTTEg

22

300300)( Eq. 2.9

Fig. 2-1 shows the intrinsic carrier concentration as a function of temperature for 4H SiC and

Si.

At high doping levels, the carrier-carrier interaction and overlap of the electron

wave functions play important role in the value of energy gap [11]. Bandgap narrowing

effects due to heavy doping are included as spatial variations in the intrinsic concentration

[12], which results in an adjustment to the electric field terms in the transportation of carriers

2-6

due to intrinsic Fermi potential. MEDICI describes the effect of heavy doping to the bandgap

as follows:

+

+= CON.BGNN.BGNN.BGN

V.BGN 2),(ln

),(ln

2.exp.),(

yxNyxNkT

qnyxn totaltotaliie Eq. 2.10

The V.BGN, N.BGN, and CON.BGN are constant parameters that can be adjusted from

their default values. Since no study of bandgap narrowing effects in SiC has been performed,

the default values for Si are used.

Figure 2-1 Intrinsic free-carrier concentration in 4H SiC and Si as a function of temperature.

2-7

2.3.2. Impact Ionization

Impact ionization, punch through mechanism, and oxide breakdown due to high

electric field stress are the main factors for determining the maximum voltage that a device

can stand. The impact ionization can be understood as the reverse process to the Auger

recombination [11]. A high energy hole or electron impacts an electron in the valence band,

thereby generating a new electron-hole pair. This in turn can generate a new electron-hole

pair after acceleration in a high electric field. The probability that electrons or holes create

electron-hole pairs is given by the product of a proportionality factor α (called impact-

ionization rate) and the electron/hole concentration.

The maximum electric field EC and the blocking capability VB is determined by the

impact-ionization rate for electron-hole pairs. Thus impact-ionization coefficient rates are the

key parameters that have to be estimated accurately to get reliable prediction of the device

blocking performance. A first approximation of the breakdown voltage as function of doping

was derived from Sze and Gibbons for various materials [13]. However, the insertion of

SiC’s energy gap into their fits yields to sufficient low values for EC [8].

Early report on measurements of the breakdown voltage as function of the doping

gradient and temperature for 4H SiC was performed by Palmour et al, that indicated negative

temperature coefficient for breakdown in SiC [14]. However, recent publication by

Raghunathan et al indicated positive temperature and lower coefficients using the pulsed

electron beam induced current (P-EBIC) technique [15]. Apart from experimental problems,

the deviations of the results might be caused by taking E parallel or perpendicular to the c-

axis of the crystals [8] or due the presence of defects in the material [15]. The parameter sets

for the ionization coefficient from Raghunathan et al measurements will be discussed in

detail and used throughout the work performed in this thesis.

Impact ionization analysis in MEDICI can be selected in two ways: using post-

processing method or self-consistent method. Either way the generation rate for electron-hole

pair due to impact ionization can be expressed by

2-8

iipp

iinnII

qJ

qJG ,, αα

+= Eq. 2.11

where nJ

and pJ

are the electron and hole current densities, and αn,ii and αp,ii are the

electron and hole ionization rates that are defined as generated electron-hole pairs per unit

length of travel and per electron and hole, respectively. These ionization rates can be

expressed in terms of the local electric field according to

−=

IIEXNIIECNexp IONIZAN

.

||,

..n

iin Eα Eq. 2.12

−=

IIEXPIIECPexp IONIZAP

.

||,

..p

iip Eα Eq. 2.13

It is not of any importance whether the ionization integral for the holes or the electrons is

calculated since both reach unity at V=VB. Therefore, the kind of dopants (n or p) in the

space charge region is not important.

From extensive measurements of impact ionization coefficients, performed by in

Raghunathan et al on many diodes across the wafer, the value of ionization coefficient αp

was found to vary as a function of electric field as dictated by the Chynoweth’s law [16],

which is the same as in the case of Si:

−=

||exp

Eb

a pppα Eq. 2.14

It was determined that the coefficients P.IONIZA (ap) and ECP.II (bp) at room temperature

in 4H SiC has average values of 3.25 x 106 cm-1 and 1.79 x 107 Vcm-1, respectively as shown

in Fig. 2-2 along with the value obtained for 6H SiC as functions of the temperature.

2-9

Figure 2-2 Temperature dependence of the coefficients ap and bp for 4H and 6H SiC [15].

MEDICI simulations were also performed in [15], to obtain the breakdown

voltages, the critical field and depletion width at breakdown for 4H SiC Schottky and

parallel plane 6H SiC structures for various doping concentration using the obtained

ionization coefficients. Fig. 2-3 shows the results of the simulations, along with the

analytical solutions for the parallel plane breakdown voltage, the critical field for breakdown,

and the depletion width at breakdown that derived using methodology for Si [17].

Calculations and simulations of the breakdown voltage, critical field, and depletion

width as function of doping performed shown in Fig. 2-3 can be used as a useful guidance in

designing any silicon carbide power device and refer only to defect free bulk material.

However, in real devices, tunneling may take place before avalanche breakdown at high

doping levels. Normally breakdown occurs at edges of the space charge region or at the

surface prior than in the bulk [18].

2-10

Figure 2-3 Comparison of the breakdown voltages, critical field, and depletion width obtained from analytical equations to the values obtained from MEDICI simulations for a Schottky diode 4H and parallel plane 6H SiC [15].

2-11

2.3.3. Mobility Models

It is well known that an accurate I-V model is strongly based on physical and

accurate mobility and velocity saturation models for any devices. At low normal electric

fields, the carrier mobility in a semiconductor is a function of the total doping concentration

and the temperature. As in the case of Si, lattice scattering (acoustic phonons) and ionized

impurity scattering, together with anisotropic scattering [19], seem to be the most relevant

mechanisms to limit the mean free path of carriers at low electric fields in SiC [20, 21, 22].

Since the free-carrier mobilities depend strongly on the magnitude of electric field, the

mobility model in MEDICI consists of low field and high field mobility components. An

optional module that described the anisotropic mobility is also available.

2.3.3.1. Low Field Mobility

For the low drift mobility, the empirical model given by the Caughey-Thomas

equation, as has been confirmed in the case of Si [23], can be selected for simulating 4H SiC.

At room temperature, it can be expressed as

ALPHAN

NREFN

MINMUNMUN.MAXMINMUN

+

+=total

nN

1

. -.0 µ Eq. 2.15

The parameter MUN.MAX (µmax) represents the mobility of undoped or unintentionally

doped samples, where lattice scattering is the main scattering mechanism, while MUN.MIN

(µmin) is the mobility in highly doped material, where ionized impurity scattering is

dominant. NREFN (Nref) is the doping concentration at which the mobility is halfway

between µmax and µmin, ALPHAN (α) is a measure of how quickly the mobility changes from

µmax to µmin, and Ntotal is the total doping concentration.

For N-type 4H SiC doped with nitrogen (N), detailed mobility data measurements

reported in [24, 25, 26, 27] are available for curve fitting. The resulting fit of Eq. 2.15 to the

experimental data at 300 K are shown in Fig.2-4, using µHall = µdrift [28], with the parameter

values listed in Table 2-I

2-12

Table 2-I Parameters of low field mobility (Eq. 2.15) for 4H SiC at 300K [28].

Parameter 4H SiC MUN.MIN 40 cm2/Vs MUN.MAX 950 cm2/Vs

NREFN 2x1017 cm-3

ALPHAN 0.76

Figure 2-4 Low field electron mobility as function of doping concentration in 4H SiC (perpendicular to the c-axis, T=300 K). The empirical best fit as shown in solid line is generated using Eq. 2.15 with parameter values given in Table 2-I [28].

2-13

2.3.3.2. High Field Effect

The effect of strong electric fields cause the carrier velocity to be no longer

proportional to the field, and thus no longer can be described by a field independent mobility.

Field-dependent mobility model is derived to account for carrier heating and velocity

saturation effects, and analytically expressed in terms of the drift velocity as a function of the

electric field in the direction of current flow, defining

EEvE d )( )( =µ Eq. 2.16

The effect of parallel field on the low drift electron mobility model as described in Eq. 2.15

uses an expression that is frequently used for modeling the field dependence of mobility of

silicon [23]:

BETANBETAN

VSATN

1

||,

,

1

+

=EnS

nSn

µ

µµ Eq. 2.17

Here µS,n is the low field mobility which may include the scattering mechanisms as will be

described in latter section, VSATN (vsat) is the saturation velocity, and BETAN (βsat) is a

constant that influence how abruptly the velocity goes into saturation.

Until now, only little temperature dependent high-field data for SiC had been

published. The only experimental data on this comes from Khan and Cooper [29], where the

drift velocity in epitaxial 4H SiC (n-doped to about 1.3 x 1017 cm-3) was measured as a

function of the applied electric field. A fit of Eq. 2.17 through the experimental high field

data by Khan and Cooper is shown in Fig. 2-5, which resulted in the parameter values as

listed in Table 2-II.

2-14

Table 2-II Parameters of the velocity field Eq. 2.17 for 4H SiC at two temperatures [29].

Temperature Parameter 23 °C 320 °C

µS,n 450 cm2/Vs 130 cm2/Vs VSATN 2.2x107 cm/s 1.6x107 cm/s BETAN 1.2 2.2

Figure 2-5 Drift velocity of electron (at 23 °C and 320 °C) in 4H SiC as functions of the applied field. An empirical best fit to these curves as shown in solid lines are generated using Eq. 2.17 with parameter values given in Table 2-II [29].

2-15

2.3.3.3. Anisotropy in Mobility

The hexagonal SiC substrates are typically cut perpendicular or offset a few degrees

to the c-axis of the crystal. Thus one needs to be concerned with the carrier mobility either

perpendicular to the c-axis (in direction of the basal of the crystal) or parallel to the c-axis,

depending on the device structure and operation. In all hexagonal type SiC polytypes, the

carrier transport properties exhibit an anisotropic behavior with regard to crystallographic

orientation in each polytype. Measurements of the electron mobility anisotropy in N-type 6H

and 4H SiC using the Hall effect and through MC calculations have been studied in [25, 30,

31, 32, 33]. These studies show an agreement of a ratio value of µ(1120)/µ(0001) ≈ 0.83 for 4H

SiC and it is temperature independent in homogeneous samples [26].

The high field mobility model (Eq. 2.17) expresses the dependence of carrier

mobility on the component of electric field that is parallel to the current flow. Due to

anisotropic behavior of SiC material, the effects caused by anisotropic in scattering need to

be included in the device model. In MEDICI, the so-called Anisotropic Material Advanced

Application Module (AM-AAM) can be used to model the anisotropic properties within

semiconductor materials. The carrier mobility tensor, (X, Y, Z), can be used in AM-AAM as

to model the anisotropic mobility behavior. This tensor is a dimensionless vector that

multiplies the normal carrier mobility as calculated using the selected mobility models. Thus

in the case of 4H SiC, a tensor of (1, 0.83, 1) is included in mobility model.

2.4. Channel-Carrier Mobility Parameters Extraction in 4H SiC MOSFET

In addition to the carrier mobility models for the bulk of semiconductor, several

mobility models for the insulator-semiconductor interfaces are also available in MEDICI. As

shown in [1] different channel mobility models can lead to different simulation results. This

shows the importance of channel mobility models and their parameter values in simulating

MOS devices. Moreover, the effect of charge trapping at interface states has been known as

the main reason for mobility reduction [34]. This effect is especially harmful in the case of

4H SiC MOS devices, due to the rapid increase of interface-trap density near the band edges

2-16

[35, 36, 37, 38]. Thus, apart from the mobility models and their parameters values, the

inclusion of energy distribution of interface-trap density is also important in modeling the

behavior of the electrical characteristics of SiC MOS devices. In this section, for the first

time, the applicability of channel mobility models implemented in MEDICI and SPICE

circuit simulator for SiC MOSFET will be analyzed. Measured interface-trap distribution

within the energy gap is used in MEDICI simulation. Best-fit model parameters are extracted

by comparing the simulated transfer characteristics and the corresponding field-effect

mobility with experimental data obtained from the substantially improved channel mobility

of 4H SiC MOSFETs, fabricated with a standard power-MOSFET processing [40].

2.4.1. 4H SiC MOSFETs

Along insulator-semiconductor interfaces, the carrier mobilities can be substantially

lower than in the bulk of semiconductor due to surface scattering. Even worst in the case of

SiC MOS devices. For years, the progress in SiC MOS devices has been hampered by

problems due to high density of interface traps within the energy gap, reflecting in very poor

channel-carrier mobility [38, 39] and oxide reliability [40, 41]. However, dramatic

improvements have recently been reported with nitrided SiO2–SiC interfaces [42, 43],

resulting in state-of-the-art 4H SiC MOSFET with improved reliability and high values of

inversion-layer mobility.

The planar N-Channel 4H SiC MOSFETs with circular width of 800 µm and

designed channel length ranging from 5 µm to 50 µm were fabricated using a non self-

aligned process. P- epitaxial layer with a nominal doping of 5x1015 cm-3, grown on P+ 4H

SiC substrate, was the starting material. The gate oxide was grown at Griffith University

using the following process: initial gate oxidation in pure NO at 1150 °C for 1 hour, the main

oxidation in dry O2 at 1150 °C for 5 hours, and interface nitridation by annealing in NO at

1150 °C for 1 hour. The resulting oxide thickness was 43 nm as determined from the

accumulation capacitance of the CV-curves measured at 1MHz. After the oxidation process,

the samples were sealed in a plastic container filled by nitrogen and shipped to SiCED,

2-17

Germany for further fabrication of the MOSFETs. The rest of the fabrication process is

described elsewhere [43].

The field-effect mobility was derived from the experimental ID-VGS characteristic,

using the following equation:

WVC

LVI

DSoxGS

D

∂∂

=µ Eq. 2.18

where L and W are the channel length and width, respectively, and Cox is the oxide

capacitance per unit area. The reduction ∆L of the designed channel length as the result of

technology processes was determined in [43]. Fig. 2-6 shows ID-VGS characteristic and the

effective mobility of the MOSFET as function of the gate voltage at VDS = 50mV.

2.4.2. MEDICI Channel Mobility Model

A model that combines Lombardi's surface mobility model [44] and impurity-

scattering term through the Matthiessen-rule is selected in this work [45]:

1

11−

+=

impurityuniversalS µµ

µ Eq. 2.19

Lombardi’s surface mobility model for µuniversal combines mobility equations for

semiconductor-insulator interface and for bulk semiconductor in the following way:

+=

−

bsrac

universal µµµ

µ ,11min1

Eq. 2.20

2-18

Figure 2-6 Measured transfer characteristic at VDS=50mV (a) and the inversion-layer mobility (b) of 4H SiC n-channel MOSFET with Ldesign/Wdesign=10µm/800µm.

2-19

where µb is the carrier mobility in bulk of the semiconductor as expressed in Eq. 2.15, µac is

the carrier mobility limited by lattice scattering (surface acoustic phonons), and µsr is the

carrier mobility limited by surface roughness scattering. In this model, the contributions of

various scattering mechanisms are separated, thus offering advantages in terms of initial

estimation of the model parameters, needed for any curve fitting.

The acoustic-phonon term, used in MEDICI, has the following form:

3

1

⊥⊥

+=ET

NE

totalac

α

µ CB Eq. 2.21

There are two fitting parameters, B and C, allowing to adjust the degree of mobility

reduction due to the electric field normal to the current flow and temperature, respectively.

Parameter αααα1 is a factor that indicates the dependency of the mobility term µµµµac on the

impurity concentration.

Surface roughness is known to cause severe degradation of the surface mobility at

high electric fields. The electron mobility term due to the surface-roughness scattering is

frequently expressed in the following way [44, 46]:

=

⊥2

DEsrµ Eq. 2.22

where D is the fitting parameter.

The impurity-scattering term in Eq. 2.19 (1/µimpurity) models the scattering of

minority carriers (inversion-layer electrons) by ionized impurity atoms (acceptor atoms) that

is screened by the net concentration of mobile carriers [45]. This term accounts for a

mechanism that becomes important when the channel-doping concentration is increased to

prevent punchthrough effects [47]. In this study, the contribution of µimpurity to the overall

2-20

mobility is insignificant and does not play an important role; therefore its parameters were

set to default values.

In the case of Si MOSFET, the existing surface scattering mobility model described

in the previous section have been validated [45], and implemented in many 2-D numerical

simulators e.g. MEDICI. The proposed best-fit parameter values (default) as the results of

comparison of the calculated drain conductance with a very large set of experiment data

points are given in Table 2-III. The surface-mobility parameters have not been studied for

4H SiC because of the erratic behavior of the inversion-layer mobility in the case of

MOSFETs with ordinary dry or wet oxides [42]. Recently made MOSFETs with nitrided

gate oxides [43] exhibit not only significantly increased mobility, but also low-field mobility

behavior that is similar to the case of Si MOSFETs (Fig.2-6). This indicates that it is possible

to use the existing mobility models by setting the parameter values. Accordingly, the

parameters B and C in Eq. 2.21, and the parameter D in Eq. 2.22 will be discussed in the

following section. The dependent impurity concentration model parameter (αααα1) is assumed

to be similar to the case of silicon.

2.4.3. MEDICI Channel Mobility Parameters Extraction

MEDICI two-dimensional device simulation program was used to determine the

surface-mobility parameters. Two-dimensional impurity profile was generated using the

same parameters as the experimental test MOSFET and material parameters for 4H SiC.

Generalized Mobility Curve (GMC) mobility model, available in MEDICI, was used as the

combination of low field and transverse field effects. Fig. 2-7 shows the cross section of the

test MOSFET generated with MEDICI.

2-21

Figure 2-7 N-channel MOSFET structure generated with MEDICI.

2.4.3.1. Interface-Trap Density

Fig. 2-8 shows the plot of typical measured interface-trap density (blank circles)

measured on MOS capacitors with nitrided gate oxides. Interface-trap density was measured

by the conductance technique [48] in dark shielded probe station. High temperature (250° C)

of the conductance measurement was necessary to activate the interface states that reside

deep in the 3.26 eV of the 4H SiC wide energy gap. Details on these measurements are

described elsewhere [48, 49]. As can be seen from Fig. 2-8, the measured interface-trap

density increases toward the conduction band edge.

Due to the nature of the measured interface-trap distribution and the limitation

imposed by 2-D device simulator (MEDICI) (20 equally spaced points of trapped

distribution within the energy gap), and for simplicity of the curve-fitting process, the

following analytical function was used:

( )( )

( )

>

−+

<

−+

=eV

eV

1.1exp

1.1exp

222

111

iC

CO

iC

CO

it

E-EEEDD

E-EEEDDED

ζ

ζ Eq. 2.23

2-22

Acceptor-like states are assumed because the equation relates to the upper half of the energy

gap. Plot of this equation with the parameter values that result in a good fit in the

subthreshold and weak inversion regions is shown in Fig. 2-8 (filled rectangles). The

parameter values are as follows: DO1=1.5x1010 cm-2 eV-1, DC1=1x1012 cm-2 eV-1, ζ1=0.138

eV, DO2=4x1010 cm-2 eV-1, DC2=5.7x1012 cm-2 eV-1, and ζ2=0.066 eV.

Figure 2-8 Plots of the interface traps distribution used in numerical simulation (filled rectangles) and of the measured data (blank circles).

2.4.3.2. Discussion on Model Parameters Extraction

The bulk carrier mobility has already been described in the previous section in

terms of its model and its parameter values. The two remaining mobility-reduction

mechanisms are surface roughness and acoustic phonon scattering. Assuming similar surface

roughness as in the case of Si, the surface-roughness degradation factor is very much related

2-23

to the processing parameters, therefore surface-roughness degradation parameter in 4H SiC

would be similar to the case of Si. Also, surface roughness scattering is known to strongly

degrade the surface mobility at high electric fields. Consequently, increasing the value of the

parameter D in the surface-roughness term would cause even sharper current decay with

increased gate voltage, therefore, an increased discrepancy between the high and low-field

regions. Therefore lower default value of 5.84x1014 V/s as proposed by Lombardi et al [44]

for parameter D seems to be appropriate.

In the case of the acoustic-phonon scattering, our sensitivity analysis shows that

variations in C result in proportional current variations over the entire gate-voltage range, i.e.

the shape of the mobility curve remains the same. In other words, C dominates µac, and

therefore µS above the threshold voltage. On the other hand, sensitivity analysis regarding

parameter B showed that its influence was limited to the region of low electric field.

The parameters B and C were fitted to achieve reasonable agreement between the

simulation and the experimental field-effect mobility data. The complete list of parameter

values, providing the good fit shown in Fig. 2-9, is listed in Table 2-III. Model parameters

from [28] are also included for convenience.

B and C were derived and estimated from the physical properties of the silicon

material, using the two-dimensional deformation potential theory of surface phonon

scattering and for a nondegenerate surface [44]. This derivation leads to the following

relationships between the coefficients B and C, and the effective conductivity mass: B α

*1

m and C α 2* )(1

m . To account for the difference in effective conductivity mass in the

case of 4H SiC [50], an initial adjustment was performed by multiplying the silicon-based

values for B and C *

*

SiC

Sim

m and 2

*

*

SiC

Sim

m , respectively. However, it was found that

further reduction in C parameter value is necessary in order to obtain a good fitting. The

extracted value for C is significantly smaller than the theoretically adjusted value. This could

be due to the effect of Coulomb scattering by the interfacial charge, which is independent of

the other scattering mechanisms as postulated elsewhere [37].

2-24

A good fit to the experimental data, as shown in Fig. 2-9, was obtained by

incorporating the effect of negatively charged acceptor-like interface traps according to the

measurement data of Fig. 2-8. An additional term of fixed positive interface charge with

density of 1.06x1012 cm-2 is used in the simulation to account for the residual shift in the

threshold voltage.

Table 2-III Parameters for 4H SiC MOSFET mobility models.

Eq. Parameter Unit Si (default) 4H SiC 2.15 µmin

a cm2/Vs 52.2 40 µmax

a cm2/Vs 1417 950 Nref

a cm-3 9.68 x 1016 2 x 1017 αa 0.68 0.76

2.21 B 8.95 x 105 1.0x106 C 3.23 x 106 1.74 x 105

α1 0.284 0.284 2.22 Db V/s 8.29 x 1014 5.82 x 1014

a :from Ref. [28], b :from Ref. [44]

2-25

Figure 2-9 Comparison of (a) transfer characteristics and (b) mobility between the experimental data and simulation with the extracted parameter values listed in Table 2-III.

2-26

2.4.4. SPICE Mobility Model

Due to its simplicity and semi-empirical nature, SPICE Level 3 model has been

proven to be more efficient than its predecessor models. It provides better accuracy, faster

simulation with less convergence problems, and quite straightforward parameter extraction

process. The mobility model in Level 3, incorporating the effect of the vertical field, is based

on the work by Schrieffer [51]:

0µ

αµ

11|| += E

v

Eq. 2.24

or expressed in the more familiar form:

)(1 tGS

v VV −+=

θµµ 0 Eq. 2.25

where µµµµ0 is the low field mobility, θθθθ is the effective reduction factor due to vertical field, and

Vt is the threshold voltage.

In SPICE Level 3, the subthreshold conduction was implemented as a separate

model, which is given by the following equation:

( ) nkTVVqonD

onGSeII /−= Eq. 2.26

where Ion is the drain current at VGS=Von, and Von is a modified threshold voltage that

depends on the value of one parameter — interface-trap density, NFS [52].

2.4.5. SPICE Parameters Extraction

The MOSFET parameters µµµµ0, θθθθ, and Vt were extracted from the strong inversion

regime of the transfer characteristic, measured at low drain voltage, using the following

drain-current equation:

2-27

( ) DStGStGS

oxD VVV

VVLCWI −

−+=

)(1 θµ0 Eq. 2.27

where W and L are effective channel width and length, Cox is the gate oxide capacitance per

unit area, and VGS and VDS are the gate- and drain-source voltages respectively. The values

for µµµµ0, θθθθ, and Vt were determined according to the method described in [53]. The extracted

low field mobility µ0 was 48.8 cm2/Vs with corresponding threshold voltage of 0.5 V and

mobility-reduction factor of 0.034 V-1 as shown in Fig. 2-10. The extracted mobility-

reduction factor is considerably smaller compared to Si MOSFETs [52]. This indicates that

the low value of low-field mobility in the MOSFET is a result of high density of interface

traps that are close to conduction band.

The subthreshold characteristic of the MOSFET is shown in Fig. 2-11 for VDS = 50

mV, along with SPICE simulations with different NFS values. The drain current of the

fabricated MOSFET increases exponentially with a subthreshold slope of 104 mV/decade.

According to [54] this subthreshold slope results in interface state density of 2x1011 cm-2/eV

(for the case of substrate doping concentration of 5x1015 cm-3 and gate oxide capacitance of

Cox=8x10-7 F/cm2). A reasonable fit is obtained with NFS of 3.5x1011 cm-2/eV as shown with

the solid line in deep subthreshold region. However, it exhibits much worse discontinuity of

the first derivative, as compared to the case of Si MOSFET [52], in the region where the gate

bias is slightly larger than the threshold voltage. This transition region, which is the region

between the fully on and the subthreshold region, is very much dominated by the interface

traps that are close to the conduction-band edge [37, 38]. The NFS value has to be increased

gradually as a function of the gate bias, as shown in Fig. 2-11 by the dotted and dashed lines,

in order to achieve a good fit in the transition from subthreshold to above-threshold regions.

2-28

Figure 2-10 Comparison of (a) transfer characteristic and (b) mobility between the experimental data and SPICE simulation with µ0=48.8 cm2/Vs, Vt =0.5 V, and θ=0.034 V-1.

VDS=50 mV

2-29

Figure 2-11 Subthreshold characteristics of the MOSFET and from SPICE simulations.

2.5. Summary

In this chapter, the important material parameter set for 4H SiC device simulation in

MEDICI 2D-simulation program has been compiled from literature data. The associated

parameters of the most important models in unipolar devices simulation described in this

chapter, are given in Table 2-IV.

Regarding channel mobility-parameters extraction, a good fit with experimental

data of lateral n-channel 4H SiC MOSFET was achieved in MEDICI and SPICE circuit

simulators. Based on the measured data of interface-trap density, the effect of increasing

interface-trap density toward the edge of the conduction band is incorporated in MEDICI

simulation. A slight adjustment in the mobility parameter values was necessary, most likely

VDS=50 mV

2-30

due to different physical properties of 4H SiC and Coulomb scattering by the interfacial

charge. The results demonstrate that both MEDICI and SPICE simulators, with the already

existing mobility models, can be used for design and optimization of 4H SiC MOSFETs and

the circuits utilizing these MOSFETs.

Table 2-IV Parameters for 4H SiC used in device simulation.

Parameter Units 4H SiC Ref. Dielectric constant ε -- 9.66 [8] Intrinsic concentration ni (300 K)

EG300 (Eg) eV 3.22 [9] ni cm-3 6.67x10-9

Energy gap narrowing (BGN) V.BGN V 9x10-3 [1] N.BGN cm-3 1017 [1] CON.BGN -- 0.5 [1]

Low field electron mobility (300 K) MUN.MIN (µmin) cm2/Vs 40 [28] MUN.MAX (µmax) cm2/Vs 950 [28] NREFN (Nref) cm-3 2x1017 [28] ALPHAN (α) -- 0.76 [28]

High field electron mobility (300 K) VSATN (vsat) cm/s 2.2x107 [29] BETAN (β) -- 1.2 [29]

Anisotropy in mobility µ(1120)/µ(0001) -- 0.83 [25]

Avalanche generation N.IONIZA (an) cm-1 1.66x106 [8] ECN.II (bn) V/cm 1.273x107 [8] P.IONIZA (ap) cm-1 3.25x106 [15] ECP.II (bp) V/cm 1.79x107 [15]

2-31

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2-33

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2-34

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2-35

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3-1

NOVEL SiC ACCUMULATION-MODE POWER MOSFET

3.1. Introduction 3-1 3.2. Power MOSFETs in SiC 3-3

3.2.1. Material Advantages of 4H SiC for Power Devices 3-4 3.2.2. Trends in SiC Power MOSFETs 3-10 3.2.3. Review of Existing ACCUFET structures 3-14

3.3. SiC Novel ACCUFET: Device Structure and Operation 3-20 3.4. Analysis and Optimization of Device Parameters 3-21

3.4.1. Simulation Parameters and Models 3-21 3.4.2. Peak Trench Region Concentration 3-22 3.4.3. P-base Layer Thickness 3-25 3.4.4. Thickness and Concentration of N-Channel Epilayer 3-27

3.5. Comparison-Based Evaluation of the Novel Structure 3-29 3.5.1. Electrical Performance 3-29 3.5.2. Discussion on the Device Structures 3-30 3.5.3. Device Processing Considerations 3-32

3.6. Summary 3-34 References 3-36

3.1. Introduction

Since the early 1980s, silicon metal-oxide-semiconductor field-effect transistor

(MOSFET) has become the most widely used semiconductor device in low voltage/power

applications and in very large scale integrated circuits. This is due mainly to the facts that

the MOSFET has simpler structure, cost less to fabricate, and consumes less power than its

bipolar transistor counterpart. The inherent MOSFET advantages make this class of devices

Chapter

3-2

an attractive direction for development of power devices for higher voltage/power ratings [1,

2].

Due to excellent physical and electrical properties, such as high breakdown electric

field, wide bandgap, high thermal conductivity, and high electron saturation velocity, silicon

carbide offers great potential for development of high temperature, high power, and high

voltage devices. Significant progress in SiC power MOSFETs have been demonstrated

recently, with the fabrication of UMOS [3], DMOSFET [4], triple-implanted vertical

MOSFET [5], RESURF MOSFET [6], and accumulation-mode MOSFETs (ACCUFETs) [7,

8, 9]. Recent ACCUFET developments [7-9] reveal important advantages of this type of

MOSFET structure. ACCUFETs emerge as the preferred solution for power MOSFETs on

SiC, because of their advantage in terms of higher channel-carrier mobility compared to the

standard inversion N-type MOSFETs. However, recent results from these devices indicate

that the full potential of SiC material for power MOSFET devices has not been fully utilized

yet. That gives an indication that more work needs to be done in device development in

parallel with the more fundamental work on materials and processing issues.

It is the aim of this chapter to propose a new design of accumulation-mode power

MOSFET on SiC, designed to circumvent limitations appearing in many SiC MOS device

structures. It begins with an overview of the silicon power MOSFET, the drift and channel

regions analysis of Si and 4H SiC ideal power MOSFETs, and the review of the current

state-of-the-art in SiC power MOSFET. This will be followed by the main focus of this

chapter, the introduction of new design of accumulation-mode power MOSFET and its

optimization using MEDICI two-dimensional device simulator. Simulation-based

comparison of the proposed structure with other ACCUFET approaches, namely planar [7]

and trench-gate [8] ACCUFETs are also presented. As identical model parameters and

simulation conditions are used, this comparison enables illustration and analysis of the

inherent advantages and strengths of the ACCUFET structures themselves. The relevant

technological issues, related to the considered ACCUFET approaches, are qualitatively

discussed in the final section.

3-3

3.2. Power MOSFETs in SiC

Power switches can be considered as the heart of all power electronic systems. The

increased power capabilities, ease of control, and reduced costs of power switches have

made power electronic systems affordable in a large number of applications. The first power

switches were thyristors and bipolar transistors developed in 1950’s. Thyristors were used in

higher power systems because their ratings were scaled at faster pace than bipolar transistors.

Bipolar transistors were favored for low and medium power applications because of their

faster switching capability. The ratings of these devices grew steadily until the late 1970s,

the year in which the first power MOSFETs introduced [10].

Since the introduction of the first power MOSFETs, Si power MOSFETs have been

immensely improved and have become the dominant device technology since 1980s for

many applications for many reasons. First, MOSFET has a very high input impedance due

to its MOS gate structure hence provides the simplest gate drive requirements. The creation

of either inversion layers or accumulation layers under the MOS channel can be controlled

using integrated circuits because of the small gate current that is required to charge and

discharge the high input gate capacitance. Second, MOSFET is a majority carrier device

hence there is no minority charge storage involved in its operation. Switching time for the

MOSFET is dictated by the ability to charge and discharge the input capacitance. No storage

time is encountered, and current rise and fall times can be very rapid. This results in faster

switching operation. Third, compared to bipolar transistors the MOSFETs has superior

ruggedness and forward biased safe operating area (FBSOA) which allows elimination of

snubber circuits for protection of the switch during operation in typical hard-switching

applications. Fourth, as the majority carriers in silicon exhibits increasing resistivity with

temperature, the thermal runaway behavior is avoided in MOSFETs. MOSFET devices are

formed as parallel combinations of many thousand of individual MOSFET cells to take

advantage of the thermal behavior. Any device carrying excess current will heat up and

become more resistive, diverting current into parallel paths. Excessive loss still produces

thermal failure in MOSFET, but there is no unstable runaway effect if the parasitic BJT does

not act.

3-4

Due to these excellent electrical characteristics, it would be desirable to utilize

power MOSFETs for high voltage/power electronic applications. However, the blocking

voltage capability of the MOSFET is based on the ratings of the reverse body diode of the

drift region. This blocking voltage is determined in part by the distance from source to drain.

High blocking voltage capability implies high resistance because of the geometry, so there is

trade off between low drift region resistance, Ron-drift, values and device voltage capability.

This trade off between low on-state resistance and the device voltage capability prevents its

advantages in high voltage/power electronic applications as illustrated in the following

section.

3.2.1. Material Advantages of 4H SiC for Power Devices

Power MOSFETs differ from conventional MOSFETs primarily in having a low-

doped and thicker drift region at the drain to support a large blocking voltage when the

MOSFET is in its off state. Therefore both drift and channel resistances are considered as the

major contribution to the specific on-resistance in any standard power MOSFET. Neglecting

the resistances associated with the ohmic contact, the JFET, and 2-dimentional effects, the

specific on-resistance, Ron-sp, in any standard power MOSFETs can be expressed as,

Ron-sp = Rchannel + Ron-drift Eq. 3.1

In the case of ideal MOSFET, i.e. Ron-sp = Ron-drift, the drift region analysis can be

performed to express the relation between the specific on-resistance (Ron-sp) and the blocking

voltage capability (VB) of a MOSFET. By approximating the depletion layer in the drift

region as an abrupt one-dimension junction, and it is uniformly doped; the doping level NB

required to support a given breakdown voltage VB and depletion width WD at breakdown can

be calculated as follows [11]:

) 2(

2

B

crB Vq

EN ε= Eq. 3.2

3-5

c

BD E

VW 2= Eq. 3.3

The specific on-resistance associated with the drift layer to support VB is

bulkcr

B

bulkB

D

EV

NqW

µε

µ

4

) (

R

3

2

drift-on

=

=

Eq. 3.4

where εr is the relative permittivity of the semiconductor, µbulk are the drift region mobilities,

Ec is the critical electric field of the semiconductor, and VB is the blocking voltage. The

denominator (εµEc3) has been referred to as Baliga’s Figure of Merit (BFOM) which can be

used to compare the relative performance of various semiconductor materials for power

device fabrication [12].

In general, both the mobility µn (µbulk of electrons) and the breakdown electric field

are dependent on NB. In Si, the well-known dependence of electron mobility and the

breakdown field on the doping concentration can be used [13].

91.015

91.018

10 x 75.3 9210 x 10.5

B

Bn N

N+

+=µ Eq. 3.5

A closed form analysis which requires the solution of ionization integral, using the electric

field distribution for an abrupt junction diode, is used for calculating expression for NB and

WD as a function of the breakdown voltage [14]. From this analysis, NB and WD for the case

of Si are obtained as [15]

33.118 10 x 01.2 −= BB VN Eq. 3.6

3-6

167.1-6 10 x 58.2 BD VW = Eq. 3.7

Substituting Eq. 3-6 and Eq. 3-7 in Eq. 3-4 and using room-temperature mobility for low

doping levels, Ron-drift in the case of Si can be expressed as

5.2-9drift-on 10 x 98.5R BV= Eq. 3.8

In case of 4H SiC, the dependence of µn on NB at room temperature that has been

described in the previous chapter (section 2.3.3, Eq. 2-15), can be used in this analysis and

derived as

76.013

76.016

76.0

17

10 x 41.1 4010 x 28.1

x1021

91040B

B

Bn N

NN +

+=

++=µ Eq. 3.9

The dependency of the breakdown field strength of 4H SiC on NB was determined from the

calculated values of Ec in 4H SiC P+-N junctions [16] as reviewed in the previous chapter

(section 2.3.2). The empirical relationship between Ec4H SiC and NB was obtained as (see Fig.

2-3):

Ec4H SiC = 1.64 x 104 (NB)1/7 Eq. 3.10

From these derivations, the drift region analysis for ideal power MOSFET can be

performed in terms of the drift region: thickness, concentration, mobility, and the specific

on-resistance, as a function of breakdown voltage. Table 3-I provides values of NB, WD, µn

and Ron-sp of an ideal generic power MOSFETs on Si and 4H SiC as a function of breakdown

voltage.

3-7

Table 3-I Values of doping concentration, electron mobility, drift layer thickness, and specific on-resistance as a function of breakdown voltage for ideal 4H SiC and Si power MOSFETs at room temperature condition.

Breakdown Voltage, VB

(V)

Doping Concentration, NB

(cm-3)

Electron Mobility, µn

(cm2/Vs)

Thickness, WD

(µm)

Specific On-resistance, Ron-sp

(Ω cm2)

4H SiC 200 3.74 x 1017 388.95 0.75 3.23e-6 500 1.04 x 1017 606.54 2.26 2.24e-5 1000 3.93 x 1016 745.55 5.19 1.11e-4 5000 4.13 x 1015 905.05 35.83 5.98e-3 10000 1.57 x 1015 928.11 82.32 3.50e-2

Silicon 200 1.72 x 1015 1351.92 12.48 3.35e-3 500 5.06 x 1014 1356.50 36.34 3.30e-2 1000 2.01 x 1014 1357.86 81.59 1.88e-1 5000 1.84 x 1013 1359.60 659.88 10.48

As mentioned in the previous section, the carrier mobilities along insulator-

semiconductor interfaces can be substantially lower than in the bulk of semiconductor due to

surface scattering. Even worst in the case of SiC MOS devices, which exhibit large density

of interface traps within the energy gap, which results in lower channel mobility and cannot

be neglected. The inclusion of channel resistance in Ron-sp – VB analysis in the case of generic

SiC power MOSFET, can be performed by adding an additional term Rchannel as expressed in

Eq. 3-1. The Rchannel term can be described using the following drain-current equation:

( ) DStGSchox

D VVVLCWI

−= µ Eq. 3.11

)(

R channeltGSch VVCoxW

L−

=µ

Eq. 3.12

3-8

where W and L are effective channel width and length, Cox is the gate oxide capacitance per

unit area, µch the channel mobility and VGS and VDS are the gate- and drain-source voltages

respectively. Fig. 3-1 shows the result from the drift region analysis as listed in Table 3-I.

The inclusion of channel resistance in 4H SiC power MOSFET analysis are also included,

for the case of W=30 cm, L=2 µm, Tox= 50 nm, (VGS-Vt)=10 V, and µch is varied form 50

cm2/Vs to 200 cm2/Vs.

Figure 3-1 Calculated specific on-resistance of 4H SiC power MOSFET using channel mobilities ranging from 50 to 200 cm2/Vs and ideal case of Si power MOSFET.

This analysis suggests that in spite of higher inversion channel mobility in Si

MOSFETs, 4H SiC MOSFET would have lower specific on-resistance, due to much higher

breakdown field. As shown in Fig. 3-1, the specific on-resistance of the ideal Si power

MOSFET increases very rapidly with increasing breakdown voltage. This is because in Si in

order to support high-drain electric field, the doping concentration of the drift region, NB,

3-9

needs to be reduced and its thickness, WD, has to be increased as seen in Table 3-I. Thus, in

spite of the ability to obtain nearly ideal specific on-resistance with Si power MOSFET

devices, they are not suitable for applications that required breakdown voltages above 200 V

due to their high specific on-resistance.

The introduction of insulated gate bipolar transistor (IGBT) in the 1980’s, resolved

the problem of utilizing full controlled silicon power device in high voltage/power electronic

applications. The IGBT device can be described as a MOSFET that is connected to the base

of a bipolar transistor in a Darlington configuration, hence can be classified as a voltage

controlled device. However, unlike the MOSFET, the switching speed of the IGBT is limited

by the time taken for removal of the stored charge in the drift region due to injection of holes

during on-state current conduction. Thus has limited operational frequency.

The superiority of 4H SiC illustrated in this section is just one of the potential

projections in using this wide semiconductor material for high power devices. Other

potential projections of SiC for power switching devices were clearly demonstrated several

years ago with the calculated figures of merit as listed in Table 3-II. These advantages in

terms of calculated figure of merits provide a motivation for the design and development of

power devices on SiC. Despite the unique problems in device fabrication, which many are

not yet totally resolved, promising progress in the device development has taken place in the

area of power MOSFETs. The following sections review some of the best-reported SiC

power MOSFETs from the literatures.

Table 3-II Normalized figures of merit of polytypism in SiC material for high voltage power

devices [17].

Material λ KM λ(vsat/εr)1/2

JM (vsatEc/π)2

QF1

λσA

QF2

λσAEc

BFOM εrµEc

3 BHFM µEc

2

Si 1 1 1 1 1 1 1 3C SiC 3 1.6 65 100 400 33.4 10.3 4H SiC 3 4.61 180 390 2580 130 22.9 6H SiC 3 4.68 260 330 2670 110 16.9

3-10

3.2.2. Trends in SiC Power MOSFETs

The development and publication of Baliga figure of merit (BFOM) [11] is

considered as the impetus for much of the current interest and activity in SiC power devices.

This publication came at a time when single crystal SiC wafers were becoming commercially

available from Cree Research, Durham, NC, USA. The confluence of these two factors

initiated the recent increase in SiC development activity in Europe, Japan, United States, and

Australia.

Due to the slow diffusion rates for dopants in SiC, it is not practical to fabricate a

MOSFET structure using a diffusion process such as double diffused MOSFET (DMOS).

The first 6H [18] and 4H SiC [19, 20] power MOSFETs were introduced by Palmour et al

(Cree Inc.) in the form of trench gate structure (UMOS) as shown in Fig. 3-2 (a). The UMOS

structure contains P-base region, which is epitaxially grown on N-drift layer and a gate

region that can be fabricated by using trench-etching process. With this process, the UMOS

cell size can be made relatively small hence results in an increase in the channel density and

elimination of the JFET component of the resistance. However, it was found that the

breakdown voltage of these first 6H SiC UMOSFETs was limited to under 100 V due to

rupture of the gate oxide. On the other hand, the 4H SiC UMOSFETs in [19] and [20] had

blocking voltages of 150 V and 250 V, respectively and specific on-resistance of 33 mΩcm2

and 18 mΩcm2, respectively. More recently Agarwal et al [3] (Northrop AG) introduced a

subsequently improved 4H SiC UMOSFET devices with a blocking voltage above 1kV.

However, these devices were found to have a high specific on-resistance of 74 mΩcm2 in

spite of using high gate drive voltages of up to 60 V, due to the poor channel inversion layer

mobility along the trench sidewalls. One of the problems with the UMOS structure is the

high-electric-field stress that occurs at the corner of the trench [21]. Given that the electric

field in the oxide is about three times higher than in the underlying semiconductor, oxide

failure at the trench corner is a persistent limitation.

In an attempt to minimize the drawbacks in SiC UMOS structure, Shenoy et al [4]

(Purdue Univ.) proposed a planar gate structure using ion implantation to form the P-base

region, also known as DIMOS, shown in Fig. 3-2 (b). From this experiment it was found that

3-11

devices fabricated using 6H SiC can sustain a blocking voltage of 760 V with a high specific

on-resistance of 125 mΩcm2 due to contribution of the channel, drift, and JFET region

resistances. A Modified structure of DIMOS, so-called TIMOS structure was later proposed

by Peters et al [5] (Siemens Inc.), which employed triple implantation processes. In contrast

to the DIMOS structure, the ion implantation to form the P-wells in TIMOS was performed

in two steps. First ion implantation is done to form the P-wells that act as reverse diode

required for blocking behavior of the MOSFET. The second one defined the P-base for the

inversion channel, which laterally extends the first P-wells by the channel length. In the

second implant the dopant concentration increases from a low surface concentration of

7x1016 cm-3 to 1x1018 cm-3 in a depth of 0.4 µm. This resulted in a device that is able to

withstand 1800 V, with a significant improved specific on-resistance of 84 mΩcm2.

In an attempt to increase the blocking voltage beyond the theoretical limit imposed

on vertical power structures by the thickness of commercially available epilayers (≤ 15 µm),

a lateral structure of DIMOS (LDIMOS), was firstly proposed by Spitz et al [22] (Purdue

Univ.). In this structure, the depletion region was extended laterally over a semi-insulating

4H SiC substrate as shown in Fig. 3-2 (c). This device exhibits a blocking voltage of 2.6 kV

with a very high specific on-resistance, owing to light doping of the epilayer. Saks et al [23]

(Naval Research Lab.) proposed an improved lateral device in terms of specific on resistance

by using reduced-surface-field (RESURF) design principles. This RESURF lateral MOSFET

was fabricated on 6H SiC wafer as shown in Fig. 3-2 (d). The device had a specific on

resistance of 57 mΩcm2 with a much-reduced blocking voltage of 600 V due to the gate

oxide breakdown [24]. One of problems in DIMOS based structures is their high specific on-

resistance. Low inversion channel mobility and JFET region resistances are the major

contributions to their high on-resistance. The low inversion channel mobility in DIMOS

structures can be related to the formation of P-wells by ion implantation process [25, 26, 27].

Table 3-III summarizes the best-reported performances for inversion-type power

SiC MOSFETs. As can be seen from the table, there is a progressive improvement in

blocking voltage of SiC power MOSFETs. Although very encouraging, these improvements

in blocking voltage need to be accompanied by reductions in specific on-resistance to utilize

3-12

the full potential of SiC material. Encouraging method to overcome the problems associated

with the poor inversion layer leads to the development of device structure called the

ACCUFET as will be discussed in the following section.

(a) UMOS structure

(b) DIMOS structure

3-13

(c) LDIMOS structure

(d) LDIMOS RESURF structure

Figure 3-2 Inversion-type power SiC MOSFET structures.

3-14

Table 3-III Summary of best-reported performances for inversion-type power SiC

MOSFETs.

Device (Group)

Blocking Voltage, VB

(V)

Specific On-resistance, RON-sp

(mΩcm2) spON

B

RV

−

2

(MWcm-2)

Reference

UMOS (Cree) 150 33 0.68 [19] UMOS (Cree) 260 18 3.8 [20] UMOS (Northrop)a 1100 74 16.4 [3] UMOS (Northrop)a 1400 74 26.5 [28] DIMOS (Purdue) 760 125 4.6 [4] TIMOS (Siemens) 1800 84 38.6 [5] LDIMOS (Purdue) 2600 -- -- [22] LDMOS RESURF (Cree) 600 57 6.3 [24]

a :same device with improvement made.

3.2.3. Review of Existing ACCUFET Structures

One of the most important parameters of a FET is its threshold voltage, Vt, which

separates the above-threshold regime (VGS > Vt), where the charge induced in the device

channel is proportional to the gate voltage, and below-threshold regime (VGS < Vt). Looking

to the cross section of the basic MOS structure shown in Fig. 3-3 (a) as an example, a thin N-

type region is formed below the MOS gate and on top of the P-type substrate. In the case of

carefully chosen thickness of N-type layer, such that it is completely depleted by the built-in

potentials of the P/N junction and the MOS gate at zero gate bias. Below threshold, this

potential barrier effectively turns off the channel conduction current, resulting in a normally

off condition. The height of the barrier, which determines the transistor off current, and

hence its on-to-off current ratio, is largely determined by the semiconductor energy gap as

shown in Fig. 3-3 (b). In the below-threshold regime, the gate bias changes the height of the

barrier separating the source and drain, and, therefore, the current depends exponentially on

the gate bias. SiC P/N junction is expected to be able to support a much higher voltage, due

to much higher energy gap. In the above-threshold regime, when a positive gate bias is

3-15

applied, an accumulation channel is created at the interface. This results in a low resistance

path for the electron current flow from the source to the drain. This type of MOSFET is

normally referred to as accumulation-mode MOSFET (ACCUFET). In the case of power

ACCUFETs, the existence of P/N junction in the drift region supports the entire drain

voltage hence the device is expected to have a high blocking voltage.

Figure 3-3 (a) Cross section of basic structure accumulation-mode MOSFET, (b) schematic conduction band profiles in the channel of MOS below threshold, illustrating the barrier between the source and drain at zero drain bias. The barrier heights shown are proportional to the energy gap for Si and 4H SiC, respectively.

3-16

Due to higher accumulation layer mobility [29, 30] as compared to inversion layer

mobility, ACCUFETs emerge as the preferred solution for power MOSFETs on SiC. A

novel planar device structure named planar ACCUFET, also known as Accu-DMOSFET,

was for the first time proposed by Shenoy et al [7] (NCSU Univ.). In this structure as shown

in Fig. 3-4 (a), a subsurface P+ implant is used to create a thin n layer below the gate oxide.

A single high-energy boron implantation is used in formation of the buried P-base region.

The depth of the P buried layer in this designed structure is so crucial, in a way to create the

N layer above it completely depleted at zero gate bias by the built-in potential of the P/N

junction. The results from the un-terminated device on 6H SiC had a breakdown of 350 V

with leakage current of < 100 µA just before breakdown. A room temperature specific on-

resistance of 18 mΩcm2 was measured at a gate bias of 5 V [7].

Another type of ACCUFET based on UMOS structure was reported for the first

time by Onda et al [8] (Denso, Inc.). A cross section of the structure is shown in Fig. 3-4 (b).

The devices reported to have blocking voltage of 450 V and specific on-resistance of 23.84

mΩcm2. As in inversion-type UMOS structures, the ACCUFET UMOS posses low blocking

voltages because of the high electric field stress on the gate oxide. A more recently

improved ACCUFET UMOS structure fabricated from 4H SiC was reported in [32].

Employing a new method to circumvent the high electric field stress to the trench corner, this

device is expected to withstand a much higher blocking voltage.

Table 3-IV summarizes the best-reported performances for accumulation-type

power SiC MOSFETs. As can be seen from the table, the ACCUFETs structure shows a

much promising result in terms of their specific on-resistance compared to the inversion N-

type UMOS and DIMOS structures.

3-17

(a)

(b)

Figure 3-4 Cross section of (a) Planar ACCUFET and (b) UMOS ACCUFET.

3-18

Table 3-IV Summary of best-reported performances for accumulation-type power SiC

MOSFETs.

Device (Group)

Blocking Voltage, VB

(V)

Specific On-resistance, RON-sp

(mΩcm2) spON

B

RV

−

2

(MWcm-2)

Reference

Planar (NCSU) 350 18 6.8 [8] UMOS (Denso)a 450 23.84 8.5 [7] UMOS (Denso)a 450 10.9 18.6 [31] UMOS (Purdue)b 850 27 26.8 [32] UMOS (Purdue)b 1400 15.7 125 [32]

a, b :same device with improvement made.

Fig. 3-5 shows the overall plot of the best performance SiC MOSFETs that has been

progressively improved over the last 9 years as listed in Table 3-III and 3-IV. As can be seen

from the plot, more work needs to be done to reduce the specific on-resistance and increase

the blocking voltage capability in SiC power MOSFETs. The emergence of ACCUFET

structures in SiC reveals important advantages in terms of higher channel-carrier mobility.

However improvement in the blocking voltage capability is still very much needed in this

type of MOSFET structure. The following section introduces a novel ACCUFET structure

that is designed to overcome problems associated with premature breakdown and low

channel mobility.

3-19

Figure 3-5 Specific on-resistance and breakdown voltage for SiC power MOSFET reported to date.

3-20

3.3. SiC Novel ACCUFET: Device Structure and Operation

The basic cell structure of the novel ACCUFET is shown in Fig. 3-6. In this

structure, a thin N-channel surface epilayer is grown on the top of P-base epilayer, and a

narrow trench is etched around each MOSFET cell. The trench region is ion-implanted to

form the thin N-type region that acts as part of the drift region (path) for the conduction of

electrons from the source to drain. At zero gate bias, there is no path for conduction of

electrons because the top N-channel epilayer is completely depleted by the built-in fields,

created by the P-base–N-channel epilayer junction and the gate electrode. This results in a

normally off device at zero gate bias with the drain voltage mostly supported by the N-drift

region. When a positive gate bias is applied, an accumulation channel of electrons is created

at SiO2–SiC interface. This results in a low resistance path for the electron current, which

flows from the source through the channel, then down to the drain through the trench and the

drift region.

Figure 3-6 Novel SiC ACCUFET structure.

3-21

The main feature of this accumulation type MOSFET is the N-type channel,

epitaxially grown on P-base region. The two epilayers provide independent control of the

doping concentration and thickness of the N-channel and P-base region. Therefore, by

varying the thickness and doping concentration of these two epilayers, as well as the

underlying N-drift region, a power MOSFET with optimum blocking voltage, on resistance,

and threshold voltage can be designed. Another important feature relates to the fact that a

planar MOS structure, created on high-quality epitaxial layer, is utilized with this approach.

As a result, many of the open issues related to reliability of MOS interface in SiC can be

addressed.

3.4. Analysis and Optimization of Device Parameters

Five parameters, characteristic of the new structure, are chosen to analyze the

relationship between blocking and driving capability of the novel ACCUFET. These

parameters are peak doping concentration of ion-implanted trench region, doping

concentration and thickness of P-base epilayer, and doping concentration and thickness of N-

channel epilayer.

3.4.1. Simulation Parameters and Models

Two-dimensional numerical-simulation structure (including the mesh, the

boundaries, and the impurity profiles) for the device was generated in MEDICI, using the 4H

SiC parameters provided in Table 2-IV, section 2.5. As no detailed model and parameters for

the accumulation-mode carrier mobility along the insulator–semiconductor interface have

been reported for SiC. A mobility degradation factor of 50% was used to account for

scattering effects at the interface. Resulted in the actual channel carrier mobility of around

100 cm2/Vs, which is in the range of the published results [29, 30]. It should be noted,

however, that the contribution and the conclusions in this chapter do not rely on quantitative

results. The methodology used in this chapter (simulation and comparison of ACCUFET

approaches) focuses on the merits of the device structure itself, independent of the specific

parameter values, which are still dominated by different technology imperfections.

3-22

Due to symmetry of the device, only half of the device structure was evaluated. The

simulated structure has a fixed 10 µm thick N-drift region doped at 1.0x1016 cm-3, an N+ type

polysilicon gate electrode with an 80 nm thick gate oxide (QF=1.0x1011 cm-2), a channel

length of 2.0 µm, and a half cell pitch of 10 µm.

The simulation results were used to calculate Baliga’s Figure of Merit (BFOM) as

the criterion for structure optimization and comparison. BFOM is given by [15],

ON

2B

RVBFOM = Eq. 3.13

where RON is the on resistance and VB is the maximum operating voltage which is set either

by the avalanche-breakdown voltage, punchthrough voltage, or the drain-to-source voltage

that corresponds to the maximum set oxide field, EOX, of 3 MV/cm.

3.4.2. Peak Trench Region Concentration

The first step in optimizing this MOSFET was to determine the peak trench region

concentration that will provide optimum blocking capability and on resistance of the device.

Since the N-type trench region has to be formed by ion implantation into the P-base layer,

i.e. the peak concentration of the ion-implanted trench region has to be set higher than the P-

base background concentration (NA), the background concentration of the P-base epilayer

has to be optimized accordingly. Three background concentrations of 6.0x1016 cm-3, 1.0x1017

cm-3, and 1.5x1017 cm-3 of 2.0 µm thick P-base epilayer were simulated, and the peak

concentration of the ion-implanted region was varied from 6.3x1016 cm-3 to 9.0x1016 cm-3 for

NA= 6.0x1016 cm-3, from 1.05x1017 cm-3 to 1.5x1017 cm-3 for NA=1.0x1017 cm-3, and from

1.575x1017 cm-3 to 2.25x1017 cm-3 for NA=1.5x1017 cm-3.

From the simulations results shown in Fig. 3-7, it was found that the maximum

blocking voltage was achieved with NA=1.0x1017 cm-3 and with a slightly higher peak trench

region concentration of 1.05x1017 cm-3 (this value was used as the closest reasonable value to

the P-base concentration of 1.0x1017 cm-3). The maximum operating voltage in this region

3-23

(P-base concentration of 1.0x1017 cm-3) is determined by the maximum oxide field set at

EOX=3 MV/cm. An increase in the peak trench region concentration causes the maximum

oxide field to occur at lower drain voltage. For the case of NA=1.5x1017 cm-3, avalanche

breakdown occurring in the trench region determines the blocking capability of the device.

On the other hand, punchthrough breakdown determines the maximum operating voltage

when the P-base background concentration is equal to 6.0x1016 cm-3. Although the N-

channel epilayer is fully depleted in off mode, in the case of low NA, the depletion-layer

fields of the P-base–N-channel junction and the gate are not strong enough to shield the high

electric field from the drain, resulting in punchthrough breakdown. In addition to that, the

maximum oxide field increases as NA is decreased, because the compensating effect of the

built-in field is reduced.

To summarize, the peak concentration of the ion-implanted trench region strongly

influences the maximum operating voltage of the device. To obtain the maximum operating

voltage, the peak concentration of the ion-implanted trench region has to be slightly higher

than the background concentration of the P-base epilayer. The concentration of the P-base

epilayer itself cannot be set too low due to punchthrough breakdown and increasing oxide

field, as the compensating effect of the built-in electric field is reduced.

However, it is not the maximum operating voltage alone, but rather the figure of

merit for power devices that is used to optimize the considered parameters. This involves the

on resistance of the device, which is decreased as the peak concentration of the trench region

is increased. As Fig. 3-7 shows, the best trade-off between the breakdown voltage and on

resistance requirements in terms of Baliga Figure of Merit (BFOM) is achieved with the

peak trench region concentration of 1.4x1017 cm-3.

3-24

Figure 3-7 Effects of peak trench-region concentration (Npeak) on maximum operating voltage, on-resistance, and BFOM. WN=0.4 µm, ND=1x1016 cm-3.

3-25

3.4.3. P-base Layer Thickness

The thickness of the P-base epilayer is important, because it determines the

depth/length of the trench region, which in turn affects the gate oxide field, breakdown

voltage, and on resistance. The effects of the P-base layer thickness (WP) on maximum

operating voltage, on resistance, and BFOM of the device are shown in Fig. 3-8. In this

simulation, the optimum values of the parameters considered in the previous section are

used. With P-base concentration of 1.0x1017 cm-3 and peak trench region concentration of

1.4x1017 cm-3, punchthrough breakdown limits the thickness of the P-base epilayer to

minimum value of WP=1.2 µm. On the other hand, avalanche breakdown determines the

blocking capability of the device for WP ≥ 2.2 µm. The region of 1.2 µm ≤ WP ≤ 2.2 µm is

selected for detailed analysis and search for the optimum value. As for the region of WP ≥ 2.2

µm is not of interest because the on resistance increases rapidly due to increasing length of

the trench region.

As shown in Fig. 3-8, an increase of the P-base thickness from 1.2 µm to 2.2 µm,

leads to increase of the maximum operating voltage from 500 V to just below 1700 V. The

maximum electric field of 3 MV/cm in the oxide appears as the limit to the maximum

operating voltage over this range of P-base thickness, except for the case of WP=2.2 µm

where its value is limited by the avalanche breakdown. The device on resistance also

increases over this range of P-base thickness. The graph in Fig. 3-8 shows that the P-base

epilayer thickness of 2.0 µm is the optimum value in terms of BFOM.

3-26

Figure 3-8 Effects of P-base thickness (WP) on maximum operating voltage, on-resistance, and BFOM. The difference between Npeak and P-base concentration is set to 4x1016 cm-3; WN=0.4 µm and ND=1x1016 cm-3, NA=1x1017 cm-3.

3-27

3.4.4. Thickness and Concentration of N-Channel Epilayer

In this section, the effects of varying thickness (WN) and doping concentration

(NCH) of the N-channel epilayer were investigated. The results are shown in Fig. 3-9. The

dashed line indicates the punchthrough limit: the punchthrough current through the N-

channel epilayer becomes too large when NCH is increased beyond the dashed line for a

given WN. Left of the dashed line, the maximum gate oxide field (set at 3 MV/cm)

determines the maximum operating voltage with the exception of WN=0.3 µm and high NCH

values, where the avalanche breakdown before the maximum gate oxide field is reached. Fig.

3-9 also shows the dependence of the on resistance on WN and NCH. As can be observed, an

increase in NCH does not have much effect on the on resistance, because majority of the

current flows through the accumulation layer at the interface. Nonetheless, increasing WN

reduces the on resistance, this being due to a decrease in the threshold voltage of the device.

The maximum BFOM value of 6.3x105 V2/Ω is achieved with 0.5 µm thickness and 8.0x1015

cm-3 concentration of the N-channel epilayer.

Overall, the maximum BFOM value of the simulated device is achieved with 2.0

µm P-base epilayer doped at 1.0x1017 cm-3, ion-implanted trench region with peak

concentration of 1.4x1017 cm-3, and N-channel epilayer concentration and thickness of

8.0x1015 cm-3 and 0.5 µm, respectively.

3-28

Figure 3-9 Effects of Nepi-channel concentration and thickness (WN) on maximum operating voltage, on-resistance, and BFOM. WP=2.0 µm, ND=1x1016 cm-3, NA=1x1017 cm-3.

3-29

3.5. Comparison-Based Evaluation of the Novel Structure

In this section, the novel structure is compared to two alternative ACCUFET

approaches, referred to in the further text as planar and trench-gate ACCUFETs. The

specific structures, selected to represent the planar and the trench-gate approaches, were

published in [7, 33] and [8], respectively as described in section 3.2.3. It should be

emphasized that the same models and parameters were used in the MEDICI device simulator

to obtain and compare the performance characteristics of all the simulated structures.

3.5.1. Electrical Performance

The simulated structures of the alternative ACCUFETs are shown in Fig. 3-4

(section 3.2.3). Due to symmetry of all the compared device structures, only half of the

device cells are shown. The trench-gate structure has been extensively investigated and

applied to 6H SiC [34, 35, 36, 37]. Recent development in trench-gate ACCUFETs on 6H

SiC demonstrated a device that is capable of withstanding voltage of 450 V with a low on

resistance of 23.84 mΩ cm2 [8]. The design concept of the trench-gate approach is

schematically illustrated in Fig. 3-4 (b). The main feature of this structure is that the N-

channel region is epitaxially grown on the trench sidewall to form the MOS structure. The

electron current flows through accumulation channel formed at the trench sidewall, from the

source towards the drain contact. The planar ACCUFET approach is illustrated in Fig. 3-4

(a). In this structure, a thin N-type epilayer is grown epitaxially over a P+-type region,

implanted into N-type drift layer. The ion-implanted P+ buried region separates the thin

epitaxially grown N-type and the thicker N-drift layer. The electron current flows laterally

through the accumulation channel formed at the surface of top N-type region, and then

vertically towards the drain contact through the opening between the P+ buried regions

(JFET region). It has been shown that the optimized device has a 2.0 µm separation distance

between the P+ regions [7, 33]. The crucial device parameters that have been established in

Ref. [8] and Ref. [7, 33] for the trench-gate and planar structure approach, respectively, are

used in this simulation and analysis. The thickness and impurity concentration of the trench-

gate ACCUFET sidewall epilayer were 0.3 µm and 1x1016 cm-3, respectively [8]. The

3-30

thickness and impurity of the planar ACCUFET P-base implanted region were 0.5 µm and

1x1020 cm-3, respectively, and the thickness and impurity of the channel epilayer were 0.6

µm and 1.0x1016 cm-3, respectively [7]. However, in order to enable meaningful

comparison, the common parameters are set to identical values: all of the compared

structures are set to have a drift region thickness and concentration of 10 µm and 1.0x1016

cm-3 respectively, channel length of 2.0 µm, an N+-type polysilicon gate electrode over an 80

nm thick gate oxide (QF=1.0x1011 cm-2), an N+ region concentration of 1.0x1020 cm-3, and a

Gaussian doping profile with characteristic width of 0.15 µm (where applicable). No other

optimization was done in trench-gate and planar ACCUFET structures beyond those already

performed in Ref. [8] and Ref. [7, 33] respectively.

The obtained current−voltage characteristics for VDS=1 V are shown in Fig. 3-10,

and they were used to calculate the on resistances. Additional simulations were performed to

obtain the maximum operating voltages, so that the figures of merit could be calculated. The

results for on resistance, maximum operating voltage and figures of merit (BFOM) are listed

in Table 3-V. The results show clearly that the new ACCUFET structure enables a BFOM

value 2.25 higher than the trench-gate and the planar approaches.

3.5.2. Discussion on the Device Structures

Fundamentally, the trench-MOS device was proposed for its low on resistance and

relatively high blocking capability compared to other MOSFET devices [38, 39, 40]. As

shown by the simulation results, the trench-gate ACCUFET has the smallest on resistance,

but also the lowest breakdown voltage as compared to the others. The major contribution to

the on resistance in the trench-gate structure comes from the channel resistance Rchannel and

the drift region resistance Rdrift. In terms of the breakdown voltage, the avalanche breakdown

limits its blocking capability, due to the localized high electric field near the trench base

level.

3-31

Gate Voltage (V)

0 1 2 3 4 5 6

Dra

in C

urre

nt (A

/µm

)

0

1x10-6

2x10-6

3x10-6

4x10-6

Trench-Gate

Novel

Planar

VDS=1V

Figure 3-10 Comparison of simulated transfer characteristics.

Table 3-V Comparison of ACCUFET structures.

Structure On resistance (Ω) (@VGS=5V, VDS=1V)

Max. Operating Voltage (V)

BFOM (V2/Ω)

Novel 3.69 1530 6.3x105 Planar 5.49 1215 2.7x105

Trench-Gate 2.80 870 2.7x105

3-32

Focusing on the planar device, let us note first that the ion-implant process involved

limits the thickness of P-base region. Hence, to achieve a high blocking voltage, the P+

region has to be implanted with a high dose. However, the high concentration of the P+

region creates a high electric field in the depletion region across the P−N junction (JFET

region), where the avalanche breakdown is more likely to occur. It should also be mentioned

that this built-in potential plays a shielding role, reducing the electric field stress of the oxide

and limiting the electron current in off mode. The distance between the P+ regions

determines the tradeoff between the on resistance and the breakdown voltage. Small opening

between the P-base regions results in a device with high breakdown voltage and high on

resistance, while wider opening will result in lower breakdown voltage and lower on

resistance. A good tradeoff between these requirements was achieved with 2.0 µm separation

distance of the buried P+ region [7, 33]. As shown in Table 3-V, the planar structure has a

medium blocking voltage capability and the highest on resistance.

In the case of the novel structure, the peak concentration of ion-implanted trench

region influences its performance in an analogous way to the separation distance of the JFET

region in the planar device. The ion-implanted trench region determines the opening for the

electron current path. The ability to control the thickness and concentration of the P-base

epilayer in the novel device gives an advantage in terms of tailoring the device electrical

performance.

In calculating the on resistance, the channel width was set to 10 cm for the novel

ACCUFET structure. To compensate for the effect of a wider unit cell of the novel structure,

the on resistance of the trench and planar structures were reduced by the half-cell pitch ratio

of 10.5/10.

3.5.3. Device Processing Considerations

The analysis and comparison presented in the previous section are focused on the

device structures, and to distill the device-structure effects, any process-related differences

are removed by selecting equal parameters for all the structures considered. This section

addresses the main process-related effects in a descriptive manner.

3-33

A disadvantage of the trench structure is due to the fact that the gate oxide is grown

on a slopped surface. Although Fig. 3-4 (b) shows this surface as vertical, in reality the angle

is 70o [8]. It was shown that the problems can be alleviated by deposition of an epilayer on

the etched surface [8], however, there are inherent problems with the slopped surface: (1) it

was shown that epilayers grown on slopped surfaces exhibit terrace profile [41], (2) the

defects from the reactive ion etching (RIE) used to create this surface could affect the quality

of the epilayer [42, 43, 44, 45], and (3) anisotropic oxidation rates [46] result in non-uniform

oxide when grown on a slopped surface [47]. All these factors adversely affect the gate oxide

and its interface with the silicon carbide, in particular in terms of the oxide reliability [48,

49].

In the case of the planar ACCUFET approach, the P-base region is formed by high-

dose ion implantation of boron, a process that may leave damage in the top 0.2-0.25 µm

region from the surface [50]. The channel, epitaxially formed over the damaged region [25,

26, 27], would exhibit increased leakage current between the source and drain. The fact that

the P+ region is formed by ion implantation is also related to inability to independently

control its thickness and doping. However, this effect is included in the simulation results

presented in the previous section.

The quality of the channel region in the novel ACCUFET is not compromised by

these process-related issues. The solution for the channel region offers not only more robust

technology, but also additional comparative advantages in electrical performance, such as

oxide reliability and channel carrier mobility. To clarify this statement, it should be

emphasized again that the simulation results given in the previous section are for identical

technological parameters, including channel carrier mobility.

3-34

3.6. Summary

The attractive features of MOS-gate structures as a switching power device and

physical limitation of silicon have led to a significant progress in the development of SiC

MOSFETs. Blocking voltages as high as 2 kV have been achieved in the inversion type of

SiC MOSFETs (DIMOS). However, these types of SiC MOSFET suffer from high specific

on resistance due to low channel mobility. The advent of accumulation type of MOSFET has

shown more promising results in terms of their specific on resistances. Although their

specific on resistance results are encouraging, their blocking voltages are quite low due to

premature breakdown phenomena.

The novel design structure of accumulation-mode MOSFET (ACCUFET) for high

power applications has been proposed and analyzed in MEDICI. The characteristic

parameters (the peak trench region concentration, the thickness and concentration of the P-

base layer, and the thickness and concentration of the N-channel epilayer) were analyzed in

terms of their influences on the on resistance and maximum operating voltage. The results

can be summarized as follows:

• The peak concentration of the ion-implanted trench region strongly influences the

breakdown voltage and on resistance of the device. Setting the peak concentration

slightly higher than the background concentration of the P-base epilayer provides

maximum operating/blocking voltage, however the on resistance suffers due to low net

carrier concentration in the trench region. On other hand, increasing the peak

concentration of the trench region reduces the maximum operating voltage of the

device.

• The doping concentration and the thickness of the P-base region are the most important

design parameters for determining the blocking voltage and on resistance of the novel

device. Decreasing the P-base doping concentration below 1.0x1017 cm-3 decreases the

blocking capability of the device due to the punchthrough in the P-base epilayer. On

the other hand, the maximum operating voltage is limited by the maximum oxide field

(set at 3 MV/cm), when the p-base concentration is increased to 1.0x1017 cm-3. If

3-35

increased further, the maximum operating voltage becomes limited by the avalanche

breakdown. The best tradeoff between these requirements is achieved by setting the P-

base background concentration at 1.0x1017 cm-3, and the peak trench concentration at

1.4x1017 cm-3. Due to reasonably high net carrier concentration in the trench region,

changing the thickness of the P-base epilayer does not change the on resistance

significantly. However, it does change the maximum operating/blocking voltage of the

device. The maximum BFOM value was obtained with P-base thickness of 2.0 µm.

• The concentration of N-channel epilayer has the least effect on the on resistance, due to

the appearance of accumulation layer at the surface. However, its thickness has

significant effect on the on resistance (due to the shift in the threshold voltage) and on

the maximum operating voltage (due to punchthrough in the channel).

• The following optimum values have been established: channel thickness and

concentration of 0.5 µm and 8.0x1015 cm-3 respectively, P-base epilayer thickness and

concentration of 2.0 µm and 1.0x1017 cm-3 respectively, and trench region ion-

implanted peak concentration of 1.4x1017 cm-3.

The simulation based evaluation of the novel ACCUFET included comparison to

trench-gate and planar ACCUFETs, as representatives of two alternative approaches. Given

that a number of ACCUFETs, based on the alternative approaches, were manufactured and

the electrical characteristics were published, our simulation-based comparison could focus

on the merits of each of the considered structures. Finally, relevant technological issues were

considered in qualitative terms.

3-36

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4-1

NOVEL ACCUFET IN SWITCH-MODE POWER SUPPLY SYSTEM

4.1. Introduction 4-1 4.2. Characteristics of SiC ACCUFET and Si VDD MOSFET 4-3

4.2.1. Device Structures 4-3 4.2.2. Device Parameters 4-5

4.3. Circuit Simulation 4-7 4.3.1. Circuit Topology 4-7 4.3.2. Circuit Simulation Results 4-9

4.4. System Benefits 4-14 4.4.1. Circuit Size Reduction 4-14 4.4.2. Superior Thermal Management 4-15

4.5. Summary 4-18 References 4-19

4.1. Introduction

Power semiconductor devices play a crucial role in the regulation and distribution

of power and energy systems. By some estimates, more than 60 percent of all power utilized

in day-to-day life flows through at least one power device and more often through multiple

devices [1]. Consequently, the performance of power devices has a significant impact on the

efficient use of electricity. Moreover, the improvements in the system performance in terms

of efficiency, size, and weight are driven by enhancements made in power device

characteristics. Enhancements in the maximum operating frequency and temperature

management of a power device are needed to reduce the size, weight, and cost of power

Chapter

4-2

electronic systems. Conduction and switching losses ultimately determine the operating

frequency for a given circuit topology and device package (thermal management approach).

The introduction of MOS-gate structures in silicon has changed the way power

electronic systems are designed. The ability to integrate the drive circuits for MOS-gate

power devices has led to a reduction in size and weight of the systems that has enabled

greater market penetration [1]. However, the growth and demand in power device

applications in many aspects of life has made the silicon power device technology come to a

point of its limitation. This, not only leaves the important applications unserved (e.g.

applications that require switching of high power at relatively high frequencies), but also

limits possible further improvements in today power electronic system performance.

As mentioned earlier, among other wide energy gap semiconductor materials, SiC is

a very promising candidate as replacement of silicon in high power switching applications.

Its wide energy gap and high thermal conductivity suggest that power devices made from

SiC can be used under severe environment, e.g., in high temperature conditions. Its high

thermal conductivity and high breakdown electric field suggest that the integration of SiC

devices can be done in higher packaging density and, thereby, results in a power device with

reduced power losses and die size.

In spite of the superiority of SiC MOSFETs, the high cost of the starting material is

hindering the pace of their commercialization at present. However, the performance

advantages of SiC MOSFETs can be utilized to achieve significant cost reduction at the

circuit level. As to date, rare experimental data is available on the switching characteristics of

SiC devices, especially for SiC MOSFETs in typical inverter applications that can be used to

deduce significant advantages at circuit level. This chapter, therefore, aims to investigate the

possibility to reduce the cost and the size of switch-mode power supplies by utilizing the

advantages of 4H SiC ACCUFET.

4-3

4.2. Characteristics of SiC ACCUFET and Si VDD MOSFET

4.2.1. Device Structures

In this chapter, in evaluating the switching performance of SiC and Si MOSFET

power devices in a typical inverter circuit, the novel 4H SiC ACCUFET and the

conventional Si Vertical Double Diffused MOSFET (VDD MOSFET) structures [2, 3] are

chosen.

The VDD MOSFET structure was chosen as the successful high-voltage structure

in Si technology [2, 3, 4]. The cross section of a half of a unit cell for Si VDD MOSFET is

shown in Fig. 4-1(a). The VDD MOSFET was based upon the diffusion of the P-base and N+

source regions using the edge of the polysilicon as a masking boundary. The P-base region is

diffused deeper than the N+ source, and the difference in the lateral diffusion between the P-

base and N+ source regions defines the channel region. In this particular case, the N+ and P-

base diffusions are taken to be fixed at 1 µm and 3 µm respectively, thus giving a 2 µm

channel length. In addition, a complete gate-drain overlap is utilized, which results in

depletion regions from adjacent p-well merge to form an almost parallel plate depletion

region across the entire active area. This way the blocking voltage characteristics of the

device is improved (close to the ideal breakdown voltage) and the channel-drain spreading

resistance is reduced [3].

As mentioned in previous chapter, the main feature of the novel ACCUFET is the

epitaxially grown N-type channel and P-base region. It provides independent control of the

doping concentration and thickness of the N-channel and P-base region. Therefore, by

varying the thickness and doping concentration of these two epilayers, as well as the

underlying N-drift region, a power MOSFET with optimum blocking voltage, on resistance,

and threshold voltage can be designed. The cross section of the novel SiC ACCUFET is re

shown in Fig. 4-1(b) for convenience.

4-4

(a)

(b)

Figure 4-1 Cross-sections of (a) VDD MOSFET and (b) novel ACCUFET.

4-5

4.2.2. Device Parameters

Two-dimensional numerical-simulation structures (including mesh, the boundary,

and impurity profiles) for the two devices were generated in MEDICI. The models and

parameters provided in Table 2-IV, section 2.5 were used for the 4H SiC and default

parameters as described in [5] for the Si MOSFET. Due to symmetry of the devices, only

half of each device structure was evaluated. Both devices had N+ type polysilicon gate

electrode with 80 nm thick gate oxides, channel length of 2.0 µm, half cell pitch of 8.5 µm,

and peak concentration of 1x1020 cm-3 for both the N+ and the P+ regions. The two structures

were designed to have equal breakdown voltage of ~700 V. The basic parameters of the Si

VDD MOSFET that result in breakdown voltage of 680 V are as follow: WD=50 µm,

WP=1.5 µm, P base concentration of 4x1016 cm-3, and N- drift region concentration of

2.5x1014 cm-3. On the other hand, the basic parameters of the 4H SiC ACCUFET, resulting

in the same breakdown voltage of 680 V, are as follows: WD=10 µm, WP=1 µm, P base

concentration of 1x1017 cm-3, N- drift region concentration of 2x1016 cm-3, and N channel

concentration of 1x1016 cm-3. As the aim of this paper to compare 4H SiC and Si power

devices of the same current rating and breakdown voltage, and channel width of the Si VDD

MOSFET was set at Wdesign =30 cm, the channel width (Wdesign) of the 4H SiC ACCUFET

was adjusted to ensure the same current rating as the Si VDD MOSFET.

The transfer characteristics for both devices, obtained by MEDICI simulations, are

shown in Fig. 4-2. Fig. 4-2 also shows the transfer characteristics obtained with the extracted

SPICE parameters (determined by using the method described in [6]) and the SPICE models

that will be used for circuit simulations. Table 4-I summarized the device parameters used in

the simulation for Si VDD MOSFET and 4H SiC ACCUFET that results in equal device

rating.

4-6

Figure 4-2 Transfer characteristics of Si VDD MOSFET (a), and 4H SiC ACCUFET (b).

4-7

Table 4-I Summary of device parameters for Si VDD MOSFET and 4H SiC ACCUFET having the same device rating.

Device parameter Si VDD MOSFET 4H SiC ACCUFET Oxide thickness, tox (nm) 80 80 P+ and N+ peak concentration (cm-3) 1x1020 1x1020 Drift region thickness, WD (µm) 50 10 Drift region concentration (cm-3) 2.5x1014 2x1016 P base thickness, WP (µm) 2.5 1 P base concentration (cm-3) 4x1016 1x1017

Gate length, Ldesign (µm) 2 2 Gate width, Wdesign (cm) 30 2.05

4.3. Circuit Simulation

4.3.1. Circuit Topology

In order to compare the performance of these two power devices in power

electronic systems, we take the example of a basic boost converter as embedded in most of

the existing first stage front-end converter used in distributed power system (DPS)

applications as shown in Fig. 4-3. The first stage of the front-end converter in DPS

application uses the power factor correction (PFC) technique with modular input power

levels of up to 1 kW. The single switch boost PFC rectifier in continuous conduction mode

(CCM) is the preferred topology due to its small ripple inductor current and the least

complexity [7]. In continuous conduction mode of operation of the boost converter under

what may be called constant frequency PWM control, the switch is closed every T seconds,

and opened dkT seconds later in the kth cycle (0 < dk < 1, where dk represents the duty ratio

in the kth cycle), while a positive inductor current is maintained, i.e., IL(t) > 0. The circuit is

intended to provide a nominal 400 V regulated output from an ac voltage in the range of 85–

264 V at the rectifier input. Fig. 4-4 shows the simplified circuit of the single switch boost

PFC rectifier. Many of the elements in the circuit, such as the bridge rectifier, the snubber,

and voltage- or current-feedback loop are removed to simplify the circuit simulation and to

4-8

focus on the switching function of the circuit. In this application, the losses must be

minimized to provide high efficiency that enhances system performance and reliability

without adding circuit complexity.

OrCAD PSPICE circuit simulator was used for the analysis [8]. As already

mentioned, the simplified circuit in Fig.4-4 was designed to operate in continuous-

conduction mode with inductor ripple current of 5 A. and output ripple voltage of 1.5 V. The

inductor and the capacitor values were adjusted to ensure the designed ripple current and

voltage, according to the operating frequency with fixed duty cycle of 50%. As for the

rectifier, the SPICE model for the BYT12P-600 diode [8] was used.

Figure 4-3 Basic configuration of a distributed power system [7].

4-9

Figure 4-4 The simplified boost PFC circuit.

4.3.2. Circuit Simulation Results

As in any PWM circuits, the gate-source and gate-drain capacitances (CGS + CGD),

of a power MOSFET must be charged and discharged by the gate drive circuit to enable the

switching. Fig. 4-5 (a) shows the basic gate charge waveform of a MOSFET. As can be seen

from the figure, as the VGS increasing, at particular voltage in which the MOSFET starting to

turn on (VGS = VDS), the gate-drain capacitance (CGD) increased drastically. Fig. 4-5 (b)

shows the variation in CGD with the voltage across it due to the variation in the depletion-

layer width [9, 10]. It was determined in Section 4.2.2 that the active area of SiC ACCUFET

is much smaller, consequently resulting in much smaller CGD capacitance.

4-10

Figure 4-5 (a) Basic gate charge waveform; (b) variation in CGD capacitance with VDS [9].

Fig. 4-6 shows the circuit waveforms obtained by simulations of the circuit in Fig.

4-4 with the following parameters and values of the other circuit elements: Vin=200 V,

L=0.4 mH, C=10µF, R=270 Ω, Vout=400 V, and operating frequency of 50 KHz. As can be

seen in Fig. 4-5 (a), the gate drive waveforms of the circuit with the Si VDD MOSFET show

plateaus during the turn-on and turn-off transitions. These plateaus, which are the

temporarily clamped gate-source voltage as the entire gate current iG is charging and

discharging CGD as indicated in Fig. 4-5. Thus, give a significant contribution to the

switching losses of Si MOSFET as shown in Fig. 4-6. As the drop/rise rate of drain-source

voltage, dVGS/dt, is determined by the value of iG/CGD [9], the instantaneous power loss in the

Si MOSFET shows high peaks especially during turn-off transitions, when the inductor

current at its highest peak.

For the same output impedance of the gate driving circuit, due to a small value of

CGD capacitance in SiC ACCUFET, there is no sign of plateaus happening in the gate

waveforms, i.e. negligible Miller effect. As can be seen from Fig. 4-7, VDS transitions are

much sharper and the switching losses are insignificant.

4-11

(a)

Figure 4-6 Waveforms of the circuit from Fig. 4-4 with Si VDD MOSFET.

4-12

(b)

Figure 4-7 Waveforms of the circuit from Fig. 4-4 with SiC ACCUFET.

4-13

The average switching losses for both MOSFETs as functions of operating

frequency up to 50 KHz. are shown in Fig. 4-8. As can be seen in Fig.4-8, the average power

losses at very low frequency are about the same for both devices. However, as the operating

frequency is increased, the switching loss of the circuit with the Si VDD MOSFET increased

significantly.

Figure 4-8 Average power losses.

The overall efficiencies of the circuit with SiC ACCUFET and Si VDD MOSFET

are shown in Fig. 4-9 as functions of the operating frequency. As can be seen the operating

frequency can be increased by an order of magnitude (for the same efficiency) by utilizing

4H SiC ACCUFET as the power switch.

4-14

Figure 4-9 Efficiency of the boost converter as a function of frequency.

4.4. System Benefits

4.4.1. Circuit Size Reduction

In the real device design, the breakdown voltage of the switching power devices can

be traded for device speed or on resistance, or both. An optimization in device speed leads to

an increase in operating frequency of the system. An increase in operating frequency brings a

number of system benefits, one of them being a reduction in volume and weight associated

with the passive components. This benefit is particularly important in power electronic

systems that normally require discrete capacitors and inductors for energy storage, filtering,

and other critical functions in the circuit. The limitation on energy storage in these

components tends to make them very large in volume compared to the semiconductor

devices. A simple way to decrease the volume of the passive components is to increase the

4-15

operating frequency. However, to achieve a higher operating frequency of a system, a

number of requirements have to be considered (i.e. system efficiency, electromagnetic

interference, and losses due to parasitic components).

Given that the SiC ACCUFET power switch was designed to have similar

breakdown voltage and on-resistance as the Si VDD MOSFET, the design resulted in a

thinner drift region and much-reduced terminal capacitances of the structure. As can be seen

from Fig. 4-9, the system efficiency of 87% corresponds to approximately 50 kHz for the

circuit with the Si VDD MOSFET and 0.5 MHz for the case of SiC ACCUFET. This 10

times improvement in system operating frequency will result in much smaller magnetic and

capacitive elements used for energy storage in the system, hence much lower system cost. It

may also enable to integrate the passive components into a packaged module, which is

essential for achieving higher power density [7].

4.4.2. Superior Thermal Management

Thermal management in electronic systems plays an important role in controlling

the reliability of electronic devices, especially the semiconductor devices. In addition, the

temperature increase above a certain level (referred to as the maximum junction temperature,

TJmax) increases the intrinsic carrier concentration above a critical level, causing loss of the

semiconducting properties. This effect relates to additional advantage of utilizing SiC power

devices in switching power supply systems. Due to a wide SiC energy gap, that is

approximately 3 times wider than in Si, the maximum junction temperature (Tjmax) of SiC is

projected to be approximately 3 times higher than Si (refer to Fig. 2-1). Thus, SiC-based

devices are more tolerable to temperature increases as it has been demonstrated in [11, 12,

13].

To illustrate the impact of this effect on the system, we can compare the system

with Si VDD MOSFET and SiC ACCUFET. Let us assume that the operating frequency is

very low (at the low frequency limit shown in Fig. 4-8) so that both devices dissipate power

of 16W. Let us also assume that they are both packaged in the same case type (TO-220), and

that each is attached to an aluminum heat sink with a thermal compound as illustrated in

4-16

Fig.4-10. The relationship between the power dissipation (Pdie) and the junction temperature

(TJ) for the case heat transfer to the surrounding medium (the ambient temperature, TA)

through a package and heat sink with thermal resistances of θJC (junction to case), θCS (case

to heat sink), and θSA (heat sink to ambient) can be expressed as follows:

SACSJCdie

AJ

PTT θθθ ++=

− Eq. 4.1

Figure 4-10 Example of thermal model of power electronic package scheme.

Since both packages have the same case and thermal compound, we can assume θJC

and θCS to be the same and equal to 1.25 0C/W and 0.1 0C/W [14] respectively. Choosing the

ambient temperature in the system to be 30 0C, and in order to maintain the Si VDD

MOSFET device junction temperature below its critical level (TJmax of 150 0C), let us assume

TJ=100 0C, which corresponds to TJ=290 0C in the case of SiC ACCUFET. Substituting

these values into Eq. 4.1, the needed thermal resistances for the heat sink are obtained as

Device

θSA

θCS

θJC Case

Heat sink

Pdie

TJ

TC

TJ

Ambient TA

4-17

θSA=3.025 0C/W and θSA=14.9 0C/W for Si VDD MOSFET and SiC ACCUFET,

respectively. The heat sink to ambient thermal resistance, θSA, depends on the sink area and

thickness, and the heat removal scheme. For the simplest case of one-dimensional heat

transfer by convection, it is given by:

hASA1=θ Eq. 4.2

where A is the cross sectional area of the sink and h is the convection heat transfer

coefficient, which in the range of 3 – 12 W/m2K (typical 5) for free air convection mode

[15]. Therefore the resulting heat sink areas under this condition are 0.066 m2 and 0.0134 m2

for the Si VDD MOSFET and SiC ACCUFET, respectively. Assuming square geometry,

these values correspond to about 25.7 cm x 25.7 cm and 11.6 cm x 11.6 cm, respectively,

which is approximately 55 % size reduction in the heat-sink area. This reduction in the size

of the heat sink is another benefit at the system level, enabling smaller size, reduced weight,

and lower cost of the system.

Another way to illustrate the beneficial effects of the SiC device in thermal

management of the system, is by looking at the scheme employed in the thermal

management. Using the thermal analysis as described above, one can chose between two

types of appropriate cooling techniques i.e. free air convection and forced air convection

schemes. For free air convection scheme the heat transfer coefficient, h, is in the range of 3

to 12 W/m2K, and for forced air convection scheme it is in the range of 10 to 100 W/m2K

[15]. Doing the same analysis as described above, for the same area of the heat sink (e.g.

0.0134 m2), the resulting heat transfer coefficients for Si VDD MOSFET and SiC

ACCUFET are 24.63 W/m2K and 5 W/m2K, respectively. This means that for the same size

of heat sink (13 cm x 13 cm), the Si VDD MOSFET would require a fan, while the SiC

ACCUFET can operate with free-air cooling.

4-18

4.5. Summary

The analysis provided in this chapter demonstrates that the efficiency of high-

voltage power supplies can be dramatically improved by using 4H SiC ACCUFET as the

switching device, instead of the standard Si VDD MOSFET. This is especially significant at

high switching frequencies where the power efficiency of the circuit with the Si VDD

MOSFET collapses. The SiC ACCUFET enables efficiencies and operating frequencies of

the simple system (i.e. boost rectifier) that can only be achieved by using more complex and

expensive circuit topologies (i.e. quansi-resonant circuits) when the Si VDD MOSFET is

utilized. The capability to operate at high frequencies without degradation in power

efficiency and with simpler circuit solutions provides incentive and opportunity for

commercialization of SiC MOSFETs. Moreover, the capability to raise the junction

temperature 3 times for the same power dissipation allows the weight and cost of the heat

sink to be reduced by 50%. The reduction in size, weight, and numbers of passive/active

component brings cost reduction that provides a compensation for the higher cost of the SiC

MOSFET.

4-19

References

[1] B. J. Baliga, “Trends in power semiconductor devices”, IEEE Trans. Elect. Dev., vol. 43,

p. 1717, 1996.

[2] S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and

VMOS power transistors,” IEEE Trans. Elect. Dev., vol. ED-27, p. 356, 1980.

[3] V. A. K. Temple and P. V. Gray, “Theoretical comparison of DMOS and VMOS

structures for voltage and on-resistance,” in IEDM Tech. Dig., p. 88, 1979.

[4] A. Murray, H. Davis, J. Cao, K. Spring, and T. McDonald, “New power MOSFET

technology with extreme ruggedness and ultra-low RDS(on) qualified to Q101 for

automotive applications”, Internatioal Rectifier, URL: http://www.irf.com

[5] Technology Modeling Associates, Inc., TMA MEDICI Two-Dimensional Device

Simulation Program Ver. 2.3, MEDICI User’s Manual, vol. 1, 1997.

[6] G. Ghibaudo, “New method for the extraction of MOSFET parameters,” Elect. Lett., vol.

24, p. 543, 1988.

[7] F. C. Lee et al, “Topologies and design considerations for distributed power system

applications,” Proc. of the IEEE, vol. 89, no. 6, p. 939, 2001.

[8] OrCAD Release 9.0 PSPICE, OrCAD, Inc., 1998.

[9] M. Brown, Practical Switching Power Supply Design, San Diego: Academic Press, Inc.,

1990.

[10] I. K. Budihardjo, P. O. Lauritzen, and H. A. Mantooth, “Performance requirements for

power MOSFET models,” IEEE Trans. Power Elect., vol. 12, p. 36, 1997.

[11] S. M. Savage, A. Konstantinov, A. M. Saroukhan, and C. I. Harris, “High temperature

4H-SiC FET for gas sensing applications”, Mat. Sci. Forum, vols. 338-342, p. 1431,

2000.

[12] S. H. Ryu, R. Singh, and J. W. Palmour, “High-power p-channel UMOS IGBT’s in 6H-

SiC for high temperature operation”, Mat. Sci. Forum, vols. 338-342, p. 1427, 2000.

[13] http://www.lerc.nasa.gov/WWW/SiC/redhot.html

4-20

[14] ST Microelectronics, Data sheet for power MOSFET component series: STP5NC70Z-

STP5NC70ZP- STP5NC70Z-1, 2000.

[15] R. R. Tummala, E. J. Rymaszewski, Microelectronics Packaging Handbook, New

York: Van Nostrand Reinhold, 1989.

5-1

CONCLUSIONS AND RECOMMENDATIONS

5.1. Conclusions

This thesis has sought to make tangible contributions towards the design and

application of MOS-based power switching devices in silicon carbide. A novel structure

designed to address both the problems of premature oxide breakdown and low channel

mobility as the outcome of a systematic study of SiC MOS-based device research is

proposed. Progress in characterization, optimization, and application of the novel SiC

ACCUFET by ways of analytical investigations, numerical device simulations, and circuit

simulation have been made. These are identified as the areas where the most contributions

could be made, and most efforts were directed along those lines.

Parameter extraction for numerical device simulation of 4H SiC unipolar devices is

the first major topic developed in this thesis. Using 2D numerical device simulation

(MEDICI), in the models describing electronic devices, the material parameters of Si are

replaced by the respective parameters of 4H SiC reported in literature. Based on a physically

based mobility model for Si MOS devices, for the first time, the channel carrier mobility

parameters in the presence of experimentally measured interface-trap density for an

inversion channel 4H SiC MOSFETs are extracted. A good fit with experiment data of state-

of-the-art 4H SiC MOSFET was achieved by MEDICI, and SPICE simulator programs.

Adjustment in the parameter values was necessary, most likely due to the physical

differences in 4H SiC and the reduction of drift mobility of inversion-layer electrons by

Coulomb scattering by the trapped charges. The results demonstrate that both MEDICI and

Chapter

5-2

SPICE simulators, with already existing models, can be used for design and optimization of

4H SiC MOSFETs and the circuit utilizing these MOSFETs.

The analysis of 4H SiC as compared to Si as semiconductor material for power

MOSFET has been shown in favor of 4H SiC due to its superior material properties. An

improvement of three-order magnitude in the specific on resistance of ideal 4H SiC

MOSFET over ideal Si MOSFET is projected. However, a review of the state-of-the-art of

SiC power MOSFETs indicates that the performance progress of SiC power devices have

been hampered by MOS interface related issues which resulted in high channel resistance

and premature device breakdown. To address the key problems in SiC MOS-based power

devices viz., high fixed charge and interface surface states, low channel mobility and high

electric field stressed to the gate oxide, the novel ACCUFET is exclusively proposed.

Numerical device simulation-based optimization efforts for this novel device have been

performed which result in an optimum device with blocking voltage capability of ~1500 V.

The simulation based evaluation of the novel ACCUFET as compared to two

alternative approaches, namely the trench-gate and planar ACCUFETs are also analyzed.

Given that a number of ACCUFETs, based on the alternative approaches, were

manufactured and the electrical characteristics were published, this simulation-based

comparison was focused on the merits of each of the considered structures, and the

qualitative terms of the relevant technological issues. It is shown that the novel ACCUFET

provides more merits in addressing key problems related to SiC MOS interface, thus

providing a superior figure of merit for power devices.

Circuit advantages enabled by utilization of the novel ACCUFET are analyzed as

the final part of the thesis. The same device rating of novel SiC ACCUFET and Si power

MOSFET is compared and analyzed in terms of their performance in typical switch-mode

power supply application. The circuit simulations indicate that operating frequency up to 1

MHz can be achieved in a system utilizing a novel ACCUFET. Thus gives an improvement

of 50 % in the operating frequency compared to a system utilizing a Si power MOSFET for

the same power efficiency. Furthermore, due to high temperature operation and the high

thermal conductivity in SiC, an additional 50 % saving in the weight, size and cost of the

5-3

comparable systems based on Si MOSFET can be achieved. Thus, overall, it provides a

compensation for the higher cost of the SiC MOSFET.

5.2. Suggestion for Further Research

The novel ACCUFET structure has been proposed and introduced to the SiC high

voltage device community in this thesis. While the numerical simulation-based analysis

results presented here point to a bright future for this device structure, the extent of work

needed to attain that reality is evident. This study focuses on the design and application

issues of SiC MOSFET and has not addressed subsequent steps of fabrication and

demonstration of the novel ACCUFET. The proposed development process for the novel

ACCUFET test structure is given in Appendix A, and it is submitted that these development

of the ACCUFET topic constitute the subject of a further research topic. The following lists

some of the other issues and other issues concerning SiC MOS-based devices that needed to

be tackled.

• Demonstration of the overall system advantages gained from the implementation of

SiC in power devices.

Chapter 4 analyzes the implementation of SiC device as a power switch in one part of

the system module (PFC stage) that shows significant advantages gained in the circuit

module. A subsequent demonstration in integration of passive components into a

packaged module as the result of implementation of SiC devices, which is imperative

for voltage regulator modules to operate at a significant higher frequency and to be

packaged with a higher power density need to be explored. Furthermore, the overall

system advantages e.g. DPS (Distributed Power System) application gained from the

implementation of SiC devices also needs to be analyzed/investigated.

• Further research in packaging technology and alternative insulator materials.

As described in Chapter 4, one of the system benefit results in utilizing SiC devices is

the simplification of the thermal management system through operation of the SiC

active junctions at much higher temperatures. However, there are several issues that

5-4

must be addressed in considering the operation of SiC devices at high temperature

(>350° C). These issues primarily include the SiO2 reliability problems and device

packaging technology. Thus additional research and development efforts to solve these

problems are warranted in view of the obvious potential of SiC for high temperature

electronic applications.

• Continued research in the areas of oxide growth and subsequent device processing in

SiC.

As the main objective of SiC MOS device research is to bring the channel mobilities

in SiC MOS devices as high as the bulk mobilities in SiC and improve reliability of

the SiO2 layer. Thus, research in the areas of oxide growth and subsequent device

processing in SiC play a vital role in providing the necessary quality dielectric layers

and low defect dielectric-semiconductor interfaces needed for the future generations of

SiC MOS-based devices.

A-1

FUNDAMENTALS OF SiC DEVICE PROCESSING AND PROPOSED PROCESS FOR THE FABRICATION OF NOVEL ACCUFET

A.1. Introduction

This appendix section provides the proposed process steps in fabricating the novel

ACCUFET structure. Reviews of SiC semiconductor in general which includes polytypism

in SiC and current processing technologies for SiC are also given.

Detail study of the process parameters and its effects related to the fabrication of

SiC MOSFETs has been carried out that led to successful 4H SiC MOSFET[1] device results.

Consequently, the process steps for the fabrication of self-aligned novel ACCUFET are

proposed according to these confirmed process parameters i.e. annealing time and

temperature, Ni/Mo/SiO2 sputtering, gate oxidation/nitridation, PMA time and temperature.

The fabrication of the novel ACCUFET is quite similar to the fabrication process of

the UMOS structure. One of the advantages of the novel ACCUFET process is its simplicity

of fabrication as compared to other structures e.g. DIMOS. Moreover, the development of

the novel ACCUFET does not require P-type implantation process, hence eliminates one of

unit processes that is problematic in SiC. The major unit processes required in the

development of novel ACCUFET are SiC RIE etching, N-type ion-implantation, and MOS

structure fabrication. Unlike in P-type implants, activation of N-type implants in SiC can be

effectively done at much lower temperature of 1500 °C. Recent experiments have shown

[1] J. S. Han, S. Dimitrijev, and H. Linewih, recent work in fabricating 4H SiC MOSFETs and Hall structures, Griffith

University – Erlangen University.

Appendix

A-2

even lower temperature to be effective as well, which resulted in successful self-aligned SiC

MOSFET transistors. Consequently, this proposed process for the fabrication of the novel

ACCUFET will be based on the self-aligned process. A self-aligned process would be able to

minimize the channel resistance contribution of the device as well as eliminate the severe

dependence of the device performance on alignment tolerances in some of the critical

alignments.

A.2. General Properties of SiC

A.2.1. Polytypism in SiC

Polytypism is a unique feature of SiC [1]. SiC polytypes differ not in relative

numbers of Si and C atoms but in the stacking sequence of the tetrahedrally bonded Si-C

bilayers. The polytypes are named according to the periodicity of these layers and the overall

symmetry of the crystal. For example one of the commonest polytypes is called 6H, this

means a hexagonal type lattice with an arrangement of 6 different Si + C layers before the

pattern repeats itself. In total more than 200 different polytypes of SiC have been shown to

exist [2], some with patterns that do not repeat for hundreds of layers.

Shorthand has been developed to catalogue the literally infinite number of possible

polytype crystal structures. Each tetrahedrally bonded Si-C bilayer can be situated in one of

three possible positions with respect to the lattice. These possible positions can be arbitrary

assigned by A, B, or C notation. Depending on the staking order, the bonding between Si and

C atoms in adjacent bilayer planes is either of a zinc-blende (cubic) or wurtzite (hexagonal)

nature. Referring to Fig. A-1(a), if the stacking is ABCABC… the only purely cubic zinc-

blende structure, so called 3C SiC is realized. While the purely wurtzite structure ABAB…

generates 2H SiC polytype. Other than 2H SiC and 3C SiC, all of the other polytypes are

mixture of fundamental zinc-blende and wurtzite bonds. Common polytypes with more

complex stacking sequence are 4H SiC and 6H SiC as shown in Fig. A-1(b) and A-1(c),

respectively. Structurally, 4H SiC is composed equally of cubic and hexagonal bonds while

A-3

6H SiC is two-third cubic. Despite the cubic elements, each has the overall hexagonal crystal

symmetry.

Figure A-1 Crystal structure of 3C SiC (a), 4H SiC (b), and 6H SiC (c).

The exact physical properties of SiC depend on the crystal structure adopted. It has

been experimentally determined that the bandgap differs widely among the polytypes,

ranging from minimum of 2.39 eV in 3C SiC to 3.265 eV in 4H SiC to maximum 3.33 eV

for 2H SiC [3]. In general, the greater the wurtzite component in crystal structure, the larger

the bandgap.

A-4

A.2.2. SiC Bulk Crystal and Epitaxial Growth

SiC is the only chemically stable form of silicon and carbon, and does not occur

naturally in nature, hence elaborate furnace technique is needed for growing SiC crystal. The

major development in SiC happened in 1955, when Lely proposed a new concept

(sublimation method) for growing single crystals with different polytypes [4]. Furthermore

the use of a seeded sublimation growth technique, which was basically a modification of

Lely’s original method and referred to as the “modified Lely technique”, was introduced in

1978 [5]. This breakthrough led to the possibility for the true bulk crystal preparation [6,7, 8]

and the foundation of CREE research in 1987 as the first, and until recently the only,

commercial supplier of SiC substrates.

Substrates are available with both N- and P-type conductivity over a wide range.

Nitrogen and Aluminum are the main N- and P-type impurity, respectively, used for doping

SiC boules because they create relatively shallow donor and acceptor levels in the SiC

energy gap [9]. The resistivity of the substrate is an important factor especially for vertical

power device structures, which is a major application area for SiC. To date, 4H SiC and 6H

boules have been produced with resistivities as low as 0.0028 Ω cm and 0.0016 Ω cm,

respectively [10]. These producible resistivities compare favorably with those currently used

in the Si industry for power devices.

As in the rest of the semiconductor industry, the desired size of SiC wafers

available for device fabrication is primarily an economic issue, especially for the production

of high current power devices, which require 100 mm or larger diameter wafer. Wafers of 1

inch in diameter have been available for several years for both 4H and 6H SiC. The size of

commercially available 4H and 6H SiC wafers has recently been increased to 3 inches in

diameter [10].

The key issue in the realization of SiC electronics is the controlled growth of high

quality epilayers. At present, the chemical vapor deposition (CVD) growth technique shows

the most promise for attaining epilayer reproducibility and throughputs that will be required

for mass production [11]. Homoepitaxial growth, whereby the polytype of the epilayer

A-5

matches the polytype of the substrate, is accomplished by step controlled epitaxy, which is

based upon growing on a SiC wafer polished at an angle of 3 to 4 degrees off the (0001)

basal plane [12, 13]. This forces epilayer growth to take place at the abundance of growth

surface steps so that the polytypic stacking sequence of the substrate is mirrored in the

epilayer.

Depending on the Si/C ratio used during growth [14, 15], undoped films generally

exhibit background carrier concentrations less than 1 x1015 cm-3. By precise control of Si/C

ratio and intentional dopant incorporation, film of both N- and P-type SiC can be grown with

carrier concentrations from less than 1 x 1015 cm-3 to greater than 1 x 1019 cm-3. The carrier

concentration can be changed abruptly throughout this wide doping range. Film uniformity is

improving, to date 3 inch diameter 4H epitaxial wafers exhibit thickness and doping

uniformities of 7% and <20%, respectively [10].

Although great progress has been made in obtaining both high quality substrates

and subsequently grown SiC epilayer, some defects related to the growth of SiC crystal still

remain. Examples of these defects are micropipes and dislocation, of which micropipes is the

primary problem and the primary obstacle to the production of large area SiC based devices.

The micropipes defects, which are typically present in densities of a few hundreds per square

centimeter, generally lead to junction breakdown at electric fields well below the known

critical field [16]. However, their density has been steadily decreasing at a roughly twofold

rate every year to date minimum density of 1 per square centimeter [17].

A.3. Process Technology Related Issues in SiC Device Fabrication

Despite the differences with silicon, there is much about the chemistry of SiC that is

similar to Si. This gives a start-up advantage in term of process technology i.e. a wealth of

processes that with refinement can be used in SiC device production.

A-6

A.3.1. Selective Doping of SiC

Unlike Si, because of the very small diffusion coefficients of those dopants in SiC,

diffusion is not a practical way to dope SiC. Dopants can only be introduced either during

epitaxy or by ion implantation. Ion implantation in SiC has been demonstrated to be a

suitable means for achieving degenerate doping densities for both P- and N-type material

with reasonable ion flux [18, 19]. Unfortunately, the high bonding strength of the SiC lattice

requires the implant anneal to be performed in excess of 1600 °C if full doping activation is

to be achieved [19]. It is widely believed that the degradation of the SiC material surface

after implant annealing is one reason responsible for low MOSFET inversion layer mobility,

a serious problem leading to unacceptable on-state resistance in these power devices [20].

Ion-implantation at high temperature, which heats up the SiC substrate to high temperature

(>500 °C) during ion implantation, is a very effective method of improving the electrical

activation rate of dopant implanted into SiC and reducing the implantation-induced damage

[21]. It was reported that the sheet resistance of nitrogen (N+) and phosphorus (P+) implanted

SiC substrates by high temperature ion implantation at 500 °C were 546 Ω/ and 160 Ω/,

respectively [22, 23].

A.3.2. SiC Etching

The need in patterning in semiconductor device fabrication and pregrowth etching

to remove foreign materials and the damaged surface layer after mechanical substrate

polishing, make etching techniques a crucial component of any semiconductor technology.

Unlike Si, the strength bonding of SiC makes it rather difficult to etch. For device fabrication

since there is no wet etchant for SiC known, reactive ion etching (RIE) proved to be the most

viable technique [24]. The necessity to use RIE is actually not a limitation because, as

feature sizes decrease, dry etching processes are preferred over wet etching processes. Etch

rates for SiC of 10-100 nm/min have been obtained with fluorinated plasmas with a high

degree of anisotropy [25]. As for substrate preparation due to the similarity of (0001)Si 6H

SiC and (111) Si, a developed simple and effective process technique [25] using the highly

successful Si substrate HF passivation technique [26], provides a clean and smooth surface

for epitaxy growth.

A-7

A.3.3. Oxidation of SiC

The thin SiO2 plays a unique role in Si technology. The availability of high quality

SiO2 grown on Si substrate has led to the development of planar technology and permits

fabrication of diffused or ion implanted junctions of precisely controllable dimensions. SiC

is the only compound semiconductor in that its native oxide is SiO2, the same oxide as Si.

This means that the workhorse power devices in Si (power MOSFET, insulated gate bipolar

transistor, MOS controlled thyristor) can be fabricated in SiC. Moreover, a good knowledge

on the SiO2/Si interface has been accumulated and has led to great progress in Si technology

that can be applied to develop SiC technology.

As with the Si technology, the oxide layer on SiC can be obtained in different ways

such as thermal oxidation [27, 28, 29] and CVD [30, 31]. SiC surfaces can be thermally

oxidized using dry and wet oxygen at around 1000 °C in the same way as Si. The oxidation

of SiC has been studied by many [28, 32, 33]. It has been found that the oxidation rate of all

SiC polytypes is much lower than that of Si. It normally takes a much longer time to get the

same thickness on SiC than on Si under the same oxidation conditions. Another unique

characteristic in the oxidation process of SiC is that the oxidation rates are different between

the silicon face and the carbon face i.e. the oxidation rates depend on the crystal orientation

of SiC, thus SiC shows an anisotropic oxidation [34].

The SiO2/Si interface plays a crucial role in the development of MOS devices. To

build high performance MOS devices in SiC, the SiO2/Si interface needs to be improved. For

years, the progress has been hampered by problems with the gate oxide, reflecting in very

poor channel-carrier mobility and oxide reliability. A lot of research efforts have been

poured into the improvement of quality SiO2/Si interface in SiC. A figure of merit in MOS

devices can be described in terms of their interface state and fixed charge densities. Dramatic

improvements have recently been reported with nitrided SiO2–SiC interfaces [35, 36],

leading to improved reliability and to recently reported values for inversion-layer mobility in

4H SiC of about 50 cm2/Vs [37].

A-8

A.4. Proposed Fabrication of Novel ACCUFET

The novel ACCUFET structure uses an n+ substrate 4H SiC wafer with 3 epilayers,

n-/p-/n. The wafer will be cut into 8 sections and each section will be developed individually

with different oxidation process. Details of wafer parameters and technology steps involved

are given in TABLE A-I and Section A.4.3, respectively.

Table A-I Wafer description for fabrication of novel ACCUFET device.

wafer #1 Part Number W4NRD8C-00S3 Production or Research Grade RESEARCH Wafer Face (C or Si) Si Orientation (3.5o/8o OFF) 8o OFF Wafer Type (N or P) N Wafer Doping Level (cm-3) 1.0 x 1019 Resistivity (ohm-cm) 0.015-0.028 Wafer Thickness (") 0.0130 Backside Polish (Yes/No) NO 1st Epi Conductivity N 1st Epi Doping Level (cm-3) 1.0 x 1016 1st Epi Thickness (µm) 10 2nd Epi Conductivity P 2nd Epi Doping Level (cm-3) 1.4 x 1017 2nd Epi Thickness (µm) 2.0 3rd Epi Conductivity N 3rd Epi Doping Level (cm-3) 1.0 x 1016 3rd Epi Thickness (µm) 0.2

A-9

A.4.1. Novel ACCUFET Structure Device Design

The cross section of the ACCUFET is shown in Fig. A-2, the ACCUFETs will have

circular gate width of 800 µm (mid-gate circumference) and varied gate length from 10 to

100 µm.

Figure A-2 Novel ACCUFET layout and cross section.

A-10

A.4.2. Novel ACCUFET Proposed Run Sheet

INITIAL MATERIAL CLEAN

• CLEAN samples of packaging contamination.

FORMATION OF THE TRENCH AND P-BASE CONTACT REGIONS

• DEPOSIT Al.

• Photolithography (METAL1 mask).

• RIE ETCH.

• Photolithography (METAL2 mask),

• RIE ETCH.

• STRIP Al.

GATE OXIDATION AND GATE DEFINITION

• PRE-OXIDATION CLEAN.

• GATE OXIDATION

Gate oxidation process in dry O2.

nitridation with NO or N2O.

• DEPOSIT Molybdenum gate by sputtering.

• Photolithography (MOLY mask).

• PATTERN Molybdenum gates.

CAPPING

• DEPOSIT oxide by sputtering.

• PROTECT oxide in the trench regions.

• Photolithography (OXIDE+MOLY mask).

• ETCH oxide capping and Molybdenum in the Source region.

N+ IMPLANTATION PROCESS

• Send to Dr. Pensl1 for Phosphorus implantation.

IMPLANT ACTIVATION ANNEALING

1 Erlangen University, Germany

A-11

• ANNEAL at 1000o C for 30 minutes.

• POST ACTIVATION CLEAN.

FORMATION OF SOURCE OXIDE WINDOW AND CONTACT DEPOSITION

• ETCH oxide capping, Molybdenum, gate oxide for the p-base and Source

contact (OXIDE+MOLY+OXIDE),

• DEPOSIT oxide buffer by spinning.

• Photolithography (OXIDE1 mask),

• OXIDE WINDOW ETCH

• DEPOSIT Ni by sputtering.

• Photolithography (NICKEL mask).

DRAIN CONTACT DEPOSITION

• PROTECT frontside

Apply positive photoresist.

Hard bake.

• ETCH backside

Remove residual layers of oxide.

• DEPOSIT Al on backside DRAIN

Al evaporation.

Strip photoresist.

PACKAGING

• Deposit oxide buffer by spinning.

• Photolithography (OXIDE2 mask),

• Oxide etching.

A-12

A.4.3. Novel ACCUFET Self-Aligned Proposed Process Steps

The fabrication process of the ACCUFET device as follow:

1. Deposit Al metal layer (~ 40nm) over the wafer by evaporation.

2. Photolithography: define the slope areas. (METAL1 mask)

3. Etch Al; strip resist.

4. Etch the top N-type epilayer by plasma etching (~2 µm); this creates a slope as part of

the drift region.

5. Photolithography: define window regions for the source p-base contact areas. (METAL2

mask).

6. Etch Al; strip resist.

7. Etch the top N-type epilayer by plasma etching (~0.2 µm): this creates a slope as part of

the drift region as well as contact area to p-base epilayer.

N-type

P-type

N-type

A-13

8. Wafer cleaning.

9. Grow gate oxide (~35 nm).

10. Deposit Mo (~600 nm) by sputtering.

11. Photolithography: define the trench/slope region for ion-implantation. (MOLY mask).

12. Remove unwanted Mo; strip resist.

13. Deposit thin oxide (~150 nm) by sputtering. This thin oxide is used as capping for Mo

during high temperature process.

14. Photolithography: define the Source region for ion-implantation. (OXIDE+MOLY

mask).

15. Remove unwanted oxide and Mo; strip resist.

16. Ion implantation.

17. Annealed for difference temperature range of 800oC – 1100oC for 30 minutes in

Nitrogen.

N-type

P-type

N-type

N-type

P-type

SiO2 Mo

N-type

A-14

18. Photolithography: opening the p-base contact. (OXIDE+MOLY+OXIDE mask).

19. Etch oxide, Mo and gate oxide; strip resist.

20. Deposit thin oxide (~150 nm) by sputtering.

21. Deposit Ni layer (~300 nm) by sputtering; backside/Drain contact.

22. Photolithography: define the Gate and Source contact windows. (OXIDE1 mask).

23. Etch oxide; strip resist.

24. Deposit Ni layer (~ 1.5 µm) by sputtering.

25. Photolithography: define Contacts. (NICKEL mask).

26. Etch Ni; strip resist.

N-type

P-type

SiO2 Mo

N-type

SiO2 Mo

N-type

P-type

N-type

N++

A-15

27. Deposit oxide by spinning on glass.

28. PMA annealing, 900 0C for 30 minutes in Nitrogen.

29. Photolithography: define open window for probing. (OXIDE2 mask).

30. Etch oxide; strip resist.

Ni Mo

N-type

N-type

N-type

N++

A-16

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A-18

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A-19

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