Assertion Based Verification

Design and Verification of SystemCTransaction-Level ModelsRoza GhamariBogazici UniversityApril 2009OutlineIntroductionSystemC LanguageFormal Verification Techniques for SystemCDesign and Verification of SystemC TLMDesign MethodologyVerification MethodologyExperimental ResultsSummeryReferences

2Total # of slides 372IntroductionWhat is SystemC?Wide range of modeling Levels from RTL to system levelBuilt on C++ (Object Oriented)Consists of an event-driven simulator in the coreWorks with events and processes Represent structures by modules and portsDescribe Communication with interfaces and channelsSeparate data types for hardware modeling and software programmingLibrary-defined elementary channels

3Total # of slides 37Introduction (Cont.)Formal Verification Techniques for SystemCAssertion-Based ValidationWriting properties in a formal language (e.g. PSL or SVA)Monitoring these properties by Simulation engineExtendable to SystemC dynamic validation (Required other package integration e.g. BDD) Can be extended:: same assertions used for SystemC and RTL 4Total # of slides 37Introduction (Cont.)Explicit-State Model CheckingKeeping track of all nondeterministic choices (e.g. input values)Monitor the states visited (to find termination)Extendable to SystemC

Limitation State explosion problem (abstraction techniques)

5Total # of slides 37Introduction (Cont.)Symbolic SimulationExecute program by abstract setting (symbols instead of concrete values)Symbolic simulation path generate test cases, reasoning ,Hard for implementation on SystemC (aimed concurrent systems)Statically analyzing dynamic execution path6Total # of slides 37Introduction (Cont.)Symbolic Model CheckingRepresented and searched by means of symbolic reasoning Needs formal semantics for description of transition relation in a SystemC design

7Total # of slides 37Introduction (Cont.)Equivalence VerificationFormal verifying the equivalence of SystemC and RTL models Similarly equivalence of RTL and Netlist modelsModest goal :: Compatibility/Conformance/Compliance

8Total # of slides 37Design and Verification of SystemCThe problem of growth in complexity and size of systems.RTL level :effort : 1) design; 2) verify; 3) simulation.Pin-levelSystemC : system level language.Transaction level modeling.9Total # of slides 37Design and Verification of SystemC (cont.)What are the problems?Verification of a SystemC model is a serious bottleneck in the design cycle.Requirement for verification Expressive languages for specifying assertions and behaviors of a complex system

10Total # of slides 37Design and Verification of SystemC (cont.)11Total # of slides 37

Property Specification LanguageAn implementation independent language to define propertiesProperties are defined in a Hierarchical wayNot enough to improve the design and verification flowsUsing UML to present PSL property.To embed PSL into designModel PSL semantics in AsmL Enable reusing PSL properties with concrete SystemC level or as stand-alone module12Total # of slides 37Layers of PSLBoolean layer build expressions for the other layers, specifically the temporal layer (evaluated in one evaluation cycles)Temporal layerDescribe properties of the designDescribe simple general propertiesDescribe properties that involve complex temporal relations (evaluated over a series of evaluation cycles)

13Total # of slides 37Layers of PSL (cont.)Verification layer tell the verification tool what to do with the properties described by the temporal layerModeling layer model behavior of design inputs for formal verification toolsmodel auxiliary parts of the design that are needed for verificationThis layer is for VHDL and Verilog and not used in this design14Total # of slides 37UML Model of PSLDefining a modified sequence diagram to map PSL propertyClocks: Clock that activate the current actionNumber of cycles:Mtd[5] says that the method Mtd is executed for exactly 5 consecutive cycles.Temporal operators: A mapping to PSL temporal operatorsalways executed (A), eventually executed (E), Executed Until a condition is fulfilled (U)

15Total # of slides 37UML Model of PSL (Cont.) Sequence operations:order of executing certain sequences (e.g., next, prev etc.)Text output:Failing report message for a caseMethod duration:Certain number of cycles for execution() operator:Set of argument of an action16Total # of slides 37UML Model of PSL (Cont.)17Total # of slides 37

ASM Model of PSLAbstract State Machines (ASM) a formal specification method for software and hardware systemssupports object-oriented modeling comparison to C++and Java.all the parameters of PSL properties are defined as objectsAsmL tool (developed by Microsoft) can automatically compile code into a C# or .NET code

18Total # of slides 37ASM Model of PSL (Cont.)PSL_SERE.Evaluate() Examplechecks if a sequence is true in a certain pathactivated according to an INIT signal (set by the property)

19Total # of slides 37ASM Model of SystemCFSM generation algorithm(four input)MethodsDomainsActionsVariablesOptional inputs: filters, action groups, propertiesSpecific style of programmingA precise configuration which generates the FSM Exploration: keeping track of the actions it performs and recording the states it visits

20Total # of slides 37ASM Model of SystemC (Cont.)FSM PartsActions :: MethodsTransitions :: Method callsStates :: Values of selected variablesRULESInitializing all of the models objectsDefining a set of preconditions for every action considered in the exploration processProviding for every state variable an exploration domain.21Total # of slides 37ASM Model of SystemC (Cont.)Example22Total # of slides 37

Translation to SystemCPurely syntactical based on 3 major rulesR1C++ : Basic Types are mapped to their equivalentR2C++ : Class TranslationR2.1C++ : Class members mapped into signals with same typesR2.2C++ : Class methodsPreconditions/Postconditions mapped to SystemC modules constructorMethod Send precondition require clk = true SC_THREAD(Send);sensitive ), equivalence () )Step 3) Define the verification unit as an A-Property, A, that includes the property P: A.Add(P)

25Total # of slides 37Model Checking (Cont.)P is represented by two Boolean state variablesP_eval and P_valueViolated propertyP_eval = true and P_value = false generation stops and problem identified based on generated portion

26Total # of slides 37Assertion-Based VerificationUpdating the SystemC design to interface to the assertion monitorGenerating the assertion as a C# code from its AsmL descriptionIntegrating the assertion into the design.27Total # of slides 37

Assertion-Based Verification (Cont.)Assertion Monitor:Stop the simulation when the assertion is fired Write a report about the assertion status and all its variablesSend a warning signal to other modules (if required).28Total # of slides 37Assertions Coverage EnhancementStatic analysisDependency checkTest Program generatorInitial DNA generatorDNA evaluation/update

29Total # of slides 37Assertions Coverage Enhancement (Cont.)Static Code AnalysisGenerate the inputs/assertions variables dependency relation based on Abstract Interpretation approachHypergraph30Total # of slides 37Assertions Coverage Enhancement (Cont.)Genetic Algorithmevaluating the fitness of each candidate selecting the fittest candidate solutions to act as parents of the next generation of candidate solutions recombining and mutating selected parents to generate offspringsCandidate solutions: finite sequences of input ranges and probability weightsEncoded by a chromosome (inputs/ranges/weighted probability)31Total # of slides 37Experimental ResultsConsidered models:Peripheral Component Interconnect (PCI) bus SystemC Master/Slave busProperties (e.g. liveness) must be verified using formal techniques

32Total # of slides 37Experimental Results (Cont.)PCI Bus results

33Total # of slides 37Experimental Results (Cont.)Master/Slave bus results

34Total # of slides 37Experimental Results (Cont.)Assertions coverage analysis

35Total # of slides 37SummeryMethodology to Design and Verify SystemC TMsUML system specification and integrating an intermediate layer using AsmLUpgrade sequence diagram of UML to capture TR systemsModel both design and properties in AsmL and preform model checkingReuse PSL properties to perform assertion-based verificationTransform the AsmL m0del to SystemCApply Static Code analysis and Genetic algorithm techniques to enhance efficiency

36Total # of slides 37ReferencesMoshe Y. Vardi: Formal Techniques for SystemC Verification; Position Paper. DAC 2007:188-192Ali Habibi, Sofine Tahar: Design and verification of SystemC transaction-level models. IEEE Trans. VLSI Syst. 14(1): 57-68 (2006)Ali Habibi, Sofine Tahar: Design for Verification of SystemC Transaction Level Models. DATE 2005: 560-56537Total # of slides 37