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Digital System Designs and Practices Using Verilog HDL and FPGAs Describe basic structures of µPsystemsUnderstand the basic operations of bus structuresUnderstand the essential operations of data transfer
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7/15/2019 Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-1
Chapter 15: Design Examples
Department of Electronic Engineering National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
7/15/2019 Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-2
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
7/15/2019 Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-3
Objectives
After completing this chapter, you will be able to:
Describe basic structures of µP systems
Understand the basic operations of bus structures
Understand the essential operations of data transfer
Understand the design principles of GPIOs
Understand the design principles of timers
Understand the design principles of UARTs Describe the design principles of CPUs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-4
Syllabus
Objectives
Bus
A µ p system architecture
Bus structures
Bus arbitration
Data transfer
General-purpose input and output
Timers Universal asynchronous receiver and transmitter
A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-5
A Basic µP System
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-6
Syllabus
Objectives
Bus
A µ p system architecture
Bus structures
Bus arbitration
Data transfer
General-purpose input and output
Timers Universal asynchronous receiver and transmitter
A simple CPU design
7/15/2019 Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-7
Bus Structures
Tristate bus
using tristate buffers
often called bus for short
Multiplexer-based bus
using multiplexers
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-8
A Tristate Bus
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-9
A Tristate Bus Example
// a tristate bus example
module tristate_bus (data, enable, qout);
parameter N = 2; // define bus widthinput enable;
input [N-1:0] data;
output [N-1:0] qout;
wire [N-1:0] qout;
// the body of tristate bus
assign qout = enable ? data : {N{1'bz}};
endmodule
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-10
A Bidirectional Bus Example
// a bidirectional bus example
module bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout);
parameter N = 2; // define bus width
input send, receive;input [N-1:0] data_to_bus;
output [N-1:0] data_from_bus;
inout [N-1:0] qout; // bidirectional bus
wire [N-1:0] qout, data_from_bus;// the body of tristate bus
assign data_from_bus = receive ? qout : {N{1'bz}};
assign qout = send ? data_to_bus : {N{1'bz}};
endmodule
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-11
A Multiplexer-Based Bus
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-12
Syllabus
Objectives
Bus
A µ p system architecture
Bus structures
Bus arbitration
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-13
Daisy-Chain Arbitration
Types of bus arbitration schemes
daisy-chain arbitration
radial arbitration
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-14
Syllabus
Objectives
Bus
Data transfer
Synchronous transfer mode
Asynchronous transfer mode
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-15
Data Transfer Modes
Data transfer modes
synchronous mode
asynchronous mode
The actual data can be transferred in
parallel: a bundle of signals in parallel serial: a stream of bits
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-16
Synchronously Parallel Data Transfers
Each data transfer is synchronous with clock signal
Bus master
Bus slave
Two types
Single-clock bus cycle Multiple-clock bus cycle
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-17
Synchronously Parallel Data Transfers
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-18
Synchronously Serial Data Transfers
Explicitly clocking scheme
Implicitly clocking scheme
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-19
Synchronously Serial Data Transfers
Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-20
Syllabus
Objectives
Bus
Data transfer
Synchronous transfer mode
Asynchronous transfer mode
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-21
Asynchronous Data Transfers
Each data transfer occurs at random
Control approaches
strobe scheme
handshaking scheme
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-22
Strobe
Ch 15 D E l
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-23
Handshaking
Four events are proceeded in a cycle order
ready (request)
data valid
data acceptance
acknowledge
Ch t 15 D i E l
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-24
Handshaking
Two types
source-initiated transfer
destination-initiated transfer
Ch t 15 D i E l
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-25
Asynchronously Serial Data Transfers
Transmitter
Receiver
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-26
Asynchronously Serial Data Transfers
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-27
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-28
General-Purpose Input and Output Devices
The general-purpose input and output (GPIO)
input
output
bidirectional
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-29
General-Purpose Input and Output Devices
An example of 8-bit GPIO
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-30
Design Issues of GPIO Devices
Readback capability of PORT register
Group or individual bit control
Selection the value of DDR
Handshaking control
Readback capability of DDR
Input latch
Input/Output pull-up
Drive capability
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-31
General-Purpose Input and Output Devices
The ith-bit of two GPIO examples
Chapter 15: Design Examples
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p g p
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-32
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers Interface
Basic operation modes
Advanced operation modes
Universal asynchronous receiver and transmitter
A simple CPU design
Chapter 15: Design Examples
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p g p
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-33
Timers
Important applications
time-delay creation
event counting
time measurement
period measurement
pulse-width measurement
time-of-day tracking
waveform generation
periodic interrupt generation
Chapter 15: Design Examples
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Timers
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-35
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers Interface
Basic operation modes
Universal asynchronous receiver and transmitter
A simple CPU design
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-36
Basic Timer Operations
Timers
What is a timer?
What is a counter?
What is a programmable counter?
What is a programmable timer?
Basic operation modes
terminal count (binary/BCD event counter)
rate generation (digital) monostable (or called one-shot)
square-wave generation
Chapter 15: Design Examples
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Terminal Count
Chapter 15: Design Examples
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Rate Generation
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-39
Retriggerable Monostable (One-Shot) Operation
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-40
Square-Wave Generation
(b) Block diagram of square-wave mode
(a) A waveform example of square-wave mode
clk
out
3 2 1 0(4)0(4)3 2 14
Latch register = 4
Latch
timer
Data buswr
rd
out
gate
clk
timer_loadgenerator
timer_enable
timer_load D
CK
Q
timer is 1
Shift plus LSB
out logic
latch_load
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-41
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
Interface
Basic transmitter structure
Basic receiver structure
Baud-rate generators
A simple CPU design
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-42
UARTs
Hardware model
the CPU interface
the I/O interface
Software model
receiver data register (RDR)
transmitter data register (TDR)
status register (SR)
control register (CR)
Chapter 15: Design Examples
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UARTs
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-44
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
Interface
Basic transmitter structure
Basic receiver structure Baud-rate generators
A simple CPU design
Chapter 15: Design Examples
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Design Issues of UARTs
Baud rate
Sampling clock frequency
Stop bits
Parity check
Chapter 15: Design Examples
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A Transmitter of UARTs
The transmitter
a transmitter shift data register (TSDR)
a TDR empty flag (TE) a transmitter control circuit
a TDR
parity generator
Chapter 15: Design Examples
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A Transmitter of UARTs
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-48
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
Interface
Basic transmitter structure
Basic receiver structure Baud-rate generators
A simple CPU design
Chapter 15: Design Examples
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A Receiver of UARTs
The receiver
a RDR
a receiver shift data register (RSDR)
a status register
a receiver control circuit
Chapter 15: Design Examples
A i f A
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A Receiver of UARTs
Chapter 15: Design Examples
S ll b
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-51
Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
Interface
Basic transmitter structure
Basic receiver structure Baud-rate generators
A simple CPU design
Chapter 15: Design Examples
B d R t G t
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Baud-Rate Generators
The baud-rate generator
provides TxC and RxC
Design approaches
Multiplexer-based approach
Timer-based approach
Others
Chapter 15: Design Examples
B d R t G t
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Baud-Rate Generators
Chapter 15: Design Examples
S ll b
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Syllabus
Objectives
Bus
Data transfer
General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
Programming model Datapath design
Control unit design
Chapter 15: Design Examples
CPU Basic Operations
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CPU Basic Operations
Chapter 15: Design Examples
The Software Model of CPU
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The Software Model of CPU
The programming model
Instruction formats
Addressing modes
Instruction set
Chapter 15: Design Examples
The Programming Mode
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The Programming Mode
Chapter 15: Design Examples
Instruction Formats
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Instruction Formats
Two major parts
Opcode
Operand
Chapter 15: Design Examples
Addressing Modes
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Addressing Modes
The ways that operands are fetched
register
indexed register indirect
immediate
Chapter 15: Design Examples
The Instruction Set
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The Instruction Set
Double-operand instruction set
Chapter 15: Design Examples
The Instruction Set
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The Instruction Set
Single-operand instruction set
Chapter 15: Design Examples
The Instruction Set
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The Instruction Set
Jump instruction set
Chapter 15: Design Examples
Syllabus
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Syllabus
Objectives
Bus
Data transfer General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
Programming model
Datapath design
Control unit design
Chapter 15: Design Examples
A Datapath Design
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A Datapath Design
Chapter 15: Design Examples
ALU Functions
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ALU Functions
Chapter 15: Design Examples
Syllabus
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y
Objectives
Bus
Data transfer General-purpose input and output
Timers
Universal asynchronous receiver and transmitter
A simple CPU design
Programming model
Datapath design
Control unit design
Chapter 15: Design Examples
A Control Unit
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The decoder-based approach
Chapter 15: Design Examples
A Control Unit
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A better approach
Chapter 15: Design Examples
A Control Unit
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The operations of T3 and T4 are determined separately by
each instruction
