Design of a QR Adapter with Improved Efficiency and Low Standby Power

Agenda

1. Quasi-Resonance (QR) Generalities

2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

Agenda

1. Quasi-Resonance (QR) Generalities

2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

What is Quasi-Square Wave Resonance ?

• MOSFET turns on when VDS(t) reaches its minimum value.

Minimizes switching losses

Improves the EMI signature

MOSFET turns on in first valley MOSFET turns on in second valley

valley

Quasi-Resonance Operation

• In DCM, VDS must drop from (Vin + Vreflect) to Vin

• Because of Lp-Clump network oscillations appear

• Oscillation half period:

Vin + Vreflect

Vin

VDSLp

Vin

SW Clump

RloadCout1 : N Vout

VDS

Vin

x p lumpt L Cπ=

A Need to Limit the Switching Frequency

• In a self-oscillating QR, Fsw increases as the load decreases

• 2 methods to limit Fsw:– Frequency clamp with frequency foldback

– Changing valley with valley lockout

Higher losses at light load if Fsw is not limited

Frequency Clamp in QR Converters

In light load, frequency increases and hits clampMultiple valley jumpsJumps occur at audible rangeCreates signal instability

Second valley First valley

QR mode

Agenda

1. Quasi-Resonance (QR) Generalities

2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

0

10000

20000

30000

40000

50000

60000

70000

80000

0 10 20 30 40 50 60

OUTPUT POWER (W)

SWIT

CHIN

G F

REQ

UENC

Y (H

z)

1st2nd3rd4th

VCO mode

QR operation

The Valley Lockout• As the load decreases, the controller changes valley (1st to 4th valley in

NCP1380)• The controller stays locked in a valley until the output power changes

significantly.

12 3 4

VCO mode

– No valley jumping noise– Natural switching frequency limitation

The Valley Lockout• FB comparators select the valley and pass the information to a

counter.• The hysteresis of FB comparators locks the valley.• 2 possible operating set points for a given FB voltage.

VFB decreases (POUT decreases)

VFB increases (POUT increases)

1st

2nd

3rd

4th

VCO

3.22.82.01.20.8 1.6 VFB (V)2.4

Agenda

1. Quasi-Resonance (QR) Generalities

2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

• Operating modes:– QR current-mode with valley lockout for noise immunity– VCO mode in light load for improved efficiency

• Protections– Over power protection– Soft-start– Short circuit protection– Over voltage protection– Over temperature protection– Brown-Out

NCP1379/1380 Features

HV-bulk

DovpZCD / OPP

1

2

3

4 5

8

6

7

NC

P138

0 C

/DFB

CS

Rzcd1

GND

Rzc

d2

Czc

d

Rst

art

Ct

Cvcc

Ct

DRV

Vcc

OVP/BO

Rbol

Rbou

Mass production: Q4 2009

QR Mode with Valley Lockout• Operating principle:

– Locks the controller into a valley (up to the 4th) according to FB voltage.– Peak current adjusts according to FB voltage to deliver the necessary

output power.

12 3 4

VCO mode

• Advantages– Solves the valley jumping instability in QR converters– Achieves higher min Fsw and lower max Fsw than in traditional QR converters– Reduce the transformer size

Fsw (Pout) for a 60 W adapter

0.00E+00

2.00E+04

4.00E+04

6.00E+04

8.00E+04

1.00E+05

1.20E+05

1.40E+05

0 10 20 30 40 50 60Pout (W)

Fsw

(Hz)

1st2nd3rd4th

QR operationVCO mode

VCO Mode

• Occurs when VFB < 0.8 V (Pout decreasing) or VFB < 1.4 V (Pout increasing)

• Fixed peak current (17.5% of Ipk,max), variable frequency set by the FB loop.

Constant peak current (17.5% of Ipk max)

Fsw1 @ Pout1 Fsw2 @ Pout2 Pout1 > Pout2

Ipk max

Combined ZCD and OPP

• Zero-Crossing Detection (ZCD) and Over Power Protection (OPP) are achieved by reading the Aux. winding voltage– ZCD function used during the off-time of MOSFET (positive voltage).

– OPP function used during the on-time of MOSFET (negative voltage)

2

1

0 V

50 mV

Possible restarts for ZCD VOPP

VDRV

VZCD

0.8 V + Vopp

ZCD/OPP IpFlag+0.8 V

+

-

ESDprotectionAux

Ropu

Ropl

1

Rzcd

CS

+

-Vth

DRV Tblank

leakage blanking

Demag

NCP1380 Versions

• 4 versions of NCP1380: A, B, C and D

XXXNCP1380 / D

XXXNCP1380 / C

XXXNCP1380 / B

XXXNCP1380 / A

LatchedOver current protection

Auto-RecoveryOver current protectionBOOVPOTP

OTP: Over Temperature ProtectionOVP: Over Voltage ProtectionBO: Bown-Out

Short-Circuit Protection• Internal 80 ms timer for short-circuit validation.

• Additional CS comparator with reduced LEB to detect winding short-circuit.

• VCS(stop) = 1.5 * VILIMIT

ZCD/OPP

Laux

CS

Rsense

LEB1 +

-

grandreset

IpFlag

PWMreset

Up

Down

TIMERReset

FB/4

OPP

VILIMIT

+

-

LEB2

VCS(stop)

CsStop

DRVS

R

Q

Q

Stop controller

S

R

Q

Q

CS after LEB1 +

-

S

R

Q

Q

Vcc

aux

managementlatch

Vdd

faultgrandreset

grandreset

DRV

IpFlag+

-

PWMreset

Up

Down

TIMERReset

VCCstop

FB/4

VILIMIT

VOPP+

+

-VCS(stop)

CS after LEB2 CSstop

t LEB2 < tLEB1

VCC

CSstop

Short-Circuit Protection (A and C versions)• A and C versions: the fault is latched.

– VCC is pulled down to 5 V and waits for ac removal.

SCR delatcheswhen ICC < ICCLATCH

• Auto-recovery short circuit protection: the controller tries to restart

• Auto-recovery imposes a low burst in fault mode.

VDS

VCC

Low average input power in fault condition

Short Circuit Protection (B and D)

S

R

Q

Q

+

-

Vcc

auxVdd

faultgrandreset

to DRV stage

IpFlag+

-

+

-

PWMreset

Up

Down

TIMERReset

VCCstopCS after LEB1

FB/4

VILIMIT

VOPP+

CS after LEB2

t LEB2 < tLEB1

CSstop

VCS(stop)

grandreset

managementVCC

Fault Pin Combinations

• OVP and OTP or OVP and BO combined on one pin.• Less external components needed.

time

VFault

OK

Latch!

Latch!

time

VFault

OK

BO

Latch!

• OVP / OTP– NCP1380 A & B versions

• OVP / BO– NCP1380 C & D versions,

NCP1379

Agenda

1. Quasi-Resonance (QR) Generalities

2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

Step by Step Design Procedure

• Calculating the QR transformer

• Predicting the switching frequency

• Implementing Over Power Compensation

• Improving the efficiency at light load with the VCO mode

• Choosing the startup resistors

• Implementing synchronous rectification

Design Example• Power supply specification:

– Vout = 19 V

– Pout = 60 W

– Fsw,min = 45 kHz (at Vin = 100 Vdc)

– 600 V MOSFET

– Vin = 85 ~ 265 Vrms

– Standby power consumption < 100 mW @ 230 Vrms

T1

..

Vout

Gnd

Vbulk

Turns Ratio Calculation

,ds max dss DV BV k=

Derate maximum MOSFET BVdss:

For a maximum bulk voltage, select the clamping voltage:

Deduce turns ratio:

, ,clamp ds max in max osV V V V= − −

( )c out fsps

p clamp

k V VNNN V

+= =

BVdss

Vds,max

Vclamp

Vbulk,max

15% derating

Vos

Vreflect

kc: clamping coef.

kc = Vclamp / Vreflect )

Vos: diode overshoot

kD: derating factor

How to Choose kc• kc choice dependant of Lleak (leakage inductance of the transformer) • kc value can be chosen to equilibrate MOS conduction losses and

clamping resistor losses.

1out c

Rclamp leakc

P kP kkη

=−2

, 2, , ,

4 13

out cMOS on dson

in min in min dss D in max os

P kP RV V BV k V Vη

⎛ ⎞= +⎜ ⎟⎜ ⎟− −⎝ ⎠

1.2 1.5 1.8 2.1 2.4 2.7 30

1

2

3600-V MOSFET

PRclamp

PMOS,on @ Vin,min

P los

s(W

)

kc

Ptot ≈ 2.5 Wkleak=0.005

kleak=0.008

kleak=0.01

Curves plotted for:Rdson = 0.77 Ω at Tj = 110 °CPout = 60 WVin,min = 100 Vdc

Primary Peak Current and Inductance

, ,

,

pri peak pri pri peak pri pssw pri lump

in min out f

I L I L NT L C

V V Vπ= + +

+

2,

12out pri pri peak swP L I F η=

,

212 ps out lump swoutpri peak

in,min out f

N P C FPIV V V

πη η

⎛ ⎞= + +⎜ ⎟⎜ ⎟+⎝ ⎠

2,

2 outpri

pri peak sw

PLI F η

=

ton toff

tv

Ipri,peak

ton toff tv0

DCM

Coss contributionalone.

RMS Current• Calculate maximum duty-cycle at maximum Pout and minimum Vin:

• Deduce primary and secondary RMS current value:

, , 3max

pri rms pri peakdI I=

,,

13

pri peak maxsec rms

ps

I dIN

−=

,,

,

pri peak primax sw min

in min

I Ld F

V=

Ipri,rms and Isec,rms Losses calculation

Design Example

, , ,0.433.32 1.26

3 3max

pri rms pri peak pri rmsdI I I A= = ⇒ =

,, ,

1 3.32 1 0.43 5.83 0.25 3

pri peak maxsec rms sec rms

ps

I dI I AN

− −= = ⇒ =

,,

,

3.32 285 45 0.43100

pri peak primax sw min max

in min

I L µd F k dV

×= = ⇒ =

,

( ) 1.3 (19 0.8) 0.25600 0.85 375 10

c out fps ps

Vdss D in max os

k V VN N

B k V V+ × +

= = ⇒ ≈− − × − −

,

,

22 1

2 60 1 0.25 2 60 250 45 3.320.85 100 19.8 0.85

ps out lump swoutpri peak

in,min out f

pri peak

N P C FPIV V V

p k I A

πη η

π

⎛ ⎞= + +⎜ ⎟⎜ ⎟+⎝ ⎠

× × × ×⎛ ⎞= + + ⇒ =⎜ ⎟⎝ ⎠

2 2,

2 2 60 2853.32 45 0.85

outpri pri

pri peak sw

PL L µHI F kη

×= = ⇒ =

× ×

Based on equations from slides 11 to 14:

Turns ratio:

Peak current:

Inductance:

Max. duty-cycle:

Primary rms current:

Secondary rms current: