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Power Electronic Systems Laboratory
Semester Thesis SS 05
Development of a 600 W Power Supply
Stefan Fuchs, Jörg [email protected], [email protected]
Supervisor: Marcelo Lobo HeldweinProfessor: Prof. Dr. J. W. Kolar
24th September 2005
Abstract
This project aims to develop a600W power supply prototype. The final systemshould provide a single output voltage of48V DC and work with input voltages of110V, 60Hz and240V, 50Hz. It must employ PFC1.
Three different topologies are given to start with. After loss and efficiency calcu-lations as well as a simulation of each of them, one is chosen, designed and built.
The selection criteria are efficiency regarding power, the size and thermal aspects.
A two-stage topology, consisting of a boost and a half-bridge converter connectedin series, seems to be the most promising solution. The boost converter providesPFC and the half-bridge converter allows easy cancellation of the100 or 120Hzvoltage ripple at the output. The second stage is not part of this project as thereis not enough time even for the first stage. Thus the developed prototype outputs≈ 600W at410V instead of600W at48V .
1Power Factor Correction
Contents
1 Summary 11.1 Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Unsolved Problems. . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Tasks Splitting. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Topology Evaluation 32.1 Topologies for Discussion. . . . . . . . . . . . . . . . . . . . . 32.2 Two-Stage Converter. . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Boost Converter . . . . . . . . . . . . . . . . . . . . . . 42.2.2 Second-Stage Half-Bridge Converter. . . . . . . . . . . 5
2.3 Isolated SEPIC Converter. . . . . . . . . . . . . . . . . . . . . . 62.4 Flyback Converter. . . . . . . . . . . . . . . . . . . . . . . . . . 72.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Power Circuit Design 103.1 Power Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Power Components Design. . . . . . . . . . . . . . . . . 103.1.2 Thermal Design. . . . . . . . . . . . . . . . . . . . . . . 123.1.3 Protection Circuit. . . . . . . . . . . . . . . . . . . . . . 153.1.4 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Auxiliary Power Supply. . . . . . . . . . . . . . . . . . . . . . . 193.2.1 Specification. . . . . . . . . . . . . . . . . . . . . . . . 193.2.2 Power Circuit Design. . . . . . . . . . . . . . . . . . . . 20
3.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.3.1 The Integrated PWM Controller. . . . . . . . . . . . . . 203.3.2 Boost Converter Control. . . . . . . . . . . . . . . . . . 213.3.3 Flyback Converter Control. . . . . . . . . . . . . . . . . 27
4 Construction and Testing 304.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Arrangement. . . . . . . . . . . . . . . . . . . . . . . . 304.1.2 Volume Efficiency . . . . . . . . . . . . . . . . . . . . . 31
4.2 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.3 Flyback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . 334.4 Boost Converter Testing. . . . . . . . . . . . . . . . . . . . . . 33
4.4.1 Low Voltage Testing. . . . . . . . . . . . . . . . . . . . 334.4.2 Discovered Problems and Future Investigations. . . . . . 34
A Loss Calculation Formulas 35A.1 Loss Calculations including Current Ripple. . . . . . . . . . . . 35
A.1.1 The Hard Way . . . . . . . . . . . . . . . . . . . . . . . 35A.1.2 Two-Stage Converter. . . . . . . . . . . . . . . . . . . . 35
A.2 Calculations neglecting Current Ripple. . . . . . . . . . . . . . . 42A.2.1 Two-Stage Converter. . . . . . . . . . . . . . . . . . . . 42
i
A.2.2 SEPIC Converter. . . . . . . . . . . . . . . . . . . . . . 44A.2.3 Flyback Converter . . . . . . . . . . . . . . . . . . . . . 45
A.3 Two-Stage Converter Loss Simulations using Simplorer. . . . . 48
B Losses Measurement Circuit Schematics 52
C Prototype Schematics and Layout 54
D Controller Design and Simulation Matter 62D.1 PFC Voltage and Current Controller Design. . . . . . . . . . . . 62
D.1.1 Matlab Script. . . . . . . . . . . . . . . . . . . . . . . . 62D.1.2 Simplorer Schematics and Results. . . . . . . . . . . . . 66
D.2 Auxiliary Flyback Controller Design. . . . . . . . . . . . . . . . 68D.2.1 Matlab Script. . . . . . . . . . . . . . . . . . . . . . . . 68
E Completion 69E.1 Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
E.1.1 What is working . . . . . . . . . . . . . . . . . . . . . . 69E.1.2 Voltage Loop. . . . . . . . . . . . . . . . . . . . . . . . 69E.1.3 Current Loop. . . . . . . . . . . . . . . . . . . . . . . . 69
E.2 Electrical Specification. . . . . . . . . . . . . . . . . . . . . . . 70E.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . 71
E.3.1 Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 71E.3.2 Static Measurements. . . . . . . . . . . . . . . . . . . . 76
E.4 Recommended Improvements. . . . . . . . . . . . . . . . . . . 80
ii
List of Figures
2.1 Two-Stage converter topology. . . . . . . . . . . . . . . . . . . 42.2 SEPIC converter topology. . . . . . . . . . . . . . . . . . . . . 62.3 Flyback converter topology. . . . . . . . . . . . . . . . . . . . . 7
3.1 Thyristor driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2 Measured MOSFET voltage and current. . . . . . . . . . . . . . 133.3 MOSFET energy (left) and current (right) with switch-on/-off lo-
cations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 Switching losses curves for MOSFET (left) and diode (right). . . 143.5 Modified simulation model. . . . . . . . . . . . . . . . . . . . . 163.6 Designed Differential Mode Filter. . . . . . . . . . . . . . . . . 173.7 Differential Mode voltage without and with filter. . . . . . . . . 173.8 Measurement of the capacitance and resistance between the drain
of the MOSFET and the heat sink. . . . . . . . . . . . . . . . . 183.9 Designed Common Mode Filter. . . . . . . . . . . . . . . . . . 193.10 Power part of the auxiliary power supply. . . . . . . . . . . . . . 203.11 Simulink model of the current controllerKi . . . . . . . . . . . . 213.12 Simulink model of the voltage controllerKv . . . . . . . . . . . . 223.13 Simulink model of the rectifier’s backward behaviour. . . . . . . 223.14 Simulink model of the boost converter. . . . . . . . . . . . . . . 233.15 Bode plot of the current loop transfer functionLi . . . . . . . . . 253.16 Bode plot of the voltage loop transfer functionLv at600W . . . . 273.17 Bode plot of the voltage loop transfer functionLv at10W . . . . 283.18 Bode plot of the AUX-Flyback’s voltage loop transfer functionLfv 29
4.1 Top view of the board (120× 84mm) with dyed functional regions 304.2 Picture with dimensions of input filter. . . . . . . . . . . . . . . 324.3 Frequency-dependent attenuation. . . . . . . . . . . . . . . . . . 32
A.1 Replacement model for the boost MOSFET. . . . . . . . . . . . 36A.2 Right hand side of eq.A.8 . . . . . . . . . . . . . . . . . . . . . 37A.3 Nomenclature of time intervals during switching. . . . . . . . . . 38A.4 Loss simulation for the first stage of the two-stage converter. . . 49A.5 Loss simulation for the second stage, normal operation. . . . . . 50A.6 Loss simulation for the second stage, worst casevz = 107V . . . 51
B.1 Power part of the loss measurement circuit. . . . . . . . . . . . . 52B.2 Control and gate driver of the loss measurement circuit. . . . . . 53
C.1 Converter overview. . . . . . . . . . . . . . . . . . . . . . . . . 54C.2 Power part including startup circuit. . . . . . . . . . . . . . . . . 55C.3 Auxiliary power supply. . . . . . . . . . . . . . . . . . . . . . . 56C.4 Common- and differential mode input filter. . . . . . . . . . . . 57C.5 Control circuit for boost and AUX converter, incl. bootstrap supply58C.6 Components on the top side (heatsink side). . . . . . . . . . . . 59C.7 Components on the bottom side. . . . . . . . . . . . . . . . . . 59C.8 Top /1st layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C.9 2nd layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
iii
C.10 3rd layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61C.11 Bottom /4th layer . . . . . . . . . . . . . . . . . . . . . . . . . 61
D.1 Simulation of controller startup phase. . . . . . . . . . . . . . . 66D.2 Simulation schematic including LISN and EMC filter. . . . . . . 67
E.1 Steady state operation at660W , 110V ; input current (5A/div),phase voltage (50V/div) . . . . . . . . . . . . . . . . . . . . . . 71
E.2 Steady state operation at660W , 230V ; input current (2A/div),phase voltage (100V/div) . . . . . . . . . . . . . . . . . . . . . . 71
E.3 Steady state operation at660W , 110V ; boost inductor current (5A/div),converter output voltage (200V/div), time scale2ms/div . . . . . 72
E.4 Steady state operation at660W , 110V ; converter output voltageripple (10V/div), time scale2ms/div . . . . . . . . . . . . . . . 72
E.5 Steady state operation at660W , 110V ; boost inductor current (5A/div),control voltage (1V/div, it is proportional to the inverse of the dutycycle), converter output voltage (200V/div), time scale2ms/div . 73
E.6 Steady state operation at660W , 110V ; boost inductor current (10A/div),voltage across the switch (200V/div), time scale2ms/div . . . . 73
E.7 Steady state operation at660W , 110V ; boost inductor current (10A/div),voltage across the switch (200V/div), time scale1µs/div . . . . . 74
E.8 Switch turn on detail: operation at660W , 110V ; boost induc-tor current (10A/div), voltage across the switch (200V/div), timescale20ns/div . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E.9 Switch turn off detail: operation at660W , 110V ; boost induc-tor current (10A/div), voltage across the switch (200V/div), timescale20ns/div . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E.10 Efficiency curves. . . . . . . . . . . . . . . . . . . . . . . . . . 76E.11 Total losses curves. . . . . . . . . . . . . . . . . . . . . . . . . 76E.12 Heatsink temperature rise∆T curves. . . . . . . . . . . . . . . . 77E.13 Input current RMS value curves. . . . . . . . . . . . . . . . . . 77E.14 Power factor curves; The voltage THD was kept below0.7% for
all the measurements.. . . . . . . . . . . . . . . . . . . . . . . . 78E.15 Input current THD curves; The voltage THD was kept below0.7%
for all the measurements.. . . . . . . . . . . . . . . . . . . . . . 78E.16 Input current phase displacement. . . . . . . . . . . . . . . . . . 79E.17 Output voltage regulation curves. . . . . . . . . . . . . . . . . . 79
iv
List of Tables
1.1 Individual assignments. . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Common design constraints for all topologies. . . . . . . . . . . 32.2 Currents of the boost converter. . . . . . . . . . . . . . . . . . . 52.3 Currents in the second-stage half-bridge converter. . . . . . . . . 52.4 Currents of the SEPIC converter. . . . . . . . . . . . . . . . . . 62.5 Currents of the PFC flyback converter. . . . . . . . . . . . . . . 82.6 Estimated efficiencies of the candidate topologies. . . . . . . . . 9
3.1 Switching losses coefficients for MOSFET and diode. . . . . . . 143.2 Components used in the DM filter. . . . . . . . . . . . . . . . . 163.3 Components used in the CM-filter. . . . . . . . . . . . . . . . . 193.4 Estimation of power requirements. . . . . . . . . . . . . . . . . 193.5 Parameters of the current controllerKi . . . . . . . . . . . . . . . 243.6 Parameters of the voltage controllerKv . . . . . . . . . . . . . . 263.7 Parameters of the AUX-Flyback’s voltage controllerKv . . . . . . 29
4.1 Volume efficiency of subsystems. . . . . . . . . . . . . . . . . . 31
A.1 Switching times of boost switch. . . . . . . . . . . . . . . . . . 39A.2 Power losses in the boost switch. . . . . . . . . . . . . . . . . . 40A.3 Calculated worst case losses for the two-stage converter. . . . . . 42
C.1 Component numbering scheme. . . . . . . . . . . . . . . . . . . 54
E.1 AC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70E.2 DC Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70E.3 AUX Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70E.4 Physical Specification. . . . . . . . . . . . . . . . . . . . . . . . 70E.5 Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 70
v
Summary
1.1 Assignment
The final aim is to have a working prototype of a power supply with PFC fulfillingthe requirements of table2.1. The most important requisites are
• universal input voltage range
• 600W output power at48VDC
• galvanic isolation from the mains
• hold up time of half a mains period
• high efficiency
During the project, after the two-stage converter has been chosen, it was decidedthat only the first stage of it, the boost converter, is built. The available time wastoo short to design the second stage also.
1.2 Solution
The project is split up in multiple subtasks:
1. selection of one out of three converter topologies based on efficiency calcu-lations and simulations
2. selection of power components and measurement of the switching losses
3. design of the cooling system, auxiliary power supply, input filter and controlcircuits
4. simulations
5. construction and testing
1.3 Results
Theoretical calculations for three topologies are carried out. A complete, singlephase PFC converter providing410VDC at600W is designed and built. It presentsa volumetric density of1.6 kW
dm3 .It is tested at low voltage conditions. Unfortunately there was not enough time tofix some remaining issues to get the converter fully working.
1
1.4 Unsolved Problems
The following known problems are not solved yet:
• The layout of the prototype board uses clearances that work but are too nar-row in a safety regulation context. A final converter needs a new layoutwhich obeys not only electrical but safety constraints also.
• The converter produces a large (up to100%) overshoot in the output volt-age during startup. This seems to come from the slow voltage controllertransient. Interestingly, none of the simulations shows this behaviour. Atnominal voltages, this overshoot usually causes a snap through destroyingthe controller IC. It should be possible to prevent this by implementing aslow start. The used PFC controller IC does neither provide such a featureexplicitly nor is it possible to ramp up the internal reference voltage of thevoltage controller. Future tests might prove that the PTC resistor implementsa working slow start. If that is not the case, it might be neccessary to use adifferent controller IC to solve this issue.
• The controller IC does not start the auxiliary power supply before a relativelyhigh output voltage of the boost converter is reached. A redesign of thebootstrap supply is needed once the exact energy requirement during thestartup phase can be measured. If a different controller IC is used to solvethe previous problem, this new controller should be able to start the auxiliarypower supply at lower voltages. The auxiliary power supply is designed towork with minimal input voltages of105VDC .
1.5 Tasks Splitting
A large part of the project is common effort, some tasks were split. The followinglist shows who worked on which task:
S. Fuchs J. Meilitopology eval. neglecting current ripple boost inductor designtest circuit design & loss measurements inrush current protection designcontrol circuit design input filter design
Table 1.1: Individual assignments
1.6 Conclusion
It is probably one of the most interesting projects to build a whole converter fromscratch. The learning curve was extremely steep as the converter was built more orless in parallel to the lecture teaching the according matter. The effort neccessaryis a lot more than one would except for a semester thesis. The authors thus recom-mend to do similar projects only as diploma thesis or if a lot of experience on theparticular subject is already available.
2
Topology Evaluation
2.1 Topologies for Discussion
The evaluation phase started with three different topologies for each of which theexpected losses were estimated. The following converter topologies were given tostart with:
• two-stage (fig2.1): A combination of a PFC boost converter with a DC/DChalf-bridge converter attached to its output.
• single-stage SEPIC (fig2.2): A topology which is usually used to obtainoutput voltages ranging from below to above the input voltage at low power.This topology can also be controlled to operate in PFC mode.
• single-stage flyback (fig2.3): This topology is commonly used for low powerrated supplies. Only its discontiuous mode of operation is discussed in whichPFC is naturally achieved.
For each of those topologies the requirements given in table2.1apply. It has to benoted that the input current ripple constraint cannot be obeyed for the discontin-uous mode of the flyback converter. The input filters are neglected for the lossescalculations.
output voltage Vo 48 VDC
output power Po 600 Wmaximum input voltage Vmax,EU 230 + 20% Vrms
minimum input voltage Vmin,US 110− 20% Vrms
mains frequency range 45 . . . 65 Hzinput current ripple ≤ 15% of max input currentswitching frequency fs 250 kHzfull power at output during half period of mains outage
Table 2.1: Common design constraints for all topologies
The losses are calculated twice. The first attempt is to include the current ripple inall equations. This works fine withMathematica1 until the peak losses have to beaveraged over half a mains period. The large expressions require too much compu-tation time. Thus it is neccessary to approximatePv(ϕ) by Pv sin2(ϕ). WhereasPv is calculated via the average power requirement. Used equations are listed inappendixA.
For the second attempt, the current ripple gets neglected. The resulting equationscan be handled manually with paper and pencil. The results for each investigated
1http://www.wolfram.com/
3
converter topology are summarized in the following sections. Detailed equationscan be found in appendixA.
Finally the losses are calculated from simulation results of each topology usingSimplorer2.
2.2 Two-Stage Converter
The two-stage topology (fig2.1) has the advantage that there are many integratedcontrol circuits available to realise a PFC power supply. This reduces the amountof required components and thus helps to reduce costs. Another clear advantage isthe intermediate high voltage power storage. The intermediate voltage may have a100 or 120Hz ripple. The second stage converter is able to suppress this.
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DFL1
C1
C2
Lp Ls
T2
T3
Dr Dr
Dr Dr
CoV1 VoT1
Figure 2.1: Two-Stage converter topology
The calculations are split up into boost and 2nd-stage converters.
2.2.1 Boost Converter
It is assumed that the input current has an ideal, sinusoidal shape. This is ensuredby the closed loop controlled PFC condition. Worst case currents result at lowinput voltage.
Two special variables,M and I1, are defined to express the component’s averageand rms currents:
M :=Vo
V1
I1 :=√
2P
V1,rms(2.1)
The average and rms currents relate to half a mains period.
The rms and average currents in the components are calculated based onM andI1. The results are shown in table2.2.
2http://www.ansoft.com/products/em/simplorer/
4
comp. Iavg Irms
Di1π I1
12 I1
DF1
2M I1
√4
3πM · I1
T1
(2π −
12M
)I1
√12 −
43πM · I1
L12π I1
1√2I1
C1,2 0√
43πM − 1
4M2 · I1
Table 2.2: Currents of the boost converter
2.2.2 Second-Stage Half-Bridge Converter
A half-bridge converter is appended to the boost converter as shown in figure2.1toget an output voltage of48V . This adds electrical isolation which is not providedby the boost converter. The half-bridge converter needs to operate with a large inputvoltage variation ranging from193V to about450V . This is required because theoutput filter capacitors of the boost converter serve as an energy storage to keep theload under full power as long as possible during a mains outage.
The worst case currents occur at the lowest input voltage of193V . The inputvoltage is assumed to be constant so there is no need to average over a mainsperiod. The half-bridge converter’s input voltagevz is defined to be half of theboost converter’s output voltage.
vz :=12Vout,boost (2.2)
The results are shown in table2.3.
comp. Iavg Irms
Dr12Io Io
(D2 + 1
4
)T2,3
Po2vz
√D Po
2vz
Lp 0 2√
DPo
(1
nVo− 1
2vz
)Co 0
√DPo
(1
nVo− 1
2vz
)Table 2.3: Currents in the second-stage half-bridge converter
Please note thatD is defined to be the duty cycle of one of the two transistors.Thus the transformer with primary inductanceLp is connected to the input voltagevz during2DTs per switching interval.
5
2.3 Isolated SEPIC Converter
The SEPIC converter as shown in figure2.2works almost the same way as a boostconverter. It is similar to the cuk converter which can be derived from a buck-boosttopology.
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T1
L1C1
n : 1
DF Co VoV1 L2
Figure 2.2: SEPIC converter topology
The SEPIC converter used here employs a two winding inductor instead of twoseparate ones to provide electrical isolation and a low output voltage compared toits input voltage. A clear drawback are the extremely high currents in the mainswitch. They are forced by the condition that there must be no average currentthroughC1.
I1 andM in table2.4are the same as for the boost converter in section2.2.1.
comp. Iavg Irms
Di1π I1
12 I1
DF1
2M I1
√4
3πM + 38M2 · I1
T12π I1
√12 + 4
3πM · I1
L12π I1
12 I1
L21
2M I1
√4
3πM · I1
C1 0 1√2I1
Co 0√
I21
(4
3πM + 38M2
)− I1Io
M + I2o
Table 2.4: Currents of the SEPIC converter
6
2.4 Flyback Converter
The proposed flyback converter (fig2.3) has three parallel outputs, realised byputting three secondary windings on the energy transfer inductor. This reduces thecurrent ripple in the output diode and the demagnetisation timeD2 during whichthe energy in the inductor gets transferred to the output. In figure2.3 only one ofthese output stages is shown.
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Co
n : 1
DFLs
V1
Vo
T1
Lp
Figure 2.3: Flyback converter topology
The current ripple cannot be neglected because the flyback converter operates indiscontinuous mode. This leads to another approach than taken for the boost andSEPIC converters. First the magnetisation timeD1 is calculated via the require-ment thatPin(ϕ) ∝ sin2(ϕ). This leads to
D1 =2V1
·√
LpPo
Ts(2.3)
which is constant. That means the PFC flyback converter can be controlled byclosing the loop fromVo, the output voltage, toD1, the primary duty cycle, witha suitable controller. It is important that the controller does not try to level out the100 or 120Hz ripple of the output. This would introduce unwanted harmonics onthe input current.
As D1 depends onLp, the latter is calculated next. The winding ration of theinductor causes voltage stresses on the transistor. Thusn is limited by
n ≤VDS,max − V1
Vo=⇒ n ≈ 3 (2.4)
Lp results as follows:
D1 ≤nVo
V1 + nVo
∣∣∣∣V1=
√2Vmax
and Lp ≤V 2
1 D21Ts
4Po
∣∣∣∣∣V1=
√2Vmin
(2.5)
=⇒ Lp ≤ 1.87µH (2.6)
Then the local averageIa(ϕ) and local rmsIr(ϕ) input currents are defined. This isan intermediate step between the switching frequency current ripple and the mainsfrequency related average and rms currents.
Ia := 2Po
V1Ia(ϕ) = Ia sin(ϕ)
Ir :=√
3D31
3 · V1Lp
Ts Ir(ϕ) = Ir sin(ϕ)(2.7)
7
On the secondary side only one of the three outputs gets evaluated. The multiwinding inductor has a winding ration := N1
N2,3,4. Now the demagnetisation duty
ratio is needed. It varies sinusoidally.
D2 = 2nVo
√LpPo
TsD2(ϕ) = D2 sin(ϕ) (2.8)
As for the primary side, the currentsIa2 andIr2 are defined for the secondary side.m = 3 is the number of parallel outputs.
Ia2 := 2PomVo
Ia2(ϕ) = Ia2 sin2(ϕ)
Ir2 :=√
3D32
3 · n2VoTsmLp
Ir2(ϕ) = Ir2 ·√
sin3(ϕ)(2.9)
It is now possible to express the average and rms currents of the components basedon the constants worked out so far.
comp. Iavg Irms
Di1π Ia
√2
4 Ir
DF12 Ia2
2√3π
Ir2
T1, Lp2π Ia
√2
2 Ir
Co1
6Lpm√
π·(16D3
2n4T 2
s V 2o − 18D2
2IoLpmn2πTsVo + 36I2oL2
pm2π) 1
2
Table 2.5: Currents of the PFC flyback converter
2.5 Conclusion
The calculated and simulated (s.A.3) losses are shown in table2.6. The assumedauxiliary power consumption is13W for the two-stage converter and10W for theothers. All efficiencies are corrected to take the auxiliary power consumption intoaccount. The current ripple is neglected forηcalc2. ηcalc1 is the result of the firstattempt which obeys the current ripple in the calculations.
The relatively high95% efficiency for the sepic converter seems to come from thelarge but neglected current ripples through the transistor and the diode. The low,simulated efficiency of69% is expected after comparing the currents of the SEPICconverter to the ones common in a two-stage topology.
8
ηcalc2 [%] ηcalc1 [%] ηsim [%]two-stage 89 84 85sepic 85 93 69flyback3 79 - -
Table 2.6: Estimated efficiencies of the candidate topologies
The approach taking the current ripple into account is complex and the resultsare not really better. Thus the calculations for the flyback converter are left out.There are no simulation results for the flyback converter because its slow voltagecontroller requires a very long simulation time. This leads to an unmanageableamount of data.
The large peak currents in the discontinuous flyback and the large switching andon-state losses in the SEPIC converter let the two-stage topology win this compar-ison.
9
Power Circuit Design
3.1 Power Stage
3.1.1 Power Components Design
Boost Inductance
For the design of the boost inductanceL100 (fig C.2) it is important to keep thesize of the core as small as possible. The height of the inductor should not exceedthe height of the whole converter, which is expected to be around3.5cm.
The data of several shapes and materials are collected and compared to each otherin order to find a suitable inductor core. Finally a choice has to be made betweenan E-core shape fromFerroxcube1 with 3C90 ferrite material and a toroidal coreshape fromMicrometals2 with N70, an iron powder material. The toroidal ironpowder core has the big advantage that it is designed with a distributed air gap.This allows the maximum flux to be much higher than in an E-core with a small airgap.
For the evaluation of the total losses in the inductor the copper losses and the corelosses have to be calculated. This is done separately. As the high-frequency currentripple is small, skin and proximity effects are neglected. The copper losses can becalculated using formula3.1
PCu = RCu · I2L,rms (3.1)
with a resistivity of the copper wire of
RCu = ρCu ·lCu
A. (3.2)
The core losses are calculated using equation3.4with a peak flux given by equation3.3. The values of a, b, c and d are material dependent and can be found on themanufacturer’s homepage.3
Bi(f) =L100 · Ii(f)
A ·N(3.3)
Pcore = V ·n∑
i=1
fi
a
Bi3 + b
Bi2.3 + c
Bi1.65
+ d · f2i · Bi
2
(3.4)
Since the peak flux is indirectly depending on the frequency, the core losses arecalculated for every significant frequency component from DC to2.5MHz. A
1http://www.ferroxcube.com2http://www.micrometals.com3http://www.micrometals.com/200cparts/200C_B.pdf
10
spectrum of the current in the boost inductor can be obtained using the DAY-postprocessor of Simplorer. By applying a filter, the smallest frequency compo-nents are neglected and more than2300 remaining frequency components can beextracted and taken into account.
The toroidal coreT106 from Micrometals with anN70 material is found to bea suitable choice. For the39 turns needed, a copper wire with1.5mm diameteris used. The copper and core losses are calculated to be around2.4W and0.8Wrespectively. Regarding a thermal resistance of10.8K/W the temperature rise isfound to be around34K.
Main Switch
The boost MOSFET has to be able to switch on and off currents of up to12A. Thepeak rms current during a single switching cycle isIT,rms,pk:
M :=Vo
V1
I1 =√
2P
V1,rmsϕ =
π
2(3.5)
IT,rms,pk =
√I21 sin2(ϕ) ·
(1− sin(ϕ)
M
)≈ 8A (3.6)
Additionally the MOSFET has to sustain drain to source voltages of at least500V .
TheSPP20N60C3of the CoolMOS series produced by Infineon is a good choice.It optimises on-state losses against calculated switching losses so they are similar.This leads to minimised losses on the transistor.
See section3.1.2for details about measured switching losses.
Input Rectifier Bridge
The two highside diodes of the rectifier bridge are replaced by thyristors. The ideaof using thyristors instead of another pair of diodes is that they can be switched onsome milliseconds later when the output capacitors are almost fully charged. Forthe time between the switch-on of the converter and the activation of the thyristors,a bypass circuit consisting ofD104, D105, R103 andD111 limits inrush currents.The PTC thermistorR103 in combination with two diodes can guarantee a safestart during which the voltage in the output capacitance is built up slowly. Theresistivity of the thermistor being used is about600Ω at moderate temperaturesand rises rapidly when the current (and therefore the temperature) reaches a certainlevel. The diodes used are standard recovery diodes with a voltage rating of1kVand a current rating of1A. The transformer is built of anEP7-3F3 core fromFerroxcube with 18 windings on each side. The circuit driving the thyristors isshown in figure3.1.
11
D10110BQ060
D10910ETS08
D11010ETS08
D10210BQ060
D10010BQ060
D10310BQ060
D106TIC126M
D107TIC126M
R105
330R
R106
330R
T100
EP7-3F3
L100
187u
C100
220n
T1g
R108
R010
R103
B59884C120A70
D105S1M
D104S1M
Figure 3.1: Thyristor driver
Output Filter
The height of the output capacitors is an important criteria. It should not be chosenany bigger than the height of the boost inductance which is measured to be a bitmore than3cm. Another important constraint is the rms-current at a frequencyof 120Hz which is again calculated with the equation of table2.2 and checkedwith the DAY-postprocessor of Simplorer. Because of the high current of about1.4A a solution with two capacitors in parallel is chosen which gives a total of fourcapacitors for the output buffer. The main advantage of this solution is that thecomponents can be chosen to be rather small.
3.1.2 Thermal Design
Measurements
A circuit consisting of the final gate driver, transistor and diode combination is usedto measure the switching losses on the transistor and the diode. As the gate drivercircuit UCC28513contains not only the gate driver but all neccessary control logictoo, it has to be configured in a manner to output a more or less constant, adjustableduty cycle. The schematics shown in figuresB.1 andB.2 (App. B) do just this.
The boost transistor, diode and inductor are connected in a buck configuration.Thus the current in the inductor rises during each on-period of the switch and free-wheels through the diode when the switch is off. This gives the same switchingbehaviour as in a boost configuration.
The measurements are carried out at a junction temperature of 100C. The inputcapacitorC900 gets charged to410V . Then the gate ofT950 is driven to GNDfor a short time. This enables switching of the transistorT900 for about4 cycles.The current in the inductorL900 rises to10 − 20A during the applied pulses.Measuring the voltage across and the current through the switch provides enoughdata to calculate the effective losses. The same procedure is done for the diode toobtain the reverse recovery losses.
Pulling the gate ofT950 to +15V disables switching ofT900 and enables opera-tion of the auxiliary power supply on the same test board. This allows to test thedesigned auxiliary power supply at this stage of the project.
12
0 5 10 15 20−0.5
0
0.5
1
1.5
2
t [µs]
I/12,
V/4
10
iv
Figure 3.2: Measured MOSFET voltage and current
Effective Losses
The measured current is delay compensated by3.8ns to lay in time with the voltagedata. This is required due to the non-syncronous behaviour of the current andvoltage probes. The result is shown in figure3.2.
There is no need to measure the losses at multiple, supplied voltages as the con-verter has a fixed output voltage.
The dissipated energy, since start of the measurement, is calculated by multiplyingthe current and voltage samples and then integrating over time. The resulting curveis expected to have jumps at the switching locations and to stay at the same valuewhile the MOSFET is off. Noise, oscillations and measurement errors work againstthis nice theory. In figures3.3each switch-on event is indicated by two red circlesand each switch-off event by two black circles. One circle at the start time of theevent, the other at the stop time.
0 5 10 15 20−5
0
5
10
15
20x 10−4
t [µs]
J
0 5 10 15 20−5
0
5
10
15
20
25
t [µs]
A
Figure 3.3: MOSFET energy (left) and current (right) with switch-on/-off locations
The switch on and off locations including their durations are read out of the plots.This gives a set of current↔ energy relations for switch-on as well as for switch-
13
off events. It is possible to fit, at a certain switching frequency, a curve of thefollowing form into these data:
Pon = s12I2 + s11I + s10
Poff = s22I2 + s21I + s20
⇒
s2 = s12 + s22
s1 = s11 + s21
s0 = s10 + s20
(3.7)
Pswitching = s2I2 + s1I + s0 (3.8)
The switching frequency for these calculations is260kHz. The nominal switch-ing frequency of the converter is250kHz but component tolerances can lead to ahigher frequency.
Taking multiple measurements and fitting a curve into them using least square ap-proximation leads to the coefficients listed in tables3.1with the according curvesplotted in figures3.4. The circles in these figures represent the measurements. Thesame is done for the diodeD900 resulting in the coefficientsd2,1,0.
s2 0.2311s1 0.9638s0 7.5073
d2 0.0262d1 −0.5186d0 6.0327
Table 3.1: Switching losses coefficients for MOSFET and diode
0 5 10 15 20 250
20
40
60
80
100
120
140
A
W
pon
poff
ptot
0 5 10 15 20 252
3
4
5
6
7
A
W
Figure 3.4: Switching losses curves for MOSFET (left) and diode (right)
For the diode only the reverse recovery losses are considered because the otherswitching losses are very small and disappear in measurement noise.
The diode switching losses seem to increase at currents above10A. The reasonfor this behaviour is probably too much switching noise or measurement errors athigh currents. The three rightmost circles in the right plot of figure3.4 diverge invertical direction more than they should. But as the maximum current of interest is12A and the losses in the diode are much smaller than those in the MOSFET, thisfact does not disturb.
The worst case switching losses are31W in the MOSFET and4W in the SiCdiode. On-state losses of15W and3W respectively have to be added.
Based on these calculations and the losses of other components attached to theheatsink, it is concluded that the heatsink’s thermal resistance must be≤ 0.7K/W .This can be achieved with certain6× 6 cm2 heatsinks and an attached fan.
14
3.1.3 Protection Circuit
Overcurrent Protection and Power Limitation
The inrush current is limited by the circuit described in section3.1.1. The currentis actively limited by the control circuit during normal operation. The maximumcurrent in the boost inductor is12A. This limit is set by the resistorsR402 andR419. The boost transistorT101 is switched off when thePKLMTinput of U401
(s.3.3.1) rises above0V .
Another protection against too much power at the output is the voltage feed forwardlimitation of the integrated controllerU401. Too low rms input voltages saturate thefeed forward branch and thus the requested current does not increase further witha falling input voltage. The input bridge rectifier thyristors are turned off whenthe boost transistor stops switching. This places the PTC resistor in series with therectifier current, protecting against short circuits in the output port or surges in theinput.
Thermal Considerations
The prototype does not use active thermal monitoring. It is designed to stay atallowed temperatures as long as the ambient temperature does not exceed50C.The chosen auxiliary power supply method, which uses the output power of theboost converter, inhibits an active shutdown because this would lead to immediatereactivation of the converter. For an active shutdown, the control circuit wouldneed to be kept under power while the main converter is inactive.
3.1.4 Input Filter
An input filter is connected between the power line and the rectifier. One of themain tasks of this filter is to protect the power line from being disturbed by theelectromagnetic interference generated by the switching transistor. On the otherhand the converter must be protected against high frequency disturbances comingfrom the power line.
The whole filter is composed of two different parts: a Differential Mode (DM) filterand a Common Mode (CM) filter. The DM filter is needed to suppress noise currentflowing on both lines but in different directions whereas the CM filter suppressesnoise current flowing on both lines and in the same direction.
Differential Mode Filter
The simulation of the boost converter is modified (fig3.5) for proper design of theDM filter. Some of the components, like the boost inductance and the output capac-itors, are replaced by their real equivalent circuit diagrams. A LISN4 is added to the
4Line Impedance Stabilisation Network
15
simulation setup which provides a well defined impedance between the power lineand the converter and allows measuring high frequency (HF) conducted emissions.
CONSTPout
CONSTv2
CONSTV1rms
+ V Vin
GAIN
Isoll IerrLIMIT
DboostlimG(s)
Dboost PWM
PWMboost
Vg
T1
L1.I [A] IT1locrms.VALID5locrms.VALIT1rms.VALID5rms.VAL
t [s]
10
-1
0
2
4
6
8
0 11m2m 4m 6m 8m
I1
630
48
110*0.8
L1.I [A] MEAN1.VAL RMS1.VAL
t [s]
10
-1
0
2
4
6
8
0 11m2m 4m 6m 8m
MEAN VALUE
MEAN1
70,7%
RMS
RMS1
A
AM3
Vmain
250u 50u
8u
5
5
8u250u 50u
250n
50
50
250n
100p
187u
26.9p
10.8k
28.8m
5
220u
580m
220u
580m
220u
580m
220u
580m
Figure 3.5: Modified simulation model
The current at the output of the LISN is recorded using the ViewTool of Simplorer.A well defined timestep is chosen which results in the precise number of216 =65536 sample points during the time of one mains period.
The procedure stated in [10] is used to design the DM filter.Mathcad5 is usedto calculate the fourier transformation of the sampled current. Furthermore theneeded attenuation of the DM filter is evaluated to be around50dB at 160kHzwhich can be achieved by a two-stage filter design as shown in figure3.6. Table3.2 gives an overview of the components used. The total power dissipation in theDM filter is calculated to be0.5W . Figure3.7 shows the result of applying thedesigned filter to the converter. The red line indicates the class A6 limit which isrelevant here. It can be seen that the DM filter is able to suppress the HF noisebelow the class A limit at the worst case frequency of160kHz.
component value core material turns wire
X2, C304, C305 0.1µF
X2, C306 1.0µF
L302 20µH T50 Micrometals−N26 20 1.0mm
L303 40µH T60 Micrometals−N26 23 1.0mm
Table 3.2: Components used in the DM filter
Common Mode Filter
For the CM filter design the simulation model has to be further improved. Theinductances of the circuit paths are estimated by measuring the length of the pathsand by using an inductance per unit length of10nH/cm. The capacitances be-tween the semiconductors (MOSFET and diode) and the heat sink are also impor-tant. These values are measured with an impedance analyser. Figure3.8shows the
5http://www.mathcad.com6CISPR (Comité International Spécial des Perturbations Radioelectriques) standard for the elec-
tromagnetic compatibility of nonconsumer products.
16
100n
4.7
100n
4.7
20u 40u
1u
Figure 3.6: Designed Differential Mode Filter
Maxresultj
20 log 1 jinit j!if
floor j FRBW
ceil j FRBW
l
Vdml
1PV¦
§¨¨©
·
¹
jinit jd jenddif
1 otherwise
ª««««««¬
º»»»»»»¼
1 105 1 10620
30
40
50
60
70
80
90
100
110
120
130
140
150
160DM voltage without filter
Frequency [Hz]
DM
con
duct
ed e
mis
sion
[dB
uVrm
s]
1 105 1 10620
4.44
28.89
53.33
77.78
102.22
126.67
151.11
175.56
200DM voltage measured by LISN
Frequency [Hz]
DM
con
duct
ed e
mis
sion
[db
uVrm
s]
MB 160kHz Mid-band frequency (worst case attenuation is calculated for this frequency)
N:\input filter\differential mode\Filter 8 (44)
MaxQPk
k Mult
k
l
Maxresultl Mult¦
Mult 1 DMDB
k
k Mult
k
l
DMdBl Mult¦
Mult 1
MaxQPk
Maxresultk Mult
DMDBk
DMdBk Mult
1 105 1 10640
30
20
10
0
10
20
30
40
50
60
70
80
90
100DM voltage with filter
Frequency [Hz]
DM
con
duct
ed e
mis
sion
[dB
uVrm
s]
MB 160kHz
ClassAMB ClassA MB
ffund
ClassBMB ClassB MB
ffund
MEASMB Maxresultceil MB T( )
Maxresultceil MB T( )
Maxresultfloor MB T( )
!if
Maxresultfloor MB T( )
otherwise
MEASMB 76.82
Margin ClassBMB MEASMB
Margin 11.356 Final margn in dBPV
7. Calculating the stresses in the filter components for LF
7.1. Initial calculations
Input voltage definition:
N:\input filter\differential mode\Filter 14 (44)
Figure 3.7: Differential Mode voltage without and with filter
measurement of the capacitance between the drain of the MOSFET and the heatsink. Moreover the boost inductor and the output capacitors are measured to knowtheir HF models.
Another simulation is made in order to get the difference of the two currentsflowing from the lines to earth. Like for the DM filter, the fourier spectrum of themeasured current gives an idea of how much attenuation is needed to lower thenoise below the class A limit. The attenuation of the CM filter is calculated to beat least37dB at250kHz, including a6dB safety margin.
With the aid of the attenuation,
Attenuation = 37dB = 20 · Log
[Vcm0
Vcm
](3.9)
with Vcm0 andVcm as defined in equations3.10and3.11, and the constraint that
17
Figure 3.8: Measurement of the capacitance and resistance between the drain ofthe MOSFET and the heat sink
the50Hz-current through the capacitors of the CM filter have to be less than3mA,due to safety regulations, the values for all the components can be found (table3.3).
Vcm0 =Ipeak√
2·∣∣∣∣ ZLISN
ZLISN + ZL100 + ZC,leak
∣∣∣∣ = 40.8mV (3.10)
Vcm =Ipeak√
2·∣∣∣∣Z1 ·
Z2
Z2 + ZL300 + ZC302||(ZL100 + ZC,leak)
∣∣∣∣ (3.11)
with
Z1 =ZC302
ZC302 + ZL100 + ZC,leakand Z2 = ZLISN ||ZC300 (3.12)
From equation3.9 Vcm is found to be6.42mV . Two Y2-capacitors with a valueof 4.7µF each are chosen forC300 andC302. Y2 capacitors in SMD shapes canbe found up to4.7µF , and are here used due to their better HF performance andsmall size. The needed inductance, which is realised as a common mode choke,can be found using equation3.11. Because of the specially arranged wires aroundthe core, the common mode choke acts as a normal wire against DM noise and as ahigh impedance against CM noise, thus suppressing mainly the CM noise. Figure3.9shows the CM filter with its components.
18
component value core material turns wire
Y2, C300-C304 4.7µF
CM-choke, L300 1170µH V ACW398 V AC500F 2× 10 1.0mm
Table 3.3: Components used in the CM-filter
22
4.7u
22
4.7u
4.7u
4.7u
1170u
1170u
Figure 3.9: Designed Common Mode Filter
3.2 Auxiliary Power Supply
3.2.1 Specification
The auxiliary power supply delivers power to the control circuit, the gate driversand the fan. This DC-DC converter, based on a two transistor flyback topology, isable to power a second stage600W DC-DC converter besides the first stage. Theestimations listed in table3.4 lead to a total power consumption of about13W .Five transistors are considered, one for the first stage boost converter, two for theauxiliary power supply and another two for the second stage converter. Thesepower estimations are already conservative, so no additional reserve is added.
part [W ]gate driver, per transistor≈ 1.5control circuits 2fan 3total 13
Table 3.4: Estimation of power requirements
The output voltage is15V . The input voltage can range from105V up to450V .The minimal output voltage of the boost converter is≈ 280V after a full periodmains outage. This is enough to keep the control circuit working. The bootstrapsupply is not needed as long as the input voltage stays above193V . Below thisthreshold the control IC stops the converter. The input voltage has to be at least368V to start operation due to a hysteresis in the control chip.
19
3.2.2 Power Circuit Design
A two transistor flyback converter is chosen. It operates in continuous conductionmode to reduce the rms currents and transformer saturation. Peak current modecontrol is used to stabilise the output voltage. The power part of the circuit isshown in figure3.10. A larger drawing of this schematic can be found as figureC.3 in appendixC.
L200
EFD15-3F3-A100-S
GT2C203
10u
C202
10u
D204
50WQ10FN
T201
IRFR
C20
PBF
AUXVin
AUXGND
T200
IRFR
C20
PBF
D201US1M
D200
US1M
R205
0R
C204
22n
AUXVpp
1 3
2 4
T202
EP7-3F3
C201
220n
R200
15RD20218V
R2024k7
C200
220n
D203
SS16
R201
15R
R203
47R
IpsenseR204
3R3/W1
C205n.p.
R206n.p.
Figure 3.10: Power part of the auxiliary power supply
The input and output sides share a common ground because isolation is not re-quired.
The gatedriver is integrated in the sameUCC28513 controller IC as used for theboost converter and both converters are synchronised.
The high side switch is driven via a12 winding1 : 1 transformer with anEP7-3F3
core from Ferroxcube.
The flyback inductor consists of anEFD15-3F3-A100-S core from Ferroxcube.The primary winding has89 and the secondary23 turns. This results in a primaryinductance of634µH and a winding ration := N1
N2of 3.87. A 0.05mm2 wire for
the primary and a0.1mm2 wire for the secondary winding result in0.3W copperlosses. The core losses are calculated to be0.5W at250kHz.
3.3 Control
3.3.1 The Integrated PWM Controller
To reduce the costs and the number of required components an integrated circuitis used which provides two gate drivers with2A peak current capability. One gatedriver is for the boost MOSFET and the other for a second stage converter. In thisproject, the second gate driver is used for the auxiliary power supply.
TheUCC28513from Texas Instruments7 provides nearly all amplifiers and a multi-plier neccessary for PFC control. The voltage feed forward loop is integrated in this
7http://www.ti.com/
20
IC. It contains the neccessary PWM functions and over- / undervoltage protectionas well. External circuits are required to control the second gate driver.
The developer has to design the external components for proper biasing of thecircuit and the current and voltage controllers. Whereas the first part is well doc-umented in thedatasheet8, the control loop design is covered by the followingsections.
3.3.2 Boost Converter Control
Approach
As a model of the converter is already implemented in Simplorer, it is a good ideato simulate the controllers together with that model in Simplorer. Unfortunatelythis is nearly unfeasible because the handling of Simplorer gets really nasty withsimluation results consisting of more than1GB of data. The slow voltage con-troller with a crossover frequency of8Hz requires simulation durations of600ms.But at the same time the switching frequency of250kHz urges to use time steps of10−100ns. Thus the size of simulation output cannot be cut down to a manageableamount of data.
The solution was to implement another model of the converter in Simulink. Byusing an averaged switch model it is possible to simulate with much larger timesteps. This model is shown in figure3.14. The according Matlab script is listed inD.1.1.
1D
nKi(s)
den(s)
Ki * s
1s
100
0..1
2Iref
1 I
Figure 3.11: Simulink model of the current controllerKi
Figures3.11and3.12show the implementation details of the current and voltagecontrollers. The saturations and antiwindup loops are neccessary to get realisticbehaviour.
Probably the most difficult part to realise is the rectifier. The voltage at the boostinductor, which is coming from the input filter, is easily rectified with anabs()block. Another part of the rectifier is responsible that the current in the boostinductor does not become negative. This is solved by a saturation block and atype of an antiwindup feedback loop around the inductor itself. Furthermore thecurrent at the input of the rectifier is sometimes positive and sometimes negative.This is modeled as shown in figure3.13which is represented by the block labeled
8http://focus.ti.com/docs/prod/folders/print/ucc28513.html
21
1Vaout
7.5
Vref
nKv(s)
den(s)
Kv * s
1s
100*kv
kVo1
Vboost
Figure 3.12: Simulink model of the voltage controllerKv
1
out
.5
SignPulse: fmains0..1, D = 0.5
1in
Figure 3.13: Simulink model of the rectifier’s backward behaviour
Rect-Bwd in the converter model (fig3.14). It ensures that the current has thesame sign as the mains voltage. A better, more realistic solution would be to usethe sign of the voltage applied to theabs() block. Unfortunately Simulink does notseem to be able to simulate this.
The component numbers used in the following equations are defined in the schemat-ics included in appendixC.
Current Loop Design
An averaged switch model is taken for the converter. The input filter and boostinductor are combined into the impedanceZi:
Z1 :=
[1
sLN+
1R301 + 1
sC304
+ sC305
]−1
(3.13)
Z2 := sL303 +[
1R300
+1
sL302
]−1
(3.14)
Zi = R108 + sL100 +[sC306 +
1Z1 + Z2
]−1
(3.15)
22
Iac150 − 500uA
Vff1.4 − 4.7V(US − EU)
Uo
D’
green: mainsblack: input filterblue: boost dynamics
Iref
red: current control looporange: power + voltage control
7ILref
6Vff
5IL
4Io
3Vo
2Imains
1Vmains
1
multiplierproperty...
Umains
1
LN.s
ULN −> ILN: G1
1
L100.s+R108
ULB −> ILB: GB
1
C306.s
UC306 <− IC306: Z4
nG3(s)
dG3(s)
UC305,C306 −> IL303: G3
nZ2(s)
dZ2(s)
UC305 <− IC304,C305: Z2
|u| Rect−Fwd
inou
t
Rect−Bwd
R108
Mi
u2
Vbo
ost
Vao
ut
Kv
I
IrefD
Ki
nZo(s)
dZo(s)
Io −> Uo: Zo
nZff(s)
dZff(s)
Iac −−> Vff lowpass
−K−
Rm
1/Riac
1
Avg−SwitchGpwm
Avg−SwitchD’ * ILB = Io
|u| 0.5
2:1 I−mirror
km
0.8 − 1.2 [1/V]
Figure 3.14: Simulink model of the boost converter
23
The converter’s current transfer function is
Gi :=I
D′ =Uo,ref
Zi
∣∣∣∣Uo,ref=410V
(3.16)
The controller has the form
Ki =1
R403 · (C406 + C407) s· R411C406s + 1
C406C407R411C406+C407
s + 1
=ωi,I
s·
sωi,z
+ 1s
ωi,p+ 1
(3.17)
Carrying all this together gives the current loop transfer function
Li = Ki ·Gi ·R108 (3.18)
The crossover frequency of the current loopωi,co is desired to be5kHz. This ishigh enough to allow good control and low enough for damping of oscillationsin Zi to occur. The pole frequency is set as close to the crossover frequency aspossible. This is neccessary to keep the gain below0dB at frequencies wherethe resonance of the input part lays. A good tradeoff between phase margin anddamping isωi,p = 8kHz. The zeroωi,z is chosen to be at17Hz to maximise thephase margin over a wide frequency range.
Selecting values for the components gives results as shown in table3.5. A bodeplot of the resulting current loop transfer functionLi is shown in figure3.15.
R403 = 374 ΩR411 = 820 ΩC406 = 11 µF
C407 = 47 nF
ωi,I = 159 Hz
ωi,z = 17.6 Hz
ωi,p = 5000 Hz
ωi,co = 5306 Hz
Table 3.5: Parameters of the current controllerKi
Voltage Loop Design
The converter’s output filterZo is modeled as
RL =V 2
o
Po= 280Ω (3.19)
Co = (C101||C102) + (C103||C104) = 220µF (3.20)
Resr = 8mΩ measured (3.21)
Zo =
[1
RL+
1Resr + 1
sCo
](3.22)
24
Bode Diagram
Frequency (Hz)
Pha
se (d
eg)
Mag
nitu
de (d
B)
−150
−100
−50
0
50
100Gm = Inf, Pm = 38.102 deg (at 5518.9 Hz)
101
102
103
104
105
106
107
−180
−135
−90
−45
0
Figure 3.15: Bode plot of the current loop transfer functionLi
The linearisation of the multipliergmv is
Iff :=Uin,AP
R405 + R406 + R407
∣∣∣∣Uin,AP =110∗.8Vrms
(3.23)
gmv = Iff · [Iff ∗ 0.5 ∗ 0.9 ∗R420]−2 · 1
km
∣∣∣∣km=1 (0.8...1.2)
(3.24)
Thus the converter’s voltage transfer functionGv := VoD′ is
Ti =Gi
1 + Li(3.25)
Gv = gmv ·Rm · Ti · Zo |Rm=R403=374Ω (3.26)
The form of the voltage controllerKv is the same as for the current controller givenin equation3.17.
A low cross over frequency ofωv,co = 4Hz should provide enough damping at100Hz. To ensure a sufficient phase margin even at low loads, a low zero frequencyis required.ωv,z = 0.3Hz seems to be a good choice. The pole frequencyωv,p =34Hz is a tradeoff between an acceptable phase margin and optimised damping at
25
100Hz. Choosing common values for the components gives the values listed intable3.6. The resulting voltage loop transfer function has the form
ZVol :=[
1R418
+ sC416
]−1
(3.27)
MVo =ZVol
R422 + R423 + R428 + ZVol(3.28)
Lv = Kv ·Gv ·MVo (3.29)
The bode diagram ofLv at 600W output power is shown in figure3.16. Figure3.17shows a bode plot of the same transfer function at only10W output power.The problem is that the phase margin around0.1Hz becomes small at low loadsdue to a pole shift. This makes an extremely low zero frequencyωv,z neccessary.The power consumption of the auxiliary power supply makes controlled operationof the converter possible without any load at the output.
R422,423,428 = 536 kΩR412 = 47 kΩC409 = 10 uF
C408 = 100 nF
ωv,I = 0.03 Hz
ωv,z = 0.34 Hz
ωv,p = 34.2 Hz
ωv,co = 4.1 Hz
Table 3.6: Parameters of the voltage controllerKv
26
Bode Diagram
Frequency (Hz)
Pha
se (d
eg)
Mag
nitu
de (d
B)
10−1
100
101
102
103
104
105
106
107
−360
−270
−180
−90
0
−400
−300
−200
−100
0
100Gm = 67.185 dB (at 618.92 Hz), Pm = 110.62 deg (at 4.1017 Hz)
System: Lv Frequency (Hz): 96.4
Magnitude (dB): −35.5
Figure 3.16: Bode plot of the voltage loop transfer functionLv at600W
3.3.3 Flyback Converter Control
Peak Current Mode Control
The UCC28513 does neither provide control amplifiers nor a blanking circuit forthe second stage gate driver. An external blanking circuit and two external ampli-fiers are required, one for the voltage controller (U400A) and the other to amplifythe sensed current (U400B).
In peak current mode control, the voltage controller provides a reference for thepeak current in the inductor. The gate driver switches the transistors in regularintervals on and it switches them off when the reference current is reached. Ablanking circuit is required to hide the current spike, originating from parasitictransistor capacitances, from the control circuit. The blanking circuit consists ofthe componentsR416, 417 , R421, C413, T400 andC414.
It was discovered that this blanking circuit and the operation amplifierU400B, usedto amplify the measured current signal, introduce a lot of distortions. To get thecontroller working it was neccessary to exchange the1.5Ω resistorR204 by 3.3Ωand to go from there without amplifier to the input of theUCC28513. The lowpassbuilt with R416 andC415 allows to ommit the blanking circuit.
27
Bode Diagram
Frequency (Hz)
Pha
se (d
eg)
Mag
nitu
de (d
B)
−400
−300
−200
−100
0
100Gm = 66.568 dB (at 597.14 Hz), Pm = 78.448 deg (at 4.8288 Hz)
System: Lv Frequency (Hz): 97.9
Magnitude (dB): −35.7
10−2
100
102
104
106
−360
−315
−270
−225
−180
−135
−90
System: Lv Frequency (Hz): 0.115 Phase (deg): −141
Figure 3.17: Bode plot of the voltage loop transfer functionLv at10W
Converter Transfer Function
Peak current mode control has the advantage that the dynamics of the flyback in-ductor do not make their way into the converter’s voltage loop transfer function.The inductor becomes a current source and the transfer function consists mainly ofthe output filter.
Co = C400 + C401 + C403 + C202 + C203 + C204 (3.30)
Resr ≈ 1.2mΩ (3.31)
Gfv =Vfo
I1
= nRL ·ResrCos + 1RLCos + 1
∣∣∣∣n=3.87
(3.32)
Controller Transfer Function
Together with the voltage controller
Kfv =1
R413 (C404 + C405)· C404R408s + 1
C404C405R408C404+C405
s + 1(3.33)
28
the open loop voltage transfer function of the auxiliary flyback converter becomes
Lfv = KfvGfv1
R204(3.34)
A bode plot ofLfv at multiple output power levels is shown in figure3.18.
R413 = 10 kΩR408 = 11 kΩC404 = 220 nF
C405 = 220 pF
ωfv,I = 72 Hz
ωfv,z = 66 Hz
ωfv,p = 66 kHz
ωfv,co = 13 kHz
Table 3.7: Parameters of the AUX-Flyback’s voltage controllerKv
Frequency (rad/sec)
Pha
se (d
eg)
Mag
nitu
de (d
B)
−100
−50
0
50
100
1W3W7.5W10W13W
101
102
103
104
105
106
107
−270
−225
−180
−135
−90
−45
Figure 3.18: Bode plot of the AUX-Flyback’s voltage loop transfer functionLfv
29
Construction and Testing
4.1 Board Layout
4.1.1 Arrangement
The top side of the board is shown in figure4.1. It contains all through hole contactdevices. The bottom side contains mostly components of the control circuit and afew of the auxiliary flyback.
The 3rd layer (figC.10), except the region of the input filter, consists of aGND
plane.
Figure 4.1: Top view of the board (120× 84mm) with dyed functional regions
The input filter lies in the bright green region. It is placed close to the input con-nector and fuse. This area contains a grounded plane1, located on the 3rd layer(fig C.10), which helps reducing common mode noise. The dense arrangement ofthe components needs to be checked according to safety regulations.
The red area indicates where the boost MOSFET, the boost diode and the inputbridge rectifier are mounted. All semiconductor components are covered by the6 × 6 cm heat sink with fan. The input rectifier is located on the left side of theheatsink, the boost MOSFET slightly right of the center and the boost diode is inthe top right edge. The pins of the boost MOSFET,T101 , and those of the boostdiode,D112, are as close together as possible to reduce parasitic inductances. TwoSMD 10nF ceramic capacitors,C105 andC106, reduce the problem of parasiticinductances to the terminals of the output electrolytic capacitors.
The blue region contains the output filter and the boost inductance. The 2nd layer
1This plane is not connected to theGNDplane. Please distinguish betweenGNDand ground (PE,protective earth).
30
(fig C.9), underneath the capacitors, contains a plane connected to the positiveoutput voltage. This provides a further high frequency capacitance in connectionwith theGNDplane. The interconnections are optimised so that the areas enclosedby switched currents are as small as possible.
The yellow area covers the auxiliary power supply. Its layout is optimised for lowspace consumption rather than for electrical functionality as there are only smallcurrents flowing. It is placed far away from the gate driver. This is neccessary be-cause the only gate driver IC is placed near the boost MOSFET and the placementof the auxiliary power supply has low precedence, since decoupling capacitors areused.
The control and monitoring circuit is split into three parts. A high voltage part,consisting mainly of voltage dividers, is located on the top side, in the bottom rightcorner of the heatsink. It is the bootstrap supply, the output voltage sensing dividerand theIac voltage feed forward input.The second part, theUCC28513controller,U401, and its related components, is onthe opposite side of the high voltage part. This keeps wiring short and is next tothe boost MOSFET.The third part is built of theLM324, U400, and its circuitry. It provides outputvoltage monitoring functions for the boost converter and a voltage controller forthe auxiliary power supply. The current amplification and blanking circuit has tobe bypassed as described in section3.3.3and figureC.5.All these parts have aVcc plane on the 2nd layer (figC.9) which is connected tothe positive supply of the ICs to build a capacitor with theGNDplane. Furthermore,each IC has a1uF capacitor across its supply voltage right next to it. This isespecially important for the gate driver IC with its2A peak current capability andsensitive control functions.
4.1.2 Volume Efficiency
The boxed converter’s dimensions are120mm× 84mm× 37mm = 372.96cm3.With a nominal output power of660W this makes for1.77 kW
dm3 .
To calculate the volumetric density of the subsystems, each of them is fit into arectangular bounding box. The height of that box is defined by the highest compo-nent it contains. Only the output filter is approximated by two such boxes due toits L shaped layout. Table4.1 lists the resulting numbers. The subsystems fill only85% of the converter’s bounding box because not all boxes are of equal height.
in-fltr power out-fltr aux-supp total
cm3 48.1 133.2 109.5 24.8 315.6% 13 36 29 7 85
Table 4.1: Volume efficiency of subsystems
31
4.2 Input Filter
The input filter is first mounted onto the board to make some measurements ofthe expected filter performance and input/output impedances. Figure4.2 shows apicture of the whole filter including its dimensions.
Figure 4.2: Picture with dimensions of input filter
The measurements are performed in a standard50Ω measurement setup utilisinga HP4195A network analyser. The insertion loss curves for the DM and CM filterare found in figure4.3.
0.1 1 10 100
-100
-80
-60
-40
-20
0
Frequency [MHz]
Atte
nuat
ion
[dB
]
DM
CM
Figure 4.3: Frequency-dependent attenuation
The measured attenuations are smaller than the aspired ones calculated in section3.1.4. The reason for this difference is that the calculations are performed with theaid of a LISN, which supports additional filter components. The final measure-ments are done in a50Ω measurement setup without any additional filter compo-nents. But when regarding the filter on the fully mounted board, its environmentcontributes to the damping performance and the needed values should be reached2.
2No tests were made on the fully mounted board.
32
4.3 Flyback Testing
The auxiliary power supply and all control components are mounted after the inputfilter is tested. The output filter is mounted also. To test the flyback converter atnominal voltages, the output voltage of the flyback converter is charged to about12V by an external supply. This drives the control circuit into an operational state.A diode prevents currents flowing back into the external power supply once theflyback converter pulls its output voltage to15V . Charging the boost converter’soutput capacitors to410V starts operation of the flyback converter. Once it started,the input voltage can vary between200 and450 + V . At that stage, the currentfrom the external12V power supply stops. The flyback converter operates in au-tonomous mode. With low load, the control loop is not stable. This results in a highvoltage ripple at the converter’s output and accoustic noise. Connecting a load, forexample the fan, brings the converter into a stable operating point. The accousticnoise is not noticeable any more.
This is the stage of the project where it became clear that the designed blankingcircuit does not work and has to be circumvented as described in section3.3.3.
4.4 Boost Converter Testing
4.4.1 Low Voltage Testing
The converter is modified to avoid snap throughs destroying the control circuit.The following modifications are made:
• R405 andR406 are short circuited.R407 is replaced by91kΩ. This is thecorrect multiplier bias circuit for input voltages from14V to 45.5V , DC orsine amplitude.
• R422 andR423 are short circuited. The remaining divider,R428 andR418,makes for49.5V at the converter’s output.
A load resistor of136Ω dissipates18W , enough for a stable voltage control loop.The input current is not sinusoidal at such low voltages due to the boost inductordynamics. But these conditions are sufficient to test the control circuit.
DC and AC tests in this voltage range were both successful. The problems discov-ered during these tests made it impossible to operate the converter at its nominalconditions.
33
4.4.2 Discovered Problems and Future Investigations
Critical Problems
The still unsolved problems discovered at this stage of the project are described insection1.4. Here is a short summary of them:
• too narrow clearances in the layout→ certification issue, technically noproblem
• ≈ 100% output voltage overshoot at startup→ might require slow start
• bootstrap supply not sufficient→ redesign or use another controller
These are the most important points to be addressed in the future.
Solved Issues
The tests revealed control loops with too low phase margins at low loads. Theseare corrected by placing the controller’s zero at a lower frequency. The revisedcontrol loops require large capacitances of about10µF at 15V . It is possible touse tantalum capacitors, butmuRata3 has non polarised, ceramic chip capacitorswith the required capacity and a1206 or 1210 footprint (e.g. Distrelec83 01
34). Section3.3contains the revised control loop data.
Optional Improvements
The auxiliary power supply uses two MOSFETs which are completely overrated.This makes it possible to use them without heatsink. Future loss measurementsmight reveal that it is possible to use devices with a smaller footprint.
The series resistors of the boost MOSFET,T101 , are chosen very conservative.This mainly because switching noise is a major problem on the test board con-sisting of only two layers. The gatedriver IC can deliver peak currents of2A andcontinuous currents of400mA. The2A are reached whenR102 andD108 are notplaced andR104 is chosen to be4.7Ω. This should reduce switching losses. Alower value than4.7Ω for R104 is not recommended.
3http://www.murata.com/cap/index.html
34
Appendix A
Loss Calculation Formulas
A.1 Loss Calculations including Current Ripple
A.1.1 The Hard Way
The first approach is to calculate the rms and average currents by taking the currentripple into account. Using Mathematica this seems to be possible. Problems arisewhen trying to calculate the average power losses over half a mains period. Thepower losses in function of time have to be approximated by aP ·sin2(ωt) functionin order to reduce the computation time.
This is tried for the two-stage and the SEPIC converter. As this approach is com-plex and the results are not really better due to uncertainties of parasitic parameters,the flyback converter is left out. As an example, the equations for the two-stageconverter are given in the next section. The computations for the SEPIC converterare done accordingly.
A.1.2 Two-Stage Converter
See figure2.1for the component enumeration used in this section.
Definition of Contstraints
The constraints used are those already specified in table2.1. The following con-stants are newly defined:
Vmax,EU :=230 · 1.2 Vrms maximum rms input voltage
Vmin,US :=110 · 0.8 Vrms minimum rms input voltage
i1,peak :=√
2PoVmax,EU
peak input current
(A.1)
Additionally the intermediate voltage2vz, the output of the boost converter, mustbe 5% above the maximum peak input voltage in order to provide an adequatedynamic margin to control the circuit:
√2 · Vmax,EU · 1.2 · 1.05 ≈ 409.8V (A.2)
=⇒ 2 · vz := 410V (A.3)
Another constraint is that the maximum current ripple in the boost inductor must besmaller than20% of the peak input current. This seems to be a good compromisebetween the inductor size and the current ripple in the output capacitor. The worstcase current ripple occurs whenD = 0.5.
35
1 2 3 4 5 6
A
B
C
D
654321
D
C
B
A
Title
Number RevisionSize
B
Date: 2-Jun-2005 Sheet of File: N:\protel\pfc.ddb Drawn By:
Cgd
Cgs
Rg
Vggm*Vgs
1 2 3 4 5 6
A
B
C
D
654321
D
C
B
A
Title
Number RevisionSize
B
Date: 1-Jun-2005 Sheet of File: N:\protel\pfc.ddb Drawn By:
CgdRg
Vg Rds(on)
Figure A.1: Replacement model for the boost MOSFET
Idealisations
For the design of the boost inductor and capacitor it is possible to assume idealswitching behaviour. Thus the boost diode is replaced by an ideal diode, the tran-sistor is assumed to be an ideal switch and all parts operate lossless.
It is assumed that the input voltage stays constant during a converter switching in-terval. In other words, the switching frequency must be some orders of magnitudehigher than the mains frequency.
The intermediate voltage buffer capacitance is assumed to be infinite. This gives aconstant intermediate voltagevz.
For semiconductor loss calculations a more detailed model is required. The switch-ing boost MOSFET is modeled (figA.1) as either a voltage controlled currentsource with gate-drain and gate-source capacitors or as a resistor, depending onthe actual state.
The boost diode is replaced by a resistor and an offset voltage in its on state. Thereverse recovery current is neglected because a SiC diode is used which has a small,practically constant reverse recovery charge of typically13− 20nC.
Calculation of L1
First it is neccessary to calculate the minimal value of the boost inductance. Thecondition to be fulfilled is
∆i1,pp ≤ 0.2 · i1,peak (A.4)
Considering equationsA.5 to A.7
v1(t) :=√
2 · Vmax,EU · sin (ωN t) (A.5)
d(t) := 1− v1(t)2vz
(A.6)
v1(t)!= L1 ·
∆I
∆t(A.7)
36
and replacing∆t with d · Ts leads to equationA.8.
L1 ·∆I√2 · Vmax,EU · Ts
= sin (ωN t)−√
2 · Vmax,EU
2vz· sin2 (ωN t) (A.8)
The right hand side of equationA.8 is plotted in figureA.2. A maximum value of0.2626 is found and used in order to find the correct value of the boost inductance.
L1 =0.2626 ·
√2 · Vmax,EU
∆i1,pp · fs= 187µH (A.9)
0.5 1 1.5 2 2.5 3
0.05
0.1
0.15
0.2
0.25
Figure A.2: Right hand side of eq.A.8
The maximum EU values are used as worst case scenario for the calculation ofL1.To obtain the worst case rms currents, the minimum US values are used.
Loss Calculations for the boost MOSFET
The used MOSFET is an Infineon CoolMOSSPP20N60C3(VDS = 650V , ID =20.7A). As shown later, the calculated switching and on-state losses at worst casecurrents and voltages are about equal for this device. Thus the use of an overrateddevice minimises overall losses.
The local rms current through the transistor,iT1,rms,loc(t), is obtained by applyingequationsA.5, A.6 andA.10 - A.12.
i1,glob =√
2 · Po
Vmin,US(A.10)
iT1,on(t) =
i1,glob · sin
(2πTN
t)− 1
2∆i1,pp(t) 0 ≤ t ≤ d(t) · TN
0 else(A.11)
iT1,rms,loc(t) =
√1Ts
∫ d(t)Ts
0
(iT1,on(t) +
∆i1,pp(t)Ts
· τ)2
dτ (A.12)
which evaluates to6.57A when minimum US values are used.
37
Evaluating1 formulaA.12 at t = TN4 for US values results in a current of9A. The
global rms value is obtained from
iT1,rms =
√2
TN
∫ TN2
0(iT1,rms,loc(t))
2 dt (A.13)
iT1,rms|V1=Vmin,US= 6.57A (A.14)
To calculate the switching losses of the boost switch, the timest0 throught5 arechosen as depicted in figureA.3. They are non-linearised R-C charging times. Thevoltages of the gate driver are defined to beVg and0V . Remember that the timeargumentt of the functionst0 . . . t5 is assumed to be constant during the respectivetime interval. It is related to half a mains period.
VGS(th)
0t0 t2t1
vp
Vg
vGS(t)
tt3 t4 t5
iD(t)
vDS(t)
Vd
I0
Figure A.3: Nomenclature of time intervals during switching
vp(t) =iT1,on(t)
gfs+ VGS(th) (A.15)
τ = (Rg + Rgv) (Cgd + Cgs) (A.16)
t0 = − ln(
1−VGS(th)
Vg
)· τ (A.17)
t1(t) = − ln(
1− vp(t)Vg
)· τ − t0 (A.18)
Vg − vp(t)Rg + Rgv
=Cgd · 2vz
t2⇒ t2(t) =
Rg + Rgv
Vg − vp(t)· 2vzCgd (A.19)
t3(t) = − lnvp(t)Vg
· τ (A.20)
1Mathematica was used for that purpose
38
vp(t)Rg + Rgv
=Cgd · 2vz
t4⇒ t4(t) =
Rg + Rgv
vp(t)· 2vzCgd (A.21)
t5(t) = − ln(
VGS(th)
Vg
)· τ − t3(t) (A.22)
The computed switching times are listed in tableA.1.
intv. US EU
t0 2.97 2.97 ns
t1 0.49 0.15 ns
t2 9.82 9.57 ns
t3 19.60 20.80 ns
t4 33.06 36.18 ns
t5 1.80 0.60 ns
Table A.1: Switching times of boost switch
By using these values it is now possible to calculate the dissipated energy perswitching period and finally the power losses.
iT1,off (t) = iT1,on(t) + ∆i1,pp(t) (A.23)
Eon(t) =12· 2vz · iT1,on(t) · (t1(t) + t2(t)) (A.24)
Eoff (t) =12· 2vz · iT1,off (t) · (t4(t) + t5(t)) (A.25)
PT1,switch(t) =1Ts
(Eon(t) + Eoff (t)) +1Ts· Cds · (2vz)2 (A.26)
The on-state losses are calculated using the following equation.
PT1,on(t) = i2T1,rms,loc(t) ·Rds,on (A.27)
The total power dissipation in the boost MOSFET is found by summing the switch-ing losses and the on-state losses. The losses found are peak losses. AP · sin2(ωt)approximation gives a guess for average losses:
PT1,tot(t) = PT1,switch (t) + PT1,on (t) +1
2TsCds (2vz)
2 (A.28)
PT1,avg =2
TN
∫ TN2
0PT1,tot
(TN
4
)· sin2
(2π
TNt
)dt
∣∣∣∣∣Vmin,Pmax
(A.29)
39
PT1,switch Pon PCdsPT1,avg
Vmin,US 25.7 24.3 1.7 25.8 W
Vmax,EU 0.2 8.4 1.7 W
Table A.2: Power losses in the boost switch
Losses in the boost SiC diode
An Infineon SiC shottky diodeSDT08S60 (VRRM = 600V , IF = 8A) is used.Their main advantage is the very low and more or less constant reverse recoverycharge resulting in minimised overall switching losses.
The current ripple is the same as in the boost inductor:
∆iDF ,pp (t) =v1 (t)L1
d (t) Ts (A.30)
The current in the diode, right before the boost transistor is switched on, is thus
iDF ,off (t) = i1,glob · sin(
2π
TNt
)− 1
2∆iDF ,pp (t) (A.31)
The current in the diode while it is conducting is (ramp reversed):
iDF(t, τ) = iDF ,off (t) +
∆iDF ,pp
(1− d (t))Ts· τ∣∣∣∣
t ∈h0,
TN2
i, τ ∈ [0,4µs]
(A.32)
It follows the local rms current in the diode.
iDF ,rms,loc (t) =
√1Ts
∫ (1−d(t))Ts
0iDF
(t, τ)2 dτ (A.33)
The global rms current, relating to half a mains period, in the diode is obtainedfrom
iDF ,rms =
√2
TN
∫ TN2
0iDF ,rms,loc (t)2 dt
∣∣∣∣∣∣Vmin,US
≈ 9.1A (A.34)
The losses in the diode are derived from equationA.32. The differential resistanceof the diode is83mΩ, the forward voltage at0A is 1.9V . First the local losses,limited to one switching cycle, are calculated.
PDF ,loc (t) =1Ts
∫ (1−d(t))Ts
0iDF
(t, τ)2 dτ (A.35)
Averaging over half a mains period gives the total diode losses:
PDF ,avg =2
TN
∫ TN2
0PDF ,loc (t) dt
∣∣∣∣∣Vmin,US
≈ 4.4W (A.36)
40
Efficiency of the Boost Converter
Losses of25.8W in T1 and4.4W in DFyield an efficiency of95% at an input volt-age of110 · 0.8Vrms and600W output power. Replacing real, measured switchinglosses would give a more precise result. But a testing circuit was not available atthat stage of the project.
DC-DC Stage Transistors
The DC-DC nature of the second stage make the calculations a lot easier. ForT2
andT3, SPP07N60C3 (VDS = 650V , ID = 7.3A) from the Infineon CoolMOSseries are taken. The switching times are calculated the same way as those forthe boost transistor in equationsA.15 to A.22. With the current in the primarytransformer winding
ip =Po
2vzD2D2 =
nVo
2vz(A.37)
the switching losses are
PT3,switch =1Ts· 12vzip (t31 + t32 + t34 + t35) ≈ 2.1W (A.38)
The on-state losses of11.4W are a lot higher than the switching losses. Thus itcould be possible to further reduce the losses by choosing a device that balancesthe switching and on-state losses. That means to take a transistor with a lowercurrent rating.
DC-DC Stage Rectifier Diodes
For loss evaluation purposes shottky diodes with a differential resistance ofRdiff =13mΩ and a forward voltage ofVf = 0.7V are taken forDr . The losses in one ofthe four diodes are
PDr = D2
(Po
VoVf +
(Po
Vo
)2
Rdiff
)
+(1− 2D2)
(Po
2VoVf +
(Po
2Vo
)2
Rdiff
)(A.39)
≈ 5.8W
The conduction losses in the whole rectifier are thus
Prect = 4PDr ≈ 23.3W (A.40)
Calculated Overall Losses
The losses in tableA.3 lead to an efficiency of87% for the whole two-stage con-verter at worst case conditions. This calculation does not include the auxiliarypower supply.
41
T1 DF T2, T3 Dr total [W ]25.8 4.1 2 · 13.5 4 · 5.8 80
Table A.3: Calculated worst case losses for the two-stage converter
A.2 Calculations neglecting Current Ripple
The following sections illustrate how the formulas in the tables2.2, 2.3, 2.4 and2.5are derived.
RMS currents are identified by a star,I∗, and average current symbols are over-lined, I.
A.2.1 Two-Stage Converter
The according schematic can be found in figure2.1.
P1!= Po =
I1√2· Vmin,US ⇒ I1 =
√2P1
V1,rms
∣∣∣∣∣V1,rms=Vmin,US
(A.41)
M :=Vo
V1
⇒ d(ϕ) = 1− sin(ϕ)M
∣∣∣∣ϕ ∈ [0,π]
(A.42)
The input rectifier diodesD1 - D4:
ID1 =I1
2π·∫ π
0sin(ϕ) dϕ =
I1
2π· 2 (A.43)
I∗D1=
[12π
∫ π
0I21 sin2(ϕ)dϕ
] 12
(A.44)
The boost diodeDF:
IDF(ϕ) = (1− d(ϕ)) · I1 sin(ϕ)
=sin(ϕ)
M· I1 sin(ϕ)
IDF=
1π
∫ π
0IDF
(ϕ)dϕ (A.45)
I∗DF=
[1π
∫ π
0
[I1 sin(ϕ)
]2· sin(ϕ)
Mdϕ
] 12
(A.46)
42
The boost transistorT1:
IT1 =1π
∫ π
0I1 sin(ϕ)d(ϕ)dϕ
=I1
π
∫ π
0sin(ϕ)
(1− sin(ϕ)
M
)dϕ (A.47)
I∗T1=
[1π
∫ π
0
(I1 sin(ϕ)
)2(
1− sin(ϕ)M
)dϕ
] 12
(A.48)
The currents inL1 are trivial as they are assumed to be perfectly sinusoidal.
IL1 =I1
π(A.49)
I∗L1=
I1
2(A.50)
The boost output capacitorCo:
I∗Co=
[1π
∫ π
0
[(I1 sin(ϕ)− Iout
)2 sin(ϕ)M
+ I2out
(1− sin(ϕ)
M
)]dϕ
] 12
∣∣∣∣∣Iout=
I12M
(A.51)
For the second stage DC-DC converter some new symbols are used. The dutycycle D is defined to be the duty cycle of one of the two transistors. Thus thetransformer’s primary winding sees the voltagevz for 2DTs per switching interval.Ip is the current in the transformer’s primary winding. Magnetisation currents areneglected.Io andVo are at the converter’s output.
2Dvz = nVo ⇒ D =nVo
2vz(A.52)
2DIpvz = Po ⇒ Ip =Po
2Dvz(A.53)
Iz =Po
2vz(A.54)
Substituting these equations into the following expressions for average and rmscurrents gives the expressions in table2.3.
The intermediate capacitorsC1 andC2:
I∗C1=
[1Ts
∫ DTs
0(Ip − Iz)
2 dt
] 12
=√
D (Ip − Iz) (A.55)
43
The transformer’s primary windingLp:
ILp = 0 (A.56)
I∗Lp= 2I∗C1
(A.57)
The transistorsT2 andT3:
IT3 = DIp (A.58)
I∗T3=
√1Ts
TsDI2p (A.59)
The output rectifier diodesDr :
IDr = DIo +12(1− 2D)Io (A.60)
I∗Dr=
√DI2
o + (1− 2D)(
Io
2
)2
(A.61)
A.2.2 SEPIC Converter
The schematic for this circuit is in figure2.2.
M :=Vo
V1
⇒ d(ϕ) =M
sin(ϕ) + M(A.62)
The input rectifier carries the same currents as with the boost converter. EquationsA.43 andA.44 yield these currents.
The currents in the input inuductorL1 are the same as those in equationsA.49 andA.50 for the boost converter’s input inductor.
The inductorL2:
d(ϕ)IL2(ϕ) != (1− d(ϕ)) IL1(ϕ) ⇒ IL2(ϕ) =sin(ϕ)
MIL1(ϕ)
IL2 =1π
∫ π
0
sin(ϕ)M
· I1 sin(ϕ) dϕ (A.63)
I∗L2=
[1π
∫ π
0
sin(ϕ)M
· I21 sin2(ϕ) dϕ
] 12
(A.64)
44
The transistorT1:
IT1 =1π
∫ π
0d(ϕ) (IL1(ϕ) + IL2(ϕ)) dϕ
=1π
∫ π
0
M
sin(ϕ) + M
(I1 sin(ϕ)
(1 +
sin(ϕ)M
))dϕ (A.65)
I∗T1=
[1π
∫ π
0d(ϕ) (IL1(ϕ) + IL2(ϕ))2 dϕ
] 12
=
[1π
∫ π
0
M
sin(ϕ) + M
(I1 sin(ϕ)
(1 +
sin(ϕ)M
))2
dϕ
] 12
(A.66)
The intermediate capacitorC1:
I∗C1=
[1π
∫ π
0(1− d(ϕ)) I1(ϕ)2 + d(ϕ)IL2(ϕ)2 dϕ
] 12
=[
1π
∫ π
0
(sin3(ϕ)
sin(ϕ) + M+
M sin2(ϕ)sin(ϕ) + M
)I21 dϕ
] 12
(A.67)
The free wheeling diodeDF:
IDF=
1π
∫ π
0(1− d(ϕ)) (IL1(ϕ) + IL2(ϕ)) dϕ
=1π
∫ π
0
sin(ϕ)sin(ϕ) + M
(I1 sin(ϕ) +
sin2(ϕ)M
I1
)dϕ (A.68)
I∗DF=
[1π
∫ π
0(1− d(ϕ)) (IL1(ϕ) + IL2(ϕ))2 dϕ
] 12
(A.69)
The output capacitorC2:
I∗C2=
[1π
∫ π
0(1− d(ϕ)) (I1(ϕ) + IL2(ϕ)− Io)
2
+ d(ϕ)I2o d(ϕ)
] 12 (A.70)
A.2.3 Flyback Converter
The component names are taken from figure2.3. D1 is the duty cycle ofT1 andthus the magnetisation time forLp. D2 is the demagnetisation time forLs . Re-member that there arem = 3 parallel output stages realized with3 secondarywindings on the flyback inductor.
See equations2.7 for Ia, Ir, Ia2 andIr2, the local average and rms input currentson primary and secondary side.
45
D1 is developed via the power consumption at the converter’s input:ip(ϕ) is thepeak current in the primary inductor right beforeT1 is switched off.
12Ts
Lpip(ϕ)2 != P1(ϕ) (A.71)
Po!=
1π
∫ π
0P1 sin2(ϕ) dϕ (A.72)
=⇒ P1 = 2Po P1(ϕ) = P1 sin2(ϕ) (A.73)
The peak inductor current is related to the average input current by
ip(ϕ) = Ia sin(ϕ)2
D1(A.74)
Substituting equationsA.73andA.74 into equationA.71gives a constantD1, evenunder PFC conditions.
12Ts
Lp
(Ia sin(ϕ)
2D1
)2!= 2Po sin2(ϕ)
=⇒ D1 =2V1
·√
LpPo
Ts∀ ϕ (A.75)
The inductor winding ration := Np
Ns= 3 is constrained by equationsA.76 and
A.77. The first is required due to the limited transistor blocking voltage ofVT,max =600V . It makes forn. The latter is the condition for discontinuous mode of opera-tion. The maximum forLp is calculated (eq.A.78) with its result.
VT,max = V1 + nVo =⇒ n ≤VT,max − V1
Vo(A.76)
n ≥ V1
Vo· D1
1−D1⇐⇒ D1 ≤
Von
V1 + Von=: Dmax (A.77)
Lp ≤Ts
Po· D2
maxV 21
4= 1.87µH (A.78)
Inductor property:
Ls = Lpm
n2(A.79)
The currents inLp andT1 are the same:
IT1 =1π
∫ π
0Ia sin(ϕ) dϕ (A.80)
I∗T1=
[1π
∫ π
0
(Ia sin(ϕ)
)2dϕ
] 12
(A.81)
46
The currents in the input rectifier diodesDi (not in schematic) are half of the cur-rents inLp andT1:
ID1 =1π
Ia (A.82)
I∗D1=
√2
4Ir (A.83)
The output diodeDF (per output stage):
IDF=
1π
∫ π
0Ia2(ϕ) dϕ
=1π
∫ π
oIa2 sin2(ϕ) dϕ (A.84)
I∗DF=
[1π
∫ π
o
(Ir2
√sin3(ϕ)
)2
dϕ
] 12
(A.85)
For the output capacitorCo (per output stage) the local rms current is first cal-culated.D2 is constant during one switching cycle, anything else does not makemuch sense.
I∗Co,loc(ϕ) =
[1Ts
(∫ D2(ϕ)Ts
0
(Vo
mn2 Lp
t− Io
)2
dt
+ I2o (1−D2(ϕ))Ts
)] 12 (A.86)
I∗Co=
[1π
∫ π
0I∗Co,loc(ϕ)2dϕ
] 12
(A.87)
47
A.3 Two-Stage Converter Loss Simulations usingSimplorer
For the simulation of the losses the converter is split up into two parts, so the firstand the second stage can be simulated independently.
Because the transistors used for the analytical calculations are not available as Sim-plorer models they are replaced by the similarIRFBC40LC. This transistor has aslightly biggerRdson value than the CoolMOS series from Infineon used in theprototype.
Losses in the input rectifier are neglected as they are common for all evaluatedtopologies.
All simulated rms values correspond to the whole simulation interval of half amains period at60Hz. The local rms values use a sliding integration interval ofthe previous32µs which is equal to8 switching cycles.
FigureA.4 shows the schematic used for the simulation of the losses in the firststage. The boost diode is a SiC schottky diode which minimises switching lossesand allows a large reverse voltage. The load of the second stage is modeled bya current source drawing constantly600W of power. This neglects the additionalpower needed to feed the losses of the second stage.
FiguresA.5 and A.6 show the simulation results of the second stage. The firstsimulation uses the nominalvz = 205V for input and the second a worst casevoltage2 of vz = 107V . The transistors are controlled by two PWM modulesgenerating exactly the same waveforms but with a relative phase shift of180. Theduty cycle is constant which results in a drop of the output voltage relating to thelosses in the second stage.
2During the design of the control circuit the worst case output voltage of the boost converter hasbeen redefined to be at least193V . The control circuit stops working below this voltage. This is aninternal limitation in theUCC28513.
48
Figure A.4: Loss simulation for the first stage of the two-stage converter
49
Figure A.5: Loss simulation for the second stage, normal operation
50
Figure A.6: Loss simulation for the second stage, worst casevz = 107V
51
Appendix B
Losses Measurement Circuit Schematics
These are the schematics of the circuit used to measure the switching losses in theboost MOSFET and diode. This circuit contains also a prototype of the auxiliarypower supply (figC.3) including its control circuit.
T900
SPP2
0N60
C3
L900
187u
D900
SDT08S60
1
2
JP900
CON2
C900 1u
M900
IT1
GT2AUXVin AUXVpp
AUXGNDIpsense
AUX-PWRauxsupp.sch
GT1GT2
AUXVppGND
Isense2 !EN
testctrltestctrl.sch
R900
10m/1.5W
Figure B.1: Power part of the loss measurement circuit
52
1 2
X95
0C
ON
2
GT1
R95
4
6R8
R95
3
10R
VA
OU
T1
RT
2
VSE
NSE
3
D_M
AX
4
CT_
BU
FF5
GN
D6
VER
R7
ISEN
SE2
8
VC
C9
GT2
10PW
RG
ND
11
GT1
12
SS2
13
PKLM
T14
CAO
UT
15
ISEN
SE1
16
MO
UT
17
IAC
18
VFF
19
VR
EF20
U95
1U
CC
2851
3
GN
D
GN
D
R95
91M
GN
D R96
418
kC
950
1u
GN
D
D95
018
V
R96
0
100k
GN
D
C95
11u
R96
23k
6
R95
5
50k
R96
110
0kR
972
22k
GN
D
T950
2N70
02
C95
410
u
D95
1
BA
V70
GT2
+15V
Gat
eDriv
er P
ower
Sup
ply
R96
910
0k
R95
268
k
R95
0n.
p.0V
to e
nabl
e G
T1 a
nd d
isab
le G
T215
V to
dis
able
GT1
and
ena
ble
GT2
AU
XV
pp
R95
712
k
R95
812
k
GN
D
GN
D
12 3
U95
0A
TL08
4CDC
953 220pC
952 2n2
R95
6
11k
+V
V-
GN
DR
951
n.p.
765
U95
0BTL
084C
D
R96
6
10k
R96
5
11k
GN
DIsen
se2
R96
710
k
!EN
R97
711
k
R96
310
0R
C95
6
1n2
C95
7
1n2
C95
81n
2
C?
68p
C?
330p
R?
10k
R?
330R
T?
2N70
02
Figure B.2: Control and gate driver of the loss measurement circuit
53
Appendix C
Prototype Schematics and Layout
The component naming scheme uses numbers as defined in tableC.1.
0 - 99 converter.sch converter overview100 - 199 power.sch power part200 - 299 auxsupp.sch auxiliary power supply300 - 399 inputfilter.sch input filter400 - 499 control.sch control circuit
Table C.1: Component numbering scheme
LinNin
Vboost
T1g IsenseVgroundVcenter
power power.sch
GT2
AUXVinAUXGND
AUXVppIpsense
auxsupp auxsupp.sch
PGND
VLsenseIsense
GT1Vboost
SGNDauxVppIsense2
GT2
control control.sch
Lin LoutNin NoutEarth
inputfilter
inputfilter.sch
F1
10A T
X3
X4
1
2
3
X1
POENIX3
1 2 3
X2CON3
Figure C.1: Converter overview
54
Lin
Nin
Vbo
ost
T1g
Isen
se
T101
SPP20N60C3
L100
187u
D11
2
SDT0
8S60
C10
222
0u
C10
422
0u
Vce
nter
C10
122
0u
C10
322
0u
R10
8
R01
0
D10
7TI
C12
6M
D10
6TI
C12
6M
D10
9
10ET
S08
D11
0
10ET
S08
Vgr
ound
R10
3
B59
884C
120A
70
D10
4S1
MD
105
S1M
D11
1U
S1M
R10
2
6R8
R10
4
10R
GT1
singl
e ga
te re
sisto
r: m
in 4
R7
R11
018
0k
R11
218
0k
R11
118
0k
R10
918
0k
D11
3 18V
R10
7
10k
R10
1SI
OV
-07
R10
0SI
OV
-07
D10
110
BQ
060
D10
210
BQ
060
D10
310
BQ
060
D10
010
BQ
060
R10
5
330R
R10
6
330R
T100
EP7-
3F3
C10
0
220n
C10
510
n
C10
610
n
D10
8B
AV
70
T1g
R11
3
n.p.
C10
7
n.p.
Figure C.2: Power part including startup circuit
55
L200
EFD
15-3
F3-A
100-
S
GT2
C20
3
10u
C20
2
10u
D20
4
50W
Q10
FN
T201
IRFRC20PBF
AU
XV
in
AU
XG
ND
T200
IRFRC20PBF
D20
1U
S1M
D20
0
US1
M
R20
5
0R
C20
4
22n
AU
XV
pp
13
24
T202
EP7-
3F3
C20
1
220n
R20
0
15R
D20
218
VR
202
4k7
C20
0
220n
D20
3
SS16
R20
1
15R
R20
3
47R
Ipse
nse
R20
43R
3/W
1
C20
5n.
p.R
206
n.p.
Figure C.3: Auxiliary power supply
56
R30
14R
7 / 1
W
R30
0
4R7
/ 1W
C30
40u
1
C30
50u
1C
306
1u
L302
20u
L303
40u
Lin
Lout
Nin
Nou
t
C30
04n
7
C30
14n
7C
303
4n7
C30
24n
7
L300
A
1170
u
L300
B
1170
u
Earth
R30
222
R
R30
322
R
Figure C.4: Common- and differential mode input filter
57
VA
OU
T1
RT
2
VSE
NSE
3
D_M
AX
4
CT_
BU
FF5
GN
D6
VER
R7
ISEN
SE2
8
VC
C9
GT2
10PW
RG
ND
11
GT1
12
SS2
13
PKLM
T14
CA
OU
T15
ISEN
SE1
16
MO
UT
17
IAC
18
VFF
19
VR
EF20
U40
1U
CC
2851
3
PGN
D
PGN
D
R40
7
330k
R40
6
330k
R40
5
130k
VLs
ense
R42
019
k8 (2
0k)
SGN
D
C41
1 220p
SGN
D
157.
..494
uA
R40
4
374R
R40
3
374R
R41
1
820R
C40
747
nC
406
1u +
10u
PGN
D
Isen
se
GT1
R42
224
0k
R42
324
0k
R42
856
k
SGN
D
Vbo
ost
R41
810
k
SGN
D
C40
21u
SGN
D
R40
2
780R
R41
947
k
R41
6
4k7
C41
468
p
C41
31n
R41
710
k
R42
133
0R
T400
2N70
02
SGN
D
auxV
pp
SGN
D
D40
0
DIO
DE
R41
310
k
R41
510
k
12 3
U40
0A
LM32
4
C40
5
220p
C40
4
220n
R40
8
11k
R41
4
10k
C41
022
0p
SGN
D
765
U40
0BLM
324
Isen
se2
R41
011
k
R40
9
10k
R42
4n.
p.
C41
568
p
Vcc
Vcc
+V
C41
610
n
R42
510
0kR
427
68k
SGN
D
Vre
f
Vre
f
GT2
SGN
D
R42
6
100k
SGN
D
R42
9
22k
R41
247
kC
408
100n
C40
910
u
Vre
f
C40
01u
C40
11u
D40
615
V
Vcc
PGN
DR43
35k
6
R43
25k
6
T401
BSP
299
R43
047
0k
R43
422
0kD
405
24V
C41
810
n
R43
147
0k
D40
3
DIO
DE
R40
11k
5
D40
4LE
D
C40
3
10u
1 2
X40
0FA
N
R40
027
R
V-
8910
U40
0C
LM32
4
141312
U40
0D
LM32
4
C41
710
n
R43
8
1k8
R43
9
1k8
D40
7
LED
,red
D40
8
LED
,gre
en
Vcc
Vcc
R43
5
120k
R43
624
k
R43
713
0k
SGN
D
+C
412
4u7
C41
910
0n
C42
110
0p
C42
0
10n
D40
1B
AT5
4A
corr
ectio
n
corr
ectio
n
Figure C.5: Control circuit for boost and AUX converter, incl. bootstrap supply
58
Figure C.6: Components on the top side (heatsink side)
Figure C.7: Components on the bottom side
59
Figure C.8: Top /1st layer
Figure C.9:2nd layer
60
Figure C.10:3rd layer
Figure C.11: Bottom /4th layer
61
Appendix D
Controller Design and Simulation Matter
D.1 PFC Voltage and Current Controller Design
D.1.1 Matlab Script
%clear; close all; clc; format compact;
LN = 5e-6; % mains impedance
Uoref = 410;Poref = 600;
% input filter stuffR301 = 4.7;C304 = .1e-6;C305 = .1e-6;R300 = 4.7;L302 = 20e-6;L303 = 40e-6;C306 = 1e-6;
% boost inductor, real inductivity at nominal currentL100 = 85e-6; %187e-6;
% shunt (L100 current sensor)R108 = .01;
% resistor to convert multiplier output current% into a voltageRm = 374;
% Vo sensing voltage dividerRvou = 536e3; % high side resistor: R422, R423, R428R418 = 10e3; % low side resistor
% multiplier gainkm = 1; % Datasheet: 0.8 - 1.2 [1/V]
% output filterRL = Uoref^2/Poref;Re = 0.008; % measured ESR of Co: EPCOS B43504-A2227-MCo = 220e-6;
s = tf(’s’);
% other controller related transferfunctionsRiac = (130+2*330)*1e3; % OhmsCff = 4.7e-6; % voltage feedforward lowpass cap.Rff = 19.8e3; % 19.8k, alternatively 20k; d.o., res.Zff = 1/(1/Rff+s*Cff);[nZff, dZff] = tfdata(Zff, ’v’);
%==================================
62
% input impedance, everything before the switch,% including mains inductance% used to design the current controller KiZi = R108+L100*s+1/(C306*s+1/(L303*s+1/(1/R300+1/(L302*s))...
+1/(1/(R301+1/(C304*s))+C305*s+1/(LN*s))));[nZi, dZi] = tfdata(Zi, ’v’);
% PWM modulator transfer function D --> Usw,avgGpwm = Uoref;
% sensed current to voltage tf.Mi = R108;
if 0% Ki design:wico = 2*pi*5e3; % desired crossover freqwiz = 2*pi*2e3; % controller zero freq.wip = 2*pi*8e3; % controller pole freq.
% "1 gain" controller transfer function:Ki = 1/s*(s/wiz+1)/(s/wip+1);ki = 1/abs(freqresp(-Ki*Gpwm/Zi*Mi, wico)) % required ki% final controller transferfunction:Ki = ki*Ki;
elseR403 = 374; % defined by peak value of input currentC406 = 11e-6; % C-zeroR411 = 820; % R-zeroC407 = 47e-9; % C-poleKi = 1/(R403*(C406+C407)*s)...
*(R411*C406*s+1)/(C406*C407*R411/(C406+C407)*s+1);ki = 1/(R403*(C406+C407));wiz = 1/(C406*R411);wip = (C406+C407)/C407*wiz;
end
[nKi, dKi] = tfdata(Ki, ’v’);
% closed loop TF of current loopGi = Ki * Gpwm / Zi; % from Iref to IL100Li = Gi * Mi; % from Iref to Isense (resp. VIsense)Ti = Gi / (1 + Li); % Iref to IL100, closed loopfigure(3);margin(Li);title(’Bode Diagram of open Current Loop’);
% Input Filter TFs for simulink modelZ2 = 1/(1/(R301+1/(s*C304)) + s*C305);[nZ2, dZ2] = tfdata(Z2, ’v’)G3 = 1/(1/(1/(s*L302)+1/R300)+s*L303);[nG3, dG3] = tfdata(G3, ’v’)
% output filter TF for simulink modelZo = 1/(1/RL+1/(Re+1/(s*Co)));[nZo, dZo] = tfdata(Zo, ’v’)
% gain of output voltage divider:C416 = 10e-9;Rvols = 1/(1/R418+s*C416);%kVo = Rvols/(Rvou+Rvols);kVo = R418/(R418+Rvou);
63
%===== linearised small signal voltage loop TF:UinAP = 110*.8; % Operating point, rms voltagefmains = 50; % 60 or 50, nearly no influencewmains = fmains*2*pi;
% multiplier gain for small signal Vea:gmultvea = UinAP/Riac / (UinAP/Riac*.5*.9*Rff)^2Gv = gmultvea * Rm * Ti * Zo;
if 0% voltage controller:wvco = 2*pi*10;wvz = 2*pi*8; % make it fast for small capacitorswvp = 2*pi*20;
Kv = (s/wvz+1)/(s*(s/wvp+1));Lv = Kv * Gv * kVo;% calculating required kv:kv = 1/abs(freqresp(Lv, wvco))
% update transferfunction with new kv:Kv = kv * Kv;Lv = kv * Lv;
elseR412 = 47e3; % R-zeroC409 = 10e-6; % C-zeroC408 = 100e-9; % C-pole
Kv = 1/(Rvou*(C409+C408)*s)...*(C409*R412*s+1)/(C409*C408*R412/(C409+C408)*s+1);
kv = 1/(Rvou*(C409+C408));wvz = 1/(C409*R412);wvp = 1/(C409*C408*R412/(C409+C408));
Lv = Kv * Gv * kVo;end
[nKv, dKv] = tfdata(Kv, ’v’);intKvInit = 0;
figure(4);margin(Lv);title(’Bode Diagram of open Voltage Loop’);
Gpower = Gv*Kv/(1+Lv); % tf Voref --> Vo
if 0%==== now simulate it.[T, X, Y] = sim(’boost.mdl’, [0 1]);% Y(:,1) Vmains% Y(:,2) Imains% Y(:,3) Vo% Y(:,4) Io% Y(:,5) IL% Y(:,6) Vff% Y(:,7) ILref
figure(3);plot(T,Y(:,1)/UinAP,T,Y(:,2)/(Poref/UinAP),...
64
T,Y(:,5)/(Poref/UinAP));legend(’Vmains’, ’Imains’, ’IL100’);
figure(4);plot(T,Y(:,3)/Uoref,T,Y(:,4)/(2*Poref/Uoref));legend(’Vo’, ’Io’);
figure(5);plot(T,Y(:,6));title(’Vff’);
end
disp(’ ’);disp(’parameter set for current controller:’);KinKi2 = nKi(2)nKi3 = nKi(3)dKi1 = dKi(1)dKi2 = dKi(2)kiwizwipdisp(’ ’);disp(’parameter set for voltage controller:’);KvnKv2 = nKv(2)nKv3 = nKv(3)dKv1 = dKv(1)dKv2 = dKv(2)kvwvzwvp
65
D.1.2 Simplorer Schematics and Results
Inpu
t_I
4.7
2040
33.5
p
1100
100n
Inpu
t_V
.V [V
] 2
* In
put_
I.I [A
] C
apac
itor.V
[V]
Out
put_
I.V [V
] 0.
1k *
D.V
AL
t [s]
0.5k
-0.5
k0
-0.4
k
-0.3
k
-0.2
k
-0.1
k
0.1k
0.2k
0.3k
0.4k
00.
650
m0.
10.
150.
20.
250.
30.
350.
40.
450.
50.
55
Figure D.1: Simulation of controller startup phase
66
Vm
ain
A
R10
8
Out
put_
I
Inpu
t_I
L100
250u
250u
8u 550
250n
5 8u
50
250n
5u50
u
50u
5u
100n 4.
7
100n
4.7
20u
40u 1u
100p
32n
85u34
p
30m
12.5
k28
4p 7
10m
7
26n 28
5p 7
285p
27n
38n
199u
199u
199u
199u
7.9m
7.9m
71n
71n
7.9m
7.9m
71n
71n
CO
NS
T
CO
NS
T
Pou
t62
5
V1r
ms
110
50
D11
2
G(s
)
LIM
IT
PW
MK
i
D
PW
M
T1013n
500p
140m
4.7n
4.7n
1170
u
4.7n
4.7n
1170
u
M1
100n
100n
2222
G(s
)
Kv
790k
GA
IN
GA
IN1
G(s
)
Zff
LIM
IT
LIM
IT1
xn
PO
W1
EQ
UB
L
Iref
536k
10k
SU
M1
LIM
IT
LIM
IT2
+ V
Inpu
t_V
SU
M2
SU
M3
GA
IN
GA
IN2
SU
M4
G(s
)
Inte
grat
e1
SU
M5
G(s
)
Inte
grat
e2
SU
M6
GA
IN
GA
IN3
CO
NS
Tkv
5.83
Cap
acito
r
Ierr
Figure D.2: Simulation schematic including LISN and EMC filter
67
D.2 Auxiliary Flyback Controller Design
D.2.1 Matlab Script
close all; clear; clc;% Auxiliary Flyback peak current mode control with UCC28513% PIT1 controller parameters:R413 = 10e3; % vo divider, upper resistorR415 = R413; % vo divider, lower resistorR408 = 11e3; % OpAmp feedback, series with C404C405 = .22e-9; % feedback, parallel to R408/C404C404 = 220e-9; % feedback, in series with R408% these values cause crossover at ~14 kHzC410 = .22e-9;R414 = 10e3;% flyback parameters:PColors = [’r’, ’y’, ’g’, ’k’, ’b’];Pout = [1, 3, 1.5*3+3, 10, 13]; % min...max loadVo = 15;RL = Vo^2./Pout;Rs = 1.5; % shunt resistor (1.5 Ohm, 1206)n = 3.87;Co = 32.22e-6; % (3x 10u, 2x 1u, 1x 220n)Re = 0.06/(2*pi*250e3*Co) % esr = tan(d)/(2 pi f C)
s = tf(’s’);[dum, x] = size(Pout);for k = 1:x
Gfv(k) = RL(k)*n*(1+Co*Re*s)/(1+Co*RL(k)*s);end
lenw = 1e4; w = 2*pi*logspace(0,6,lenw);clf;figure(1); clf; hold on;for k = 1:x
bode(Gfv(k),PColors(k),w);endtitle(’Flyback Transferfunction: Gfv(s) = Vo/Ipk’);legend(’1W’, ’3W’, ’7.5W’, ’10W’, ’13W’);hold off;
% PIT1 controller with R413 at its input:Rin = R413; % upper res only (amp dynamics neglected)Kfv = 1/(Rin*(C405+C404)*s)*...
(C404*R408*s+1)/(C405*C404*R408/(C405+C404)*s+1);fvI = 1/(Rin*(C405+C404) * 2*pi)fvz = 1/(C404*R408 * 2*pi)fvp = 1/(C405*C404*R408/(C405+C404) * 2*pi)Fout = 1/(s*C410)/(R414+1/(s*C410));
% open loop systemfor k = 1:x
L(k) = Kfv*Fout*Gfv(k)/Rs;endfigure(3);bode(L(1), PColors(1), L(2), PColors(2), L(3),...
PColors(3), L(4), PColors(4), L(5), PColors(5));legend(’1W’, ’3W’, ’7.5W’, ’10W’, ’13W’);figure(4); margin(L(1));
68
Appendix E
Completion
E.1 Corrections
E.1.1 What is working
Even though the project was prolonged by one month, the converter was not work-ing as expected by the end of July, one month after the end of the semester. ThusMarcelo Lobo Heldwein, the supervisor of this project, continued the work. Hefixed the voltage control loop and adjusted the current control loop to work withthe very low shunt resistor (10× lower than recommended).
Besides the corrections mentioned in the following sections, the devicesR100 andR101 have to be connected toPE (Earth ) instead ofPGND.
The thyristor drive circuit is not working as expected yet. It is bypassed for testingand has to be replaced by a new design in the next development step.
E.1.2 Voltage Loop
It was discovered that the voltage loop amplifier is a transconductance amplifier.Thus the following modifications are made:
• connectC408 andC409 to SGNDinstead ofVSENSE.
• use the following values:C408 = 1µF , R412 = 18kΩ, C409 = 1µF
• R422 andR423 are replaced by4× 120kΩ in series.
• R405 to R407 are replaced by4× 160kΩ + 1× 150kΩ in series.
• R420 = 30kΩ to provide a larger feed forward voltage andC412 = 2µF forfaster reaction.
E.1.3 Current Loop
The current loop has to be modified to allow for the very small current measure-ment shunt. This mainly because the differential amplifier has a relatively largeoffset voltage.
• R403 andR404 are set to1.6kΩ, R402 to 1.1kΩ.
• R411 = 18kΩ, C406 = 2.2nF , C407 = 68pF
69
E.2 Electrical Specification
The corrections mentioned above lead to the electrical specification listed in tablesE.1to E.5:
nominal voltage single phase,110/230 VAC,rms
operating voltage range 88 to 270 VAC,rms
frequency 45 to 60 Hzpower factor > 0.985 from 50 to 100% loadTHD < 12% from 50 to 100% loadswitching frequency 250 kHz
Table E.1: AC Input
nominal voltage 400± 30 VDC
rated output power 660 W
hold-up time 10 ms
efficiency > 90% from 50 to 100% load atUin = 88V
> 95% from 50 to 100% load atUin = 230V
Table E.2: DC Output
output voltage +15 VDC (non-isolated)output power 13 W
Table E.3: AUX Supply
height 37 mm
width 84 mm
depth 120 mm
weight 320 g
power density 2.06 kW/kg
1.77 kW/l
Table E.4: Physical Specification
input over-current 17.5 A
output over-voltage 430 V
input under-voltage ∼= 85 V
power limitation 750 W
fuse 10 A
Table E.5: Protection Circuits
70
E.3 Experimental Results
E.3.1 Waveforms
Figure E.1: Steady state operation at660W , 110V ; input current (5A/div), phasevoltage (50V/div)
Figure E.2: Steady state operation at660W , 230V ; input current (2A/div), phasevoltage (100V/div)
71
Figure E.3: Steady state operation at660W , 110V ; boost inductor current(5A/div), converter output voltage (200V/div), time scale2ms/div
Figure E.4: Steady state operation at660W , 110V ; converter output voltage ripple(10V/div), time scale2ms/div
72
Figure E.5: Steady state operation at660W , 110V ; boost inductor current(5A/div), control voltage (1V/div, it is proportional to the inverse of the duty cy-cle), converter output voltage (200V/div), time scale2ms/div
Figure E.6: Steady state operation at660W , 110V ; boost inductor current(10A/div), voltage across the switch (200V/div), time scale2ms/div
73
Figure E.7: Steady state operation at660W , 110V ; boost inductor current(10A/div), voltage across the switch (200V/div), time scale1µs/div
From figureE.7it is possible to calculate the inductance of the boost inductor closeto the expected peak current as follows:
UL∼= 394V ∆t ∼= 2.0885µs (E.1)
∆IL =4.37V
10mV/div· 10A/div ∼= 4.37A (E.2)
Lboost = UL ·∆t
∆IL= 394V · 2.0885µs
4.37A=⇒ Lboost
∼= 188µH (E.3)
74
Figure E.8: Switch turn on detail: operation at660W , 110V ; boost inductor cur-rent (10A/div), voltage across the switch (200V/div), time scale20ns/div
Figure E.9: Switch turn off detail: operation at660W , 110V ; boost inductor cur-rent (10A/div), voltage across the switch (200V/div), time scale20ns/div
75
E.3.2 Static Measurements
Each of the following diagrams shows some characteristic value of the convertermeasured at different input voltages,88, 110 and230V , versus output power.
89
90
91
92
93
94
95
96
97
98
0 100 200 300 400 500 600 700
Output power [W]
E f f
i c i e
n c y
[ % ]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.10: Efficiency curves
0
10
20
30
40
50
60
70
80
0 100 200 300 400 500 600 700
Output power [W]
T o t
a l l o
s s e s
[ W
]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.11: Total losses curves
76
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
0 100 200 300 400 500 600 700
Output power [W]
T e m
p e r a
t u r e
r i s
e [
C ]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.12: Heatsink temperature rise∆T curves
0
1
2
3
4
5
6
7
8
9
0 100 200 300 400 500 600 700
Output power [W]
I n p u
t c u r
r e n t
[ A
]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.13: Input current RMS value curves
77
0.984
0.986
0.988
0.990
0.992
0.994
0.996
0.998
1.000
0 100 200 300 400 500 600 700
Output power [W]
P F
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.14: Power factor curves; The voltage THD was kept below0.7% for allthe measurements.
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
0 100 200 300 400 500 600 700
Output power [W]
I n p u
t c u r
r e n t
T H
D [
% ]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.15: Input current THD curves; The voltage THD was kept below0.7%for all the measurements.
78
0
2
4
6
8
10
12
14
0 100 200 300 400 500 600 700
Output power [W]
P h a s
e d i
s p l a
c e m
e n t [
d e g ]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.16: Input current phase displacement
387
388
389
390
391
392
393
394
395
0 100 200 300 400 500 600 700
Output power [W]
O u t
p u t D
C v
o l t a
g e [
V ]
U in = 230 V
U in = 110 V
U in = 88 V
Figure E.17: Output voltage regulation curves
79
E.4 Recommended Improvements
1. The soft-start circuit should be redisigned. That means that the driving cir-cuits for the input rectifier bridge thyristors should be changed.
2. The use of a single IC to control both PFC and auxiliary supply is a goodidea, but the internal structure of the used IC just allows the auxiliary sup-ply to start after the PFC is already operating. That is a nice feature for adown stream DC/DC converter, but not for the auxiliary supply. The use of aseparated IC for the auxiliary supply control would allow a more controlledstart-up. This gives also the advantage that the second gate driver, whichis syncronised with the boost converter, can be used for the planned secondstage DC/DC converter.
3. Care should be taken when designing the PFC inner current control loopwhen using a low value shunt resistor because the control operational ampli-fier offset is not small (±5mV ).
4. The peak drive currents for the boost switch are currently lower than2A.Increasing switching noise and reducing switching times by lowering thegate series resistors could lead to lower switching losses.
80
Glossary
I1 converter input current
Io output current of a converter
M Vo
Vin, the ratio between output and peak input voltage
Po nominal converter output power
RL load resistance
TN mains period
Ts converter switching period
Vo output voltage of a converter
Vfo output voltage of the auxiliary flyback
Vmax maximum rms converter input voltage,= 1.2 · Vnom
Vmin maximum rms converter input voltage,= 0.8 · Vnom
Vnom nominal rms input voltage, sometimes indexed withUS (110Vrms, 60Hz)or EU (230Vrms, 50Hz)
Vth MOSFET threshold voltage
Xglob variable with global relation to a50 or 60Hz half period
Xloc variable with local relation to a sampling periodTs
I, V amplitude of some sinusoidal current or voltage
I1 peak current in transformer’s or multi winding inductor’s primary winding
ωN mains frequency[
rads
]fN mains frequency[Hz]
gfs transconductance
n transformer winding ratioN1N2
vp MOSFET plateau voltage→ switching
vz half intermediate DC voltage of a two-stage converter
81
Bibliography
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[2] J. W. Kolar, Leistungselektronische Systeme 1, PES ETHZ, 2004
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[4] IRF, Power MOSFET Avalanche Design GuidelinesApplication Note AN-1005
[5] IRF, Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETsand IGBTs
Application Note AN-944
[6] IRF, A More Realistic Characterization of Power MOSFET Output Capaci-tance Coss
Application Note AN-1001
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http://www.infineon.com/cmc%5Fupload/documents/052/544/SiCDesignRules.pdf
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[12] I. Barbi et al., Correção de Fator de Potência de Fontes de Alimentação, Uni-versidade Federal de Santa Catarina, 1995
[13] L. Yanget al., Modeling and Characterization of a 1KW CCM PFC Converterfor Conducted EMI Prediction, Virginia Polytechnic Institute and StateUniversity, 2004
[14] S. Wanget al., Controlling the Parasitic Parameters to Improve EMI FilterPerformance, Virginia Polytechnic Institute and State University, 2004
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