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9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com
DfX in Electronic Packaging
March 25, 2019 | Kayleen Helms
9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com
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Agenda
DfX in Electronic
Packaging
02 Package Design
Background01
06
03 Reliability Topics
04 Enabling DfX with Customers+
05
2
Q&A (if time)
Future Trends
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History of Intel
Back in 1968, two scientists, Robert Noyce and Gordon Moore, founded Intel with a vision for semiconductor memory products.
By 1971, they had introduced the world’s first microprocessor.
Since then, Intel has established a heritage of innovation that continues to expand the reach and promise of computing while advancing the ways people work and live
worldwide.
3
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One Law to Rule them all……
4
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Package Design Executing to Moore’s Law
• Resulting in FLI and SLI scaling
5
Hi-K Metal Gate
Strained Silicon
3D Transistors
65 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm90 nm
Enabling new devices with higher functionality and complexity while
controlling power, cost, and size
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Package Function and Constraints
6
Thermal
Management
Environ.
Friendliness
Silicon
Protection
Assembly/
System
Fit/LifeCost
Interconnect
Scaling
High Speed
Signaling
Power
Delivery
Functional
Integration
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Package Technology Lifecycle
7
Year 0 Year 1 Year 2 Year 3 Year 4
(Mostly) Internal Research Pathfinding Development
Product
Package
Silicon
Test
Product & TD Activities are Synchronized at Intel (with Suppliers and Customers as required). University engagement complements TD with Research in the (5-8)+ Years Space.
First Product
Si
Technology
Definition
Technology
Definition
Technology
Definition
Proof of
Concept
Proof of
Concept
Proof of
Concept
Pro
cess
Flo
w
Desi
gn R
ules
Ma
teri
als
Und
er
Cha
nge
Cont
rol
Func
tiona
l and
Test
Vehi
cles
Architecture
Definition
Product
OpportunityValidation
Pro
duc
t Readin
ess
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Package Design
• Drivers
− Electrical – IO & power
− Thermals
− Size & cost
• Requirements/Constraints
− Supplier capabilities
− Package Manufacturability
− Customer assembly
− Reliability on board/in system
− Sustainability, Ethical, etc.
• Collaborations
− OxM’s, CM’s, suppliers
− Pathfinding to Certification
• Customer Collaterals
− Design – board/system
− Manufacturing/Assembly
• Standards, etc.
− Drive, publish, contribute
− JEDEC, IPC, iNEMI, etc.
− ECTC, InterPACK, SMTAi, etc.
Optimization Process Enabling Environment
8
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Ethical Constraints: Conflict-Free Minerals
• 2009 Issue: Four key metals sourced from Democratic Republic of Congo
− Possible for procurement to benefit armed militants in civil war
− If stop sourcing from DRC, supply shortages and cost to DRC civilians
• Ethical Design Requirement
− Audit suppliers and unravel complex global supply chain
− Ensure the metals were conflict-free through entire supply chain
− 2014+ Intel Conflict-Free Processors AND establishment of Electronic Industry Citizenship Coalition, Global e-Sustainability Initiative, US laws, etc.
9
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Product Reliability: A Definition
• Manage product development & manufacture to ensure assembly and field failure meets customer expectations
• Multiple approaches from atomic-level models to test structures:
− Defects and process excursions
− Screening and guard banding
− Intrinsic mechanisms in qualifications & the field
− Designing to manage intrinsic & defect mechanisms
− Circuit reliability
− Field reliability experience
− Failure goals and use conditions (GUC)
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Product Field Failure Types
• Failure type evolves thru product life. GUC starts after class test
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Si Si
IC MFG OxM End Users
Quality Reliability
Infant Mortality
Constant
Wearout
Fab Sort Pkg Class Ship Test System Ship Use EOL
Test Test
Yield Loss
Q&R manages quality - product meets specification at OEM, &
reliability - product functions correctly thru intended use life
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Goals and Failure Types
• Quality - @ OxM/CM: function to spec at OEM− Maintain below a specific DPM
• Reliability – @ end user: function to spec to end of life − Hard fails:
− Specify as DPM (integrate fail) or FIT (average fail rate)
− Can segment by mechanism or sum them
− Left (infant mortality) & right (wearout) sides of bathtub curve
− For design phase, may want targets per mechanism
• Soft fails - @ end user: recoverable (or data corruption)− Describe in FIT, random in time
− Example: SER due to cosmic rays and alpha particles
12
All have goals, met explicitly (KBQ) or by compliance (SBQ)
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Reliability Stress Assessments
• Many stresses req’ts are standardized (see JESD-47):− Especially, temperatures and sample size (for statistics)
− Slow evolution of IC technology supports this approach
• Sample size (SS) depends on assessments:− Smaller SS for intrinsic fails, all units similar (may be < 100)
− Larger SS for extrinsic fails, some units have defects (>1000)
− SS may be based on confidence levels from binomial stats
• For discussion purposes can categorize, but today limited focus:− OEM: Si and package quality
− Field: Si reliability
− Field: Package reliability
13
“Stress-Test-Driven Qualification of Integrated Circuits”, JEDEC JESD-47 Rev I (2012)
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Package Field Assessments (Reliability)
• Common combinations of stimuli to evaluate failure modes:
14
Stress T (C) RH1 DT (C) Vcc Durat. Mechanisms
HTSL: High
Temp Storage
Life
>150
C
No No No 1000
hr
Atomic diffusion, e.g., ionic
contamination, contact
integrity, metal voids.
UHAST:
Unbiased Temp.
Humidity
130 C 85% No No 96 hr Interfacial delamination and
materials property
degradation
TC:
Temperature
Cycling2
See
DT
No B:
-55 C /
125 C
No 700
cycle
Mechanical integrity at
temperature extremes, e.g.,
Interlayer & solder joint
cracking, delamination.
HAST:
Temperature
Humidity Bias
130 C 85% No Vcc
max
96 hr Moisture-accelerated
effects on device and
package, e.g., corrosion,
passivation layer defects,
contamination.
1.Relative Humidity
2.May adjust based on physical properties, e.g., stay below glass transition temp
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Standards-Based Qualification Visualized
• Advantages:
− 1 Supported by, and adds to similar historical data
− 2 Based on stresses product will experience, T, RH, DT…
− 3 Detect failures associated with interactions, e.g. pkg-Si
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Cu
mu
lati
ve
We
aro
ut
Use Time
0 Use Life
Wearout
Standard
Stress
Above
Use Life
Standard
Stress
Below
Use Life
Right side of
bathtub curve
See Sematech 00053958A-XFR
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Limitations of Standards
• Generic, not product-specific, failure GUC and failure models
• Maybe conservative or aggressive
• Standards may lag scaling impact on failure models
• Long feedback loop to pre-Si design, hard to use post-Si:
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QualMany data
turns & learning
Monitors
improvements
Definition Design Development Production
Needs
SER
ESDElectromigrationSolder Joint Cracking
Infant MortalityTDDBVmin Shift
Fail Mode(examples)
Pre-Silicon Post-Silicon
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Knowledge-Based Qualification (KBQ)
• A Definition: Using knowledge of failure mechanisms to adjust qualification to better meet customers’ quality & reliability needs:
− 1) Adjust standard stress time to represent customer need
− Increase (cover risk) or decrease (reduce cost and qual time)
− 2) Create unique stresses to expose specific mechanism
− Ex: JESD22-A117A, non-volatile memory data patterns
− 3) Predict field failure to better meet customer expectations
− Most needed for extremes of environment, usage or design
17
17
KB methods are discussed in standards body & other docs
See JEDEC JESD 94 & JEP 148 and Sematech 00053958A-XFR & 99083810A-XFR
Failure Model
GoalFailure
vs. timeP/F
Field Use Cond
Process & Product Data
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Example: Radiation Flux Use Condition
• What radiation flux represents users? It depends on user altitude
− Need intended usage, e.g., server, desktop, etc.
− Could assume systems population, as an approximation
› If usage is avionics or space, need other data like times at altitudes
• An approach*:
− Calculate flux as weight average of flux (altitude) and population (altitude)
− Guard band for uncertainties & to sufficiently protect extreme users
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* See Kwasnick et al., IRPS 2014
Rel. R
adia
tion
Flu
x
Denver
Mexico
City
Quito
0 1000 2000 3000 4000
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Q&R Goal Setting
• To set goals balance:
• Other insights:− Goals are market segment specific (automotive, phone…)
− Products in same market may have the same goal
− Goals are a business or mission-specific decision
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Goals and Usage Segments
• Relative goals between usage segments (markets) examples:− Tighter means more challenging to meet, looser means easier
• Comments:− Server use cases may be more demanding
− Auto Entertainment is cost-driven
− Phone may have shorter use life
• Products sold to multiple segments: meet goal “envelope”
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Established per previous slide & with customer engagement
Segment Soft Quality Reliability
Phone Looser
Notebook
Server Tighter
Auto Entertainment Tighter Tighter
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Use Conditions Through Product Life
21
End user use conditions depends on application
Assembly Shipping Storage Shipping
System Assembly Shipping End user
IC MFG
OEM End Users
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Standards vs. Knowledge-Based Methods
22
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Examples Enabling DfX with Customers+
• Pb-Free SLI Mechanical Reliability
− BFI (board-flexure) & Dynamic Load strain guidance approaches
› Developed bend mode invariant board-level strain indicator of assembly SJR risk
› Correlated board-level strain indicator of shock, etc. SJR risk (shipping and field)
› Revised methodology to meet customer needs, trained customers, published/standards, etc.
− SLI Adhesive use guidance
› Benefits in dynamic load vs. potential reliability losses in TC
› Approaches to evaluate material and coverage choices
• SJR and Assembly
− Optimized land pattern guidance for printed board
• Thermals and Reliability
− Developed additional thermal load guidance approaches
− Improved methods to validate thermal solution static & dynamic loads
− Trained customers, etc.
23
Length
Width Height
Substrate
Die
Corner Glue
Board
Temperature,oC
CT
E,p
pm
/oC
Mo
du
lus
,G
Pa
-50 -25 0 25 50 75 100 125
100
120
140
160
180
200
0
0.5
1
1.5
2
2.5
3
3.5
4
CTE
Modulus
Frame 001 16 Jan 2014 |Thermo mechanical Properties
Tg
CTE2
E2
CTE1
E1
Corner Glue Expansion/Contraction in TC
Fa
Fs
Die
Substrate
Board
Corner-glue Behavior in TC
Package corner joints
Die Shadow joints
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Examples Enabling DfX with Customers+
• Potential Benefits from Low Temp Solder Usage (Guidance & iNEMI WG)
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Green House Gas Reduction SMT Margin for Thin Designs
Lower Electricity Usage Reduces Cost Reduced PLC Environmental Impact
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Examples Enabling DfX with Standards
• Drive new or revised standards for customer assembly
− JEDEC SPP-024 revision follows JEDEC Moisture Sensitivity Levels approach
› “Reflow Flatness Requirements” from large industry data set
› Level 1: tightest, assumes no board or SMT optimization
› Level 2: ~similar to current w/HT board ≤25% ball diameter
› Level 3: loosest, w/board (e.g. ≤ 50um) & SMT optimization
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Future Packaging Driven by High Bandwidth Need
High BW Demand has Spurred Recent Interest in Dense MCPs2
Year 2007 2010 2013 2017
Product Xeon Core 4th gen core 8th gen core
I/O BusFront side bus
(FSB)QPI OPIO HBM
# of signals
(data)64 32 (differential) 128 1024
Signaling rate
(Gb/s)1.333 6.4 6.4 1.6
BW (GB/s)1 10.7 25.6 102.4 204.8
1. Intel specific data only. BW per memory device shown.
2. Dense MCP demand also driven by need for (wide & slow) parallel links which are generally understood to be power efficient.
These links require high density interconnects
HBM Adoption Drove Transition to EMIB
26
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IP Integration with Chiplets Drive Advanced Packaging
27
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Summary
• Package Design: interconnect scaling, IO, thermals, cost, conflict-free, etc.
• Approaches for Package DfX with Customers− Quality & Reliability Challenges
› Impact to design via Knowledge-Based (vs. Standards)
› Key for Customer-Supplier: agreed goals as part of design so no surprises
− Examples Enabling Customer DfX
› SJR – board-level strain guidance, land-pattern design, SLI adhesive guidance, LTS, etc.
› Thermals & Reliability - thermal load guidance and validation methods
› Assembly – land-pattern guidance, LTS, industry standards for SMT (e.g. HT Flatness), etc.
• Future Packaging Challenges− 2x BW growth every 2yrs!
− DARPA modular chiplets disruption coming!
28
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Kayleen Helms, PhD
About Dr. HelmsShe completed a BS in civil engineering (Marquette University) and a MS, PhD & post-docs in aerospace engineering
(Texas A&M University). Dr. Helms then joined Intel’s TMG ATTD organization in Chandler, AZ where she has worked in
multiple groups supporting manufacturing, design, and quality & reliability projects. She is currently the External
Engagement Lead for Core Competency driving efforts interacting with customers, industry consortia, suppliers, and
various Intel organizations to address structural integrity challenges in manufacturing, thermal-mechanical enabling, and
other quality & reliability risks.
Contact
(preferred)
https://www.linkedin.com/in/kayleen-helms
29
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Questions (if time)
• Thank you for your attention….
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