Digital Lab Manual

Digital lab manual B.KALAIMATHI AP/ECE

LIST OF EXPERIMENTS

1. Verification of Boolean theorems using digital logic gates

2. Design and implementation of combinational circuits using basic gates for arbitrary functions, code converters, etc.

3. Design and implementation of 4-bit binary adder / sub tractor

using basic gates and MSI devices

4. Design and implementation of parity generator / checker using basic gates and MSI devices

5. Design and implementation of magnitude comparator

6. Design and implementation of application using multiplexers/

Demultiplexers

7. Design and implementation of Shift registers

8. Design and implementation of Synchronous and Asynchronous counters

9. Simulation of combinational circuits using Hardware Description

Language (VHDL/ Verilog HDL software required)

10. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL software required)


AND GATE: SYMBOL: PIN DIAGRAM:

OR GATE:


EX. NO: 1 STUDY OF BASIC DIGITAL IC’s DATE:

AIM:

To study about the basic digital IC and verify their truth tables.

APPARATUS REQUIRED:

S.NO APPARATUS NAME RANGE QUANTITY

1 IC Trainer Kit 1

2 Patch Cords - 14

COMPONENTS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1 AND Gate IC 7408 1

2 OR Gate IC 7432 1

3 NAND Gate IC 7400 1

4 NOR Gate IC 7402 1

5 XOR Gate IC 7486 1

6 NOT Gate IC 7404 1


NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :



2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :



NOR GATE:


RESULT:

Thus the truth table of Digital logic gates and the working of various gates are studied

and verified.

VIVA QUESTIONS:

1. Draw the Pin diagram for all IC.

2. Explain the working procedure.

3. Draw the symbol diagram for all IC?

4. Explain the truth table.

5. Inside an IC 7408, How many AND gates are there?

6. How do you identify the gates?

7. Define an IC?

8. Difference between AND gate and OR gate?

9. Differentiate between NAND gate and NOR gate?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


DEMORGAN ’S THEOREM:

a) (x+y)’=x’y’ x x+y (x+ y)’

y

U4A

74ALS1032A

1

23

U5A

74AC04

1 2

TRUTH TABLE:

x Y (x+y)’ x’ y’ x’y’

0 0 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 0

a) (xy)’=x’+y’

TRUTH TABLE:

X Y (xy)’ x’ y’ x’+y’

0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0


EX NO.: 2 VERFICATION OF BOOLEAN THEORM USING DATE:

LOGIC GATES AIM: To design the following Boolean theorem using logic gates and verify the truth table. APPARATUS REQUIRED:

SI.NO APPARATUS NAME RANGE QUANTITY

1. Digital trainer kit - 1 2. IC’s 7432,7408,7404 Each 1 3. Connecting wires _ As required

THEOREM: DEMORGAN,S THEOREM: a) (x+y)=x’y’ b) (xy)’=x’+y’ ABSORBTION THEOREM: a) x+xy=x b) x(x+y)=x DISTRIBUTION THEOREM: a) x+(y+z)=(x+y)+z b) x(yz)=(xy)z OTHER THEORM:

a) x+x=x b) x+x’=1

DUALITY THEOREM:

a) A(B+C)=AB+AC b) A+(BC)=(A+B)(A+C)


ABSORBTION THEOREM: a) x+xy=x

TRUTH TABLE:

X Y x+xy X 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1

b) x(x+y)=x

TRUTH TABLE:

x Y x+y x(x+y) x

0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1


PROCEDURE:

1. Make a circuit connections are as the circuit diagram. 2. Given the VCC ’s on all IC’s. 3. Given the input and output for the following theorem connection in DTK. 4. Verify the output of the truth table for the following theorem.

(i) Demorgan’theorem. (ii) Distributive theorem. (iii) Absorbtion theorem (iv) Basic Boolean theorem.


DISTRIBUTIVE THEOREM: a) x+(y+z)=(x+y)+z

TRUTH TABLE:

x Y z x+(y+z) (x+y)+z 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1


b) x(y+z)=(xy)z

TRUTH TABLE:

x y Z x(yz) (xy)z 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

OTHER THEOREM:

a) x+x=x b) x+x’=1


TRUTH TABLE:

x x x+x

0 0 0 1 1 1

TRUTH TABLE:

x x’ x+x’ 0 1 1 1 0 1

DUALITY THEOREM:

TRUTH TABLE:

A B C A+BC (A+B)(A+C) 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1


RESULT: Thus the boolean theorem was verified using logic gates. VIVA QUESTIONS

1. What is Boolean theorem? 2. What is Boolean algebra? 3. What is the difference between Boolean algebra and logic gates? 4. True or False: The commutative law of Boolean addition states that A+B=

AxB 5. Applying Demorgan’s theorem to the expression , we get 6. What is the aim for using Boolean algebra to simplify logic expressions? 7. Boolean algebra is different from ordinary algebra in which way? 8. What are the basic theorems of Boolean algebra? 9. What are demorgan’s law? 10. Explain the uses of Demorgan’s law.

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


CIRCUIT DIAGRAM:


EX NO.: 3 DESIGN AND IMPLEMENTATION OF COMBINATIONAL DATE:

CIRCUITS USING BASIC GATES FOR ARBITRARY

FUNCTIONS, CODE CONVERTERS AIM: To design and implement the combinational circuits using logic gates arbitary function and code converters and verify the truth table. APPARATUS REQUIRED:

SI.NO APPARATUS QUANTITY

1 Digital trainer kit 1 2 IC 7408,7432,7411,7404,7402,7486,7404 Each1 3 Patch cords & connecting wires As required


TRURTH TABLE:

S.NO INPUT OUTPUT

A B C D F= D ' B ' + C ' ( B ' +A' D )

1 0 0 0 0 1

2 0 0 0 1 1

3 0 0 1 0 1

4 0 0 1 1 0

5 0 1 0 0 0

6 0 1 0 1 1

7 0 1 1 0 0

8 0 1 1 1 0

9 1 0 0 0 0

10 1 0 0 1 1

11 1 0 1 0 1

12 1 0 1 1 1

13 1 1 0 0 0

14 1 1 0 1 0

15 1 1 1 0 0

16 1 1 1 1 0



BINARY TO GRAY CODE CONVERTOR:

LOGIC DIAGRAM:

K-Map for G3:

G3 = B3 K-Map for G2:



K-Map for G1:

K-Map for G0:

TRUTH TABLE: | Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0



GRAY CODE TO BINARY CONVERTOR :

LOGIC DIAGRAM:

K-Map for B3:

B3 = G3



K-Map for B2:

K-Map for B1:



K-Map for B0:

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1



BCD TO EXCESS-3 CONVERTOR :

LOGIC DIAGRAM:

K-Map for E3:

E3 = B3 + B2 (B0 + B1)



K-Map for E2:

K-Map for E1:



K-Map for E0:

TRUTH TABLE: | BCD input | Excess – 3 output |

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 1 1 1 1 1 x x x x x x

0 1 1 1 1 0 0 0 0 1 x x x x x x

1 0 0 1 1 0 0 1 1 0 x x x x x x

1 0 1 0 1 0 1 0 1 0 x x x x x x



EXCESS-3 TO BCD CONVERTOR: LOGIC DIAGRAM:

K-Map for B3:

B3=E3 E2 +E3 E1 E0



K-Map for B2:

K-Map for B1:

B1=E1 E0



K-Map for B0:

TRUTH TABLE:

EXCESS 3 CODE BINARY CODE E3 E2 E1 E0 B3 B2 B1 B0

0 0 0 0 0 1 1 1 1 1

0 1 1 1 1 0 0 0 0 1

1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1


RESULT: Thus the design and the implementation of circuit using logic gates for arbitary function and code converters were done and the truth tables were verified.

VIVA QUESTIONS:

1. Draw the circuit diagram for Boolean function

2. Draw the circuit diagram for Truth table

3. Explain the working procedure.

4. What is K-Map

5. What are the characteristics of Boolean function

6. Mention some application of Boolean function

7. Difference between SOP and POS

8. Draw the K-Map for the Boolean function

9. What is SOP

10. What is POS

11. Differentiate BCD & Excess 3 code

12. What is BCD?

13. What is the base for Binary?

14. How will you convert Binary to Gray?

15. What is Gray Code?

16. Give the conversion process of Excess 3 to BCD

17. What are the logic gates used in converting Gray code to Binary?

18. What is the need of code converters?

19. How will you design Code converters?

20. What is the difference between Positive and Negative logic?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM: 4-BIT BINARY ADDER


EX NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR DATE :

AIM:

To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1 2. EX-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - As required


LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR


PROCEDURE:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.


TRUTH TABLE

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1


RESULT:

Thus the 4 bit binary adder, 4 bit binary subtractor and BCD adder were designed using

logic gates and their truth table was verified.

VIVA QUESTIONS 1. Distinguish between Full Adder , 4 bit Binary adder 2. What is BCD? 3. How many pins are there in Ic 7483? 4. What is the need of Binary adder? 5. What is a Carry Look ahead Adder? 6. Is IC 7483 can be used for Adders and Subtractors? How? 7. Give the difference between a Half adder and a Parallel adder 8. How multipliers are utilized using adders 9. What is 4 bit subtraction? 10. Compare BCD adder , Binary adder

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


EVEN PARITY GENERATOR CIRCUIT

4

56

74LS861

23

74LS86

EVEN PARITY BIT(P) GENERATOR X Y Z EVEN PARITY BIT(P) 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

PARITY GENERATOR/CHECKER (74LS180)

PARITY GENERATOR/CHECKER (74LS180)- PIN DETAILS

X Y Z

P

I6 I7

PE PO ∑E

∑O

GND

Vcc

I5 I4 I3 I2 I1 I0

74LS180


EX NO.: DESIGN AND IMPLEMENTATION OF PARITY DATE: GENERATOR AND CHECKER

AIM: To design a combinational logic circuit for parity bit generator and parity bit receiver circuit APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION

QTY.

1. EX-OR GATE IC 7486 1 2. 9-bit PARITY

GENERATOR/CHECKER IC 74180 1

3. IC TRAINER KIT - 1 4. PATCH CORDS - As required

PROCEDURE 1. Reduce PARITY GENERATOR/CHECKER functions using Theorems or

Karnaugh-MAP method 2. Construct the Combinational Logic Circuit for reduced resulting function using

corresponding Gates ICs and MSI Devices 3. For various combinations of input verify the output and tabulate the result


DESIGN EVEN PARITY GENERATOR EVEN PARITY CHECKER CIRCUIT

9

108

74LS86

4

56

74LS86

1

23

74LS86

EVEN PARITY BIT(P) CHECKER X Y Z P C ERROR

0 0 0 0 0 No

0 0 0 1 1 YES

0 0 1 0 1 YES

0 0 1 1 0 No

0 1 0 0 1 YES

0 1 0 1 0 No

0 1 1 0 0 No

0 1 1 1 1 YES

1 0 0 0 1 YES

1 0 0 1 0 No

1 0 1 0 0 No

1 0 1 1 1 YES

1 1 0 0 0 No

1 1 0 1 1 YES

1 1 1 0 1 YES

1 1 1 1 0 No

X EVEN PARITY GENERATOR

Z

Y MESSAGE PARITY BIT (P)

X Y

Z P

C


EVEN PARITY GENERATOR

From the truth table the expression for P is

P = X’Y’Z + X’YZ’ + XY’Z’ + XYZ = Z [X’Y’+ XY] + Z’ [X’Y + XY’] = Z [X’Y + XY’]’ + Z’ [X’Y + XY’]

ZYXP EVEN PARITY CHECKER

From the truth table the expression for C parity error checks can be derived as,

pxyzpzxyzpyxpzyxyzpxpzyxpzyxpzyxC pxyzpzxyzpyxpzyxyzpxpzyxpzyxpzyx

zp)pz)(yxyx()pzpzxy)(yx( PZXC Y

FUNCTION TABLE

CHECK BIT (C)

X

EVEN PARITY GENERATOR

Z

Y MESSAGE

P



RESULT:

Thus the parity checker and parity generator circuit were designed using logic

gates and their truth table was verified.

VIVA QUESTIONS

1. What is Parity? 2. Where Parity is necessary? 3. How parity is generated? 4. Where will we use parity checkers? 5. What is odd parity? 6. Give an example for an even parity? 7. How many errors can be corrected using a parity checker? 8. Why parity is used in digital circuits rather than analog circuits? 9. Can the IC 74180 work as parity generator and checker? 10. What is the disadvantage of parity?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR

K MAP


EX NO.: DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR DATE: AIM:

To design and implement

(i) 2 – bit magnitude comparator using basic gates.

(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1. AND GATE IC 7408 2 2. X-OR GATE IC 7486 1 3. OR GATE IC 7432 1 4. NOT GATE IC 7404 1 5. 4-BIT MAGNITUDE

COMPARATOR IC 7485 2

6. IC TRAINER KIT - 1 7. PATCH CORDS - As required


TRUTH TABLE:

A1 A0 B1 B0 A > B A = B A < B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0


A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

x3 x2 x1 x0

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.


PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1


RESULT:

Thus the magnitude comparator circuit was designed using logic gates and their

truth table was verified.

VIVA QUESTIONS

1. What is the need of Comparators? 2. What is Magnitude Comparator? 3. How magnitude Comparators are achieved using gates? 4. What is 8 bit Magnitude Comparator? 5. What is the use of IC 7485? 6. What is the pin no 8 of IC 7485? 7. Is 7485 is a 14 pin IC? 8. Which gate is used as a single bit Comparator? 9. What is advantage of Ex-Nor gate?

10. If A=1,B=0 What is the result in Magnitude comparator?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0


EX NO. : DESIGN AND IMPLEMENTATION OF MULTIPLEXER DATE:

AND DEMULTIPLEXER

AIM: To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1. 3 I/P AND GATE IC 7411 2 2. OR GATE IC 7432 1 3. NOT GATE IC 7404 1 2. IC TRAINER KIT - 1 3. PATCH CORDS - As required

PROCEDURE:





CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3


BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0


LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1


RESULT: Thus the multiplexer and de-multiplexer circuit was designed using logic gates and their truth table was verified.

VIVA QUESTIONS

1. What is Mux? 2. What is the use of select lines? 3. What is a Demultiplexer? 4. Differentiate 2:1, 4:1 Multiplexer 5. What is called as Distributor? Why? 6. What is the use of IC 74150? 7. Why Mux is called as selector? 8. What is the use of IC 74154? 9. Will you design 8:1 Multiplexor using logic gates? 10. Why 74154 is used rather than logic gates?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1


EX NO. : DESIGN AND IMPLEMENTATION OF SHIFT REGISTER DATE:

AIM: To design and implement

(i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out

APPARATUS REQUIRED:

S No. COMPONENT SPECIFICATION QTY. 1. D FLIP FLOP IC 7474 2 2. OR GATE IC 7432 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - As required

PROCEDURE:





LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA

OUTPUT

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:



TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0


RESULT:

Thus the various shift registers were designed successfully using flip-flops and

their truth tables were verified successfully.

VIVA QUESTIONS

1. What is a Register? 2. What is a Shift Register? 3. What is the basic device used in a Shift register? 4. What is the of Shift registers? 5. Give one application of shift register 6. What is SISO shift register? What is the IC used for it? 7. What is a Ring Counter? 8. What is a Bi-directional Shift register? 9. What is a PISO shift register? 10. Which is faster? A PISO,PIPO

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


4-BIT ASYNCHRONOUS DOWN COUNTER:

TRUTH TABLE 4-BIT ASYNCHRONOUS DOWN COUNTER:

CLK INPUT Q3 Q2 Q1 Q0 (1) 1 1 1 1 (1) 1 1 1 0 (1) 1 1 0 1 (1) 1 1 0 0 (1) 1 0 1 1 (1) 1 0 1 0 (1) 1 0 0 1 (1) 1 0 0 0 (1) 0 1 1 1 (1) 0 1 1 0 (1) 0 1 0 1 (1) 0 1 0 0 (1) 0 0 1 1 (1) 0 0 1 0 (1) 0 0 0 1 (1) 0 0 0 0

(1)-positive edge input


EX NO. : DESIGN AND IMPLEMENTATION OF SYNCHRONOUS DATE:

AND ASYNCHRONOUS COUNTERS

AIM: To design and implement 4 bit synchronous and asynchronous counter using logic

gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 1 2. NAND GATE IC 7400 1 3. AND GATE IC 7408 1 6. IC TRAINER KIT - 1 7. PATCH CORDS - as required

PROCEDURE

COUNTERS 1. Construct the circuit as in circuit diagram. 2. Output of the mono pulse generator is given to clk input of Flip-Flop and set the

pulse generator to manual mode. 3. To verify the count sequence, apply manually not less then 7/8 pulses and verify

the truth table.


DESIGN PROCEDURE FOR COUNTERS 1. COUNTER WITH NON-BINARY SEQUENCE

STEP 1 (STATE DIAGRAM) STEP 2 EXCITATION TABLE Note: From this excitation table the logic circuit is designed using karnaugh map

Present State Next State Flip-flop excitation A B C A B C Ja Ka Jb Kb Jc Kc 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0 1 1 1 X X 1 0 X 1 0 0 1 0 1 X 0 0 X 1 X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 0 0 0 X 1 X 1 0 X

STEP 3 CIRCUIT DIAGRAM

7476

4

1

16

15

14

J

CLK

K

Q

Q

CLK

7476

4

1

16

15

14

J

CLK

K

Q

Q

CB

7476

9

6

12

11J

CLK

K QB

Q

A

logic 1


4-BIT SYNCHRONOUS UP COUNTER:

TRUTH TABLE 4-BIT SYNCHRONOUS UP COUNTER:

CLK INPUT Q3 Q2 Q1 Q0 (1) 0 0 0 0 (1) 0 0 0 1 (1) 0 0 1 0 (1) 0 0 1 1 (1) 0 1 0 0 (1) 0 1 0 1 (1) 0 1 1 0 (1) 0 1 1 1 (1) 1 0 0 0 (1) 1 0 0 1 (1) 1 0 1 0 (1) 1 0 1 1 (1) 1 1 0 0 (1) 1 1 0 1 (1) 1 1 1 0 (1) 1 1 1 1 (1)-positive edge input


(MOD-10) SYNCHRONOUS UP COUNTER:

TRUTH TABLE - (MOD-10) SYNCHRONOUS UP COUNTER:

CLK INPUT Q3 Q2 Q1 Q0 (1) 0 0 0 0 (1) 0 0 0 1 (1) 0 0 1 0 (1) 0 0 1 1 (1) 0 1 0 0 (1) 0 1 0 1 (1) 0 1 1 0 (1) 0 1 1 1 (1) 1 0 0 0 (1) 1 0 0 1 (1)-positive edge input


RESULT:

Thus, the 4-bit Synchronous and Asynchronous counters were designed,

implemented using logic gates.

VIVA QUESTIONS 1. What is counter? 2. Why do we need counters? How are counters made? 3. What is synchronous counter? 4. What is the difference between synchronous and asynchronous counter? 5. What advantages do synchronous counters have over asynchronous counter? 6. The combinational element of a counter can be made with 7. What are the applications of synchronous counter? 8. Which flipflop is used to made synchronous counter? 9. What is flipflop? 10. What are the different types of synchronous counter? 11. What is a Counter? 12. What is Up/Down counter? 13. What are the applications of Flipflops? 14. What is the use of a Clock signal? 15. What are the types of Triggering methods in F/Fs 16. Compare Synchronous, Asynchronous counters? 17. What is State diagram? 18. What is the disadvantage of Synchronous counter? 19. How will you design a synchronous counter? 20. What are the types of Flipflops?

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5



EX NO. : SIMULATION OF COMBINATIONAL CIRCUIT USING HDL DATE:

AIM: To design and simulate (i) Adder and Subtractor (ii) Multiplexer and De-multiplexer

TOOLS REQUIRED

XILINX Software

Modelsim simulator

PROCEDURE

Write and draw the Digital logic system. Write the Verilog HDL code for above system. Open project navigator Select File New project Give the file name and press next Give the entity name and select Verilog HDL module and press next Give the inputs and outputs and specify input or output or in-out and select next Then give finish and the entity and the architecture details appear by itself Enter the Verilog HDL code in after architecture. Check the syntax and simulate the above Verilog HDL code (using ModelSim or

Xilinx) and verify the output waveform as obtained. Verify the graph with the truth table

PROGRAM: HALF ADDER

module half_adder(in_x, in_y, out_sum, out_carry);

input in_x;

input in_y;

output out_sum;

output out_carry;

xor (out_sum, in_x, in_y);

and (out_carry, in_x, in_y);

end module;


FULL ADDER

module full_adder(x, y, z, sum, carry);

input x;

input y;

output sum;

output carry;

wire a, b, c;

xor (sum, x, y, z);

and (a, x, y);

and (b, y, z);

and (c, z, x);

or (carry, a, b, c);

end module;

HALF SUBTRACTOR

module half_subtractor (x, y, diff, borrow);

input x;

input y;

output diff;

output borrow;

wire ybar;

not (ybar, y);

xor (diff, x, y);

and (borrow, x, ybar);

end module;


FULL SUBRACTOR module fullsub(a, b, c, borrow, dif); input a; input b; input c; output borrow; output dif; wire d,e,f; xor(dif,a,b,c); and(d,~a,b); and(e,b,c); and(f,~a,c); or(borrow,d,e,f); endmodule

MULTIPLEXER module mux_4 to 1 ( y, I1, I2, I3, I4, S0, S1);

input I1, I2, I3, I4, S0, S1;

output y;

wire S1bar, S0bar, a, b, c, d;

not (S1bar, S1);

not (S0bar, S0);

and (a, S1bar, S0bar, I1);

and (b, S1bar, S0, I2);

and (c, S1, S0bar, I3);

and (d, S1, S0, I4);

or (y, a, b, c, d);

end module;


DE-MULTIPLEXER module mux_4 to 1 ( Y1, Y2, Y3, Y4, I, S0, S1);

input I, S0, S1;

output Y1, Y2, Y3, Y4;

wire S1bar, S0bar;

not (S1bar, S1);

not (S0bar, S0);

and (Y1, S1bar, S0bar, I);

and (Y2, S1bar, S0, I);

and (Y3, S1, S0bar, I);

and (Y4, S1, S0, I);

or (y, a, b, c, d);

end module;

RESULT:

Thus the simulation of adders, subtractors, multiplexer and demultiplexer using

XILINX software were done and simulated their circuit using modelsim simulator.

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5


EXNO. : SIMULATION OF SEQUENTIAL CIRCUITS USING HDL DATE:

AIM: To design and simulate (i) Ripple counter (ii) Shift registers

TOOLS REQUIRED

XILINX Software

Modelsim simulator

PROCEDURE

Write and draw the Digital logic system. Write the Verilog HDL code for above system. Open project navigator Select File New project Give the file name and press next Give the entity name and select Verilog HDL module and press next Give the inputs and outputs and specify input or output or in-out and select next Then give finish and the entity and the architecture details appear by itself Enter the Verilog HDL code in after architecture. Check the syntax and simulate the above Verilog HDL code (using ModelSim or

Xilinx) and verify the output waveform as obtained. Verify the graph with the truth table


PROGRAM

RIPPLE COUNTER module counter (count, load, in, clk, clr, a, c);

input count, load, clk, clr; input [3:0] in; output c; output [3:0] a; reg [3:0] a; assign c = count & ~load & (a = = 4’b1111); always @ (posedge CLK or negedge clr) if (~clr) A = 4’b0000; else if (load) a = in; else if (count) a = a + 1’b1; else a = a;

end module; SISO SHIFT REGISTER module shift (clk, SE, SI, SO);

input SE, SI; output SO; reg [3:0] temp; always @ (posedge clk) begin if (SE) begin temp = temp << 1; temp[0] = SI; end; begin assign SO = temp [3];

end module;


SIPO SHIFT REGISTER module shift (clk, SE, SI, PO);

input SE, SI; output PO [3:0]; reg [3:0] temp; always @ (posedge clk) begin if (SE) begin temp = {temp [2:0], SI}; end; begin assign PO = temp;

end module; RESULT:

Thus the simulation of ripple counter, shift registers using XILINX software were

done and simulated their circuit using modelsim simulator.

DEPT OF ECE

PERFORMANCE 2

OBSERVATION 2

VIVA 1

TOTAL 5

Documents

Digital Lab Manual