Digital modules at ETH

||IPA – Institute for Particle Physics and Astrophysics

Malte Backhaus, Vasilije Perovic, Branislav Ristic, Gianluca Vagli

Digital modules at ETH

13/05/2019Malte Backhaus 1


Both faces loaded with modules no possibilities for service routing on

back-side / access to module

Need to route supply current and return

current on ladder front-side from module to

module

challenging connection

high current density

need one “power-in” and one “power-out”

connection on each side of the module

signal cable connection independent

from power connection

Keep quick replace/repair option

Replacement without damage to structure

or neighbouring modules

Avoid permanent glueing of modules

to support if possible


Modules for the CMS barrel


Conceptional view of chain connection


center

to services

||IPA – Institute for Particle Physics and Astrophysics 13/05/2019Malte Backhaus 4

HDI Requirements

Clearance driven by wire-bond pad frame

Single row, no fanout, >50um wide pads

ROC: 100um pitch

Chose 60um wide pads with 40um clearance

10um copper thickness and ENIG/ENEPIG gold-plating possible with larger clearance

High voltage design

More challenging due to distribution from module to module

Lines with large clearances etc.

Supply current distribution

Up to 8A in Iin and also Iret on final modules, ~1/2 on RD53 modules (on ~1/2 area)

Low as possible resistance difference between chips in parallel

Need a plane on stable potential for shielding + return current routing on the module (TBPX)

Use Bottom Layer as “local module GND” plane

Use Top Layer as Iin plane

Use middle plane for return current routing

Radiation tolerance

Activation

Glue delamination

To be validated


HDI layer stack

Two major challenges:

Impedance and DC-resistance of eLink routing

Power dissipation in supply current and return current routing (of serial powering chain)

Use a solid copper plane for return current routing „closest possibility to a GND plane“

improved power dissipation of return current

crossing of signal lines (down-link) on bottom plane, still solid copper plane shielding the eLinks

Input current to chips on top layer plane

Output current (input to next module) on bottom plane


Status Built seven functional digital modules (“S0”, “S1”, “S3”, “S4”, “S5”, “S6”, “S7”)

Three modules with silicon slab glued on top of 4 ROCs (S0, S1, S3)

S0 and S1 with silicone glue

curing problems, HDI bending during bonding

S3 with epoxy glue (UHU EF310)

no bonding problems

Four modules without silicon slab (S4, S5, S6, S7) HDI glued directly on top of the HDI

Used epoxy glue (UHU EF310)

no bonding problems

started to do systematic pull test on dedicated wires (HDI to ROCs!)

S4: manual glue application

worked well, but very labor intensive

>S5: glue application with stamp

worked well with a rubber stamp and 200um deep glue bath (several other tried)

Typical failures:

“Wire bond hack fails”

ROC fully functional, but analog injections fail (no analog/threshold/noise/tuning)

about ¼ ROCs (one per module)

ShuntLDOs don’t power-up / power-up too late

typically one or two SLDOs per module

what’s the observed yield of this failure mode on SCCs?

always different LDOs on different chips

no HDI design issue, no wire bond order feature

S4 + S6 fully operational!


Test setup


Test results: HDI

Thermal image vs. simulation

High voltage stress test(IV-curve on six bare HDIs)

High voltage resistance:

Measured IV up to 1kV as well as further spark

and stress tests

no issue observed (D4 cured after bake-out)

Power dissipation:

~600mW, mostly in the pigtail.

Good agreement with power simulations (ITA)

Current sharing between chips:

~20mV voltage drop variation between chips at

5A

~1.5% of input voltage


Wire bonding

Small pads on HDI:

• No issues observed when placement of bond

foot is good

• Exact foot placement needed on small

HDI pads needed, otherwise bond foot

falls off to one side.


Performed pull tests on spare bonds

HDI ROC (spare pads)

(labelled with “PT” on HDI)

Blue module (S4):

High pull force: mean 12.1g, sigma 1.3g, min. 9.5g

All wires break at heel on HDI

no lift offs

Red module (S5):

Lower pull force: mean 7.7g, sigma 2g, min. 4.5g

Most wires have lift off on HDI

HDI issue

HDI was quickly “re-cleaned” after glueing trials

with stamp


Pull tests


Results: SLDOs

Measure first SLDO VI curves for all ROCs

Module impedance follows closely the

expected Impedance setting


Results: SLDOs

Measure first SLDO VI curves for all ROCs

Module impedance follows closely the

expected Impedance setting

Measurement of Vin close to each chip

voltage drop mismatch on HDI:

~50mV resistance difference ~12.5 mΩ


Digital scan always

good if LDOs working

Initially we never saw analog

injctions, but did see noise hits at

low threshold


Results: digital scan on S6


Reason for missing analog hits


Vref-ADC fix Small pads on HDI:

• No issues observed when placement is good

• Exact foot placement needed on small

HDI pads needed, otherwise bond foot

falls off to one side.


Results: S5, ROC0


Results: Noise

All pixels in LinFE on all

ROCs of all Modules!

Nice Gaussian distribution

no geographical noise

difference on HDI


Chain assembly

• Started to assemble and operate a chain of 2x2 RD53A modules

Today 3 modules in operation

• Saphire plates for electrical insulation

• Successive operation of modules to date


Chain powering

Return path

Vin Module 1

Vin Module 2Vin Module 3


Noise in chain

noise single – noise in chain [e]

• Results from modules in chain similar with respect to single module operation

• No re-tuning done here, but temperature increased due to triple power consumption

• Marginal noise shift seen, but mean threshold shift.

• Noise shift disappears after re-tuning.


Summary of modules with HDI V1.0

No difference in chip behavior (powering, threshold, noise) observed when operated on

CMS HDI prototypes

Revised 2x2 chip HDI (next slides)

Designed 1x2 chip HDI based on revised version

Both submitted for production

Chip SN

Modul / HDI ROC0 ROC1 ROC2 ROC3 Functionality Problems

S0 053B 054B 056B 055BROC1, ROC2, ROC3 working well ROC0 communication ok, but damaged during debugging

S1 053A 0517 058B 057B ROC2, ROC3 working wellROC0: digital SLDO not working, analog ok. Disconnected Vin of ROC1 to avoid overheating

S2 HDI S2 not used

S3 054C 055C 057C 056CROC1, ROC2 all good, ROC3 only digital hits

ROC0: digital SLDO not working, analog ok. No communication to ROC0

S4 0374 0376 0377 0375 all ROCs working well None so far

S5 0528 0538 0558 0548ROC0 working well, ROC3 only digital hits ROC1 digital LDO fails, ROC2 analog LDO fails

S6 035B 036C 036B 035C all ROCs working well None so far

S7 0526 0536 0516 05A7 untested


Improvements in HDI design

Old design has 0.5mm diameter alignment holes

hard to purchase and tool 0.5mm alignment pins

Moved aligment holes out of active pigtail area

could increase diameter to 1mm

V2.0V1.0

Measured SLDO VI-curves with needles on the SMD

capacitors for each module

very laborous

Added voltage test pads for SLDO outputs and

module GND

facilitate SLDO measurements using a simple

“needle card”

Exact layout of RD53A module sensors known now

adjusted dimensions of HDI

Increased distance of pads and internal planes to

border

better high voltage resistance

Added overhang of 100um in wire bond sides

protection against glue coverage of HDI pads

increase of spark protection

Careful revision of locations with increased current

density in simulations

reduction of power consumption by ≥10%


No difference in chip behavior (powering, threshold, noise) observed when operated on

CMS HDI prototypes

Revised 2x2 chip HDI (next slides)

Designed 1x2 chip HDI based on revised version

Both submitted for production


Documents

Digital modules at ETH