Digital System Design lectures

8/17/2019 Digital System Design lectures

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By Dr.Oday A.L.A Ridha 1

Digital System DesignDr. Oday A.L.A Ridha

University of Baghdad 2010

Syllabus

-Digital system in general;

-Simplification of logic circuits;

-Combinational circuit design;

-Design using programmable logic circuits such as ROM, PLA, PAL and GAL

-Design of synchronous sequential circuit;

-Algorithmic state machine;

-Design of asynchronous sequential circuit;-Microprocessor and microcontroller based systems.

References

1. M. Morris Mano, Digital design, Prentice/ Hall International, 1984.

2. Fredreck J. Hill and Gerald R. Peterson, Digital logic and microprocessors.

3. Malvino, Digital principles and applications.

4. Tony R. Kuphaldt, Lessons In Electric Circuits, Volume IV “Digital”, 2005.

5. Others

Digital System

Digital design is concerned with the design of digital electronic circuits. The subject is

also known by other names such as logic design, switching circuits, digital logic, and

digital systems. Digital circuits are employed in the design of systems of digital

computers, electronic calculators, digital control devices, digital communication

equipments, and many other applications that required electronic digital hardware.

Basic elements of the digital systems

The basic elements of any digital system are logic gates. These gates are:

1- NOT gate (inverter)Truth table

X Z

0 1

1 0ZX

X Z =


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2- AND gate (multiplication)

3- OR gate (sum)

Positive and negative logic

There are two choices for logic-level assignment. Choosing the high-level H to

represent logic-1 defines a positive logic system. Choosing the low-level L to represent

logic-1 defines a negative logic system.

Truth table

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

Truth table

X Y Z

0 0 00 1 1

1 0 1

1 1 1

x

y z

Y X Z ⋅=

x

yz

Y X Z +=


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Example:

a) if we use positive logic system

b) if we use negative logic system

Truth table

X Y Z

L L H

L H H

H L H

H H L

Truth table

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

Truth table

X Y Z

1 1 0

1 0 0

0 1 0

0 0 1

1

0

H

L

Signal

value

Logic

value

a) Positive logic

0

1

H

L

Signal

value

Logic

value

b) Negative logic

?X

Y

Z

x

y z

x

yz

NAND gate

NOR gate


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Simplification of logic circuits

Logic circuits can be simplified using one or combination of the following methods

1) Boolean algebra

2) Karnaugh mapping

3) Tabular method

Boolean algebra

Like "normal" algebra, Boolean algebra uses alphabetical letters to denote

variables. Unlike "normal" algebra, though, Boolean variables are always CAPITALletters, never lower-case. Because they are allowed to possess only one of two possible

values, either 1 or 0, each and every variable has a complement: the opposite of its value.

For example, if variable "A" has a value of 0, then the complement of A has a value of 1.

Boolean notation uses a bar above the variable character to denote complementation.

Basic Boolean identities:

a) Additive (equivalent to OR logic function)

1) A A =+ 0

2) 11 =+ A

3) 1=+ A A

4) A A A =+

b) Multiplicative (equivalent to AND logic function)

1) A A =⋅1

2) 00 =⋅ A

3) A A A =⋅

4) 0=⋅ A A

c)

Double complement

A A =

Basic Boolean algebraic properties:

1) A B B A +=+ (commutative property of addition)

2) A B B A ⋅=⋅ (commutative property of multiplication)

3) C B AC B A ++=++ )()( (associative property of addition)

4) C B AC B A )()( ⋅=⋅ (associative property of multiplication)


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5) C A B AC B A ⋅+⋅=+ )( (distributive property)

Boolean rules are

1) A AB A =+

2) B A B A A +=+ 3) BC AC A B A +=++ ))((

DeMorgan's Theorems

A mathematician named DeMorgan developed a pair of important rules regarding

group complementation in Boolean algebra.

DeMorgan's theorem may be thought of in terms of breaking a long bar symbol.When a long bar is broken, the operation directly underneath the break changes from

addition to multiplication, or vice versa, and the broken bar pieces remain over the

individual variables.

Boolean rules for simplification

Boolean algebra finds its most practical use in the simplification of logic circuits. If

we translate a logic circuit's function into symbolic (Boolean) form, and apply certain

algebraic rules to the resulting equation to reduce the number of terms and/or arithmetic

operations, the simplified equation may be translated back into circuit form for a logic

circuit performing the same function with fewer components. If equivalent function may

be achieved with fewer components, the result will be increased reliability and decreased

cost of manufacture.


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Steps for simplifying logic circuits

Step 1: Convert the logic circuit to a Boolean expression. Label each gate output with aBoolean sub-expression corresponding to the gates' input signals, until a final expression

is reached at the last gate;

Step 2 : simplify Boolean expression, obtained from first step, using basic rules and

properties of the Boolean algebra;

Step 3: convert simplified Boolean expression to a logic circuit. Evaluate the expression

using standard order of operations: multiplication before addition, and operations within

parentheses before anything else.

Example: simplify the following logic circuit

Solution:

Step 1:

a)


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b)

c)

Step 2:


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Step 3:


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By Dr Oday Al.A Ridha 12

Minterms (standard products) vs. maxterms (standard sums)

For a logic circuit with n input variables there are n2 different

combinations (numbers) of the input variables. If the input variables of thesecombinations are combined by an AND operation, they are called minterms

or standard products. For the output, minterm is a combination of the input

variables that produces a 1 at the output. Each variable in the minterm is

unprimed if the corresponding bit in the equivalent binary number is a 1 and

prime if it is a 0. In the other words, minterm is an AND term of the n

variables, with each variable being unprimed if the corresponding bit in the

equivalent binary number is a 1 and prime if it is a 0.

On the other hand, If the input variables of these combinations are

combined by an OR operation, they are called maxterms or standard sums. For the output, maxterm is a combination of the input variables that

produces a 0 at the output. Each variable in the maxterm is primed if the

corresponding bit in the equivalent binary number is a 1 and unprimed if it is

a 0.

∑ (sum) and Π (product) notation

Any truth table or a Boolean equation description of unsimplified

logic can be expressed by summing minterms m∑ . Sigma indicates sum

and lower case “ m ” indicates minterms.

Equivalent

binary number

Minterms Maxterms

term designation term designation

0 0 0 Z Y X ⋅⋅ m0 Z Y X ++ M0 0 0 1 Z Y X ⋅⋅ m1 Z Y X ++ M1

0 1 0 Z Y X ⋅⋅ m2 Z Y X ++ M2

0 1 1 Z Y X ⋅⋅ m3 Z Y X ++ M3

1 0 0 Z Y X ⋅⋅ m4 Z Y X ++ M4

1 0 1 Z Y X ⋅⋅ m5 Z Y X ++ M5

1 1 0 Z Y X ⋅⋅ m6 Z Y X ++ M6

1 1 1 Z Y X ⋅⋅ m7 Z Y X ++ M7


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Example

∑== ),(),( 30 mm B AF Z

∑== )3,0(),( B AF Z

B A B A B AF Z ⋅+⋅== ),( …….… (a)

It is also can express any truth table or a Boolean equation description

of unsimplified logic by multiplying maxterms (∏ M ). Pi indicates product

and upper case “ M ” indicates maxterms. For the same above example, Z

can be expressed by using maxterms.

∏== ),(),( 21 M M B AF Z

∏== )2,1(),( B AF Z

)()(),( B A B A B AF Z +⋅+== ……………………………………………….…………. (b)

Exercise Show that expressions (a) and (b) in the above example areequivalents.

Karnaugh map

The Karnaugh map, like Boolean algebra, is a simplification tool

applicable to digital logic. The Karnaugh Map will simplify logic faster and

more easily in most cases. Boolean simplification is actually faster than the

Karnaugh map for a task involving two or fewer Boolean variables. It is still

quite usable at three variables, but a bit slower. At four input variables,Boolean algebra becomes tedious. Karnaugh maps are both faster and easier.

Karnaugh maps work well for up to six input variables, are usable for up to

eight variables. For more than six to eight variables, simplification should be

by CAD (computer automated design).

The outputs of a truth table correspond on a one-to-one basis to Karnaugh

map (simply k-map) entries.

For two input variables A and B k-map is formed as follow:

Starting at the top of the truth table, the A=0, B=0 inputs produce an

outputα . Note that this same output α is found in the Karnaugh map at the

A=0, B=0 cell address, upper left corner of K-map where the A=0 row and

No.Inputs Output

A B Z

0 0 0 1

1 0 1 0

2 1 0 0

3 1 1 1


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B=0 column intersect. The other truth table outputs δ χ β ,, from inputs

AB=01, 10, 11 are found at corresponding K-map locations.

Procedure for simplification using k-map

a) Divide input variables into two groups, such that the difference between

the numbers of variables in each group doesn’t exceed one.

b) Draw two dimensions grid.

c)

Arrange corresponding binary numbers of the input variables

combinations of the first and second groups on the top and left sides of

the grid, respectively, such that the difference between any adjacent

numbers is in only one digit (variable). In other words, corresponding

binary number of input variables must be arranged on the top and leftsides of the grid as gray code.

d)

Identify the minterm (product term) term to be mapped.

e)

Write the corresponding binary numeric value.

f) Use binary value as an address to place a 1 in the K-map.

g)

Repeat steps (d-f) for other minterms.

h)

Form largest groups of 1s possible covering all minterms. Groups must

be a power of 2.

i)

Write binary numeric value for groups.

j) Convert binary value to a product term.

k)

Repeat steps (i-j) for other groups. Each group yields a product term

within a Sum-Of-Products.


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Examples

∑= )15,8,2,0(out

∑= )15,13,12,9,8,5,4,1,0(out

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 10001 DC B A 0

0010 DC B A 1

0011 CD B A 0

0100 DC B A 0

0101 DC B A 0

0110 D BC A 0

0111 BCD A 0

1000 DC B A 1

1001

DC B A 0

1010 DC B A 0

1011 CD B A 0

1100 DC AB 0

1101 DC AB 0

1110 D ABC 0

1111 ABCD 1

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 1

0001 DC B A 1

0010 DC B A 0

0011 CD B A 0

0100 DC B A 1

0101 DC B A 1

0110 D BC A 0

0111 BCD A 0

1000 DC B A

1

1001 DC B A 1

1010 DC B A 0

1011 CD B A 0

1100 DC AB 1

1101 DC AB 1

1110 D ABC 0

1111 ABCD 1


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∑= )15,14,13,12,11,7,3(out

Binary

number

Inputs

ABCD

Output

Z

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 1 1000 DC B A 1

0001 DC B A 1 1001 DC B A 00010 DC B A 1010 DC B A 1

0011 CD B A 1011 CD B A 0

0100 DC B A 1100 DC AB 0

0101 DC B A 1 1101 DC AB 0

0110 D BC A 1110 D ABC 1

0111 BCD A 1 1111 ABCD 1

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 0

0001 DC B A 0

0010 DC B A 0

0011 CD B A 1

0100 DC B A 0

0101 DC B A 0

0110 D BC A 0

0111

BCD A 1

1000 DC B A 0

1001 DC B A 0

1010 DC B A 0

1011 CD B A 1

1100 DC AB 1

1101 DC AB 1

1110 D ABC 1

1111 ABCD 1


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∑= )15,13,12,7,5,4,3,1,0(out

∑= )11,10,9,8,3,2,1,0(out

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 1

0001 DC B A 10010 DC B A 0

0011 CD B A 1

0100 DC B A 1

0101 DC B A 1

0110 D BC A 0

0111 BCD A 1

1000 DC B A 0

1001 DC B A 0

1010 DC B A 0

1011 CD B A 0

1100 DC AB 1

1101 DC AB 1

1110 D ABC 0

1111 ABCD 1

Binary

number

Inputs

ABCD

Output

Z

0000 DC B A 10001 DC B A 1

0010 DC B A 1

0011 CD B A 1

0100 DC B A 0

0101 DC B A 0

0110 D BC A 0

0111 BCD A 0

1000 DC B A 1

1001 DC B A

1

1010 DC B A 1

1011 CD B A 1

1100 DC AB 0

1101 DC AB 0

1110 D ABC 0

1111 ABCD 0


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Don't care cells in the Karnaugh map

Up to this point we have considered logic reduction problems where the

input conditions were completely specified. That is, a 3-variable truth tableor Karnaugh map had 2

n = 2

3 or 8-entries, a full table or map. It is not

always necessary to fill in the complete truth table for some real-world

problems. We may have a choice to not fill in the complete table. For

example, when dealing with BCD (Binary Coded Decimal) numbers

encoded as four bits, we may not care about any codes above the BCD range

of (0, 1, 2...9). The 4-bit binary codes for the hexadecimal numbers (Ah, Bh,

Ch, Dh, Eh, Fh) are not valid BCD codes. Thus, we do not have to fill in

those codes at the end of a truth table, or K-map, if we do not care to. We

would not normally care to fill in those codes because those codes (1010,

1011, 1100, 1101, 1110, 1111) will never exist as long as we are dealing

only with BCD encoded numbers. These six invalid codes are don't cares as

far as we are concerned. That is, we do not care what output our logic circuit

produces for these don't cares. Don't cares in a Karnaugh map, or truth table,

may be either 1s or 0s, as long as we don't care what the output is for an

input condition we never expect to see. We plot these cells with an asterisk,

*, among the normal 1s and 0s. When forming groups of cells, treat the don't

care cell as either a 1 or a 0, or ignore the don't cares. This is helpful if it

allows us to form a larger group than would otherwise be possible without

the don't cares. There is no requirement to group all or any of the don't cares.Only use them in a group if it simplifies the logic.

ExampleDesign a lamp logic circuits that drives five lamps (L1-L5), as shown

in the figure below. These lights work as follows:

No lamps will light for no motion of the bicycle. As speed increases, the

lower lamp, L1 lights, then L1 and L2, then, L1, L2, and L3, until all lamps

light at the highest speed. Once all the lamps illuminate, no further increase

in speed will have any effect on the display. A small DC generator coupled

to the bicycle tire outputs a voltage proportional to speed. It drives a


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tachometer board which limits the voltage at the high end of speed where all

lamps light. No further increase in speed can increase the voltage beyond

this level. This is crucial because the downstream A to D (Analog to Digital)

converter puts out a 3-bit code, ABC, 2

3

or 8-codes, but we only have fivelamps. A is the most significant bit, C the least significant bit. The lamp

logic needs to respond to the six codes out of the A to D. For ABC=000, no

motion, no lamps light. For the five codes (001 to 101) lamps L1, L1&L2,

L1&L2&L3, up to all lamps will light, as speed, voltage, and the A to D

code (ABC) increases. We do not care about the response to input codes

(110, 111) because these codes will never come out of the A to D due to the

limiting in the tachometer block. We need to design five logic circuits to

drive the five lamps.

Solution

A/DInputs

ABC

Output

L1 L2 L3 L4 L5

000 C B A 0 0 0 0 0

001 C B A 1 0 0 0 0

010 C B A 1 1 0 0 0

011 BC A 1 1 1 0 0100 C B A 1 1 1 1 0

101 C B A 1 1 1 1 1

110 C AB * * * * *

111 ABC * * * * *


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Larger 5 & 6-variable Karnaugh maps

We can arrange variables in 5-variable map in two ways:

1)

Using Gray code.2)

Using overlay code.


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Examples:


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Tabulation method (Quine-McCluskey)

The map method of simplification is convenient as long as the number

of input variables doesn’t exceed five or six. As the number of variablesincreases, the excessive number of squares prevents a reasonable selection of

adjacent squares. The tabulation method overcomes this difficulty. It is a

specific step-by-step procedure that is guaranteed to produce a simplified

standard-form (sum of products) expression for a function. It can be applied

to problems with many variables and has the advantage of being suitable for

machine computation, but it is tedious for human.

Tabulation method consist from two parts

Part1: find by an exhaustive search all terms that are candidate for

inclusion in the simplified function. These terms are called “ prime-

implicants”.

Part2: choose among the prime-implicants those that give an

expression with least number of literals.

Determination of prime-implicants (part 1)

Step 1: group binary number representation of according to number of

1’s contained.

Step 2: form second column. Combine any two minterms which differfrom each other by only one variable. Differed variable is replaced by a

dash. Combined minterms are marked. Process of comparison and

combination (if possible) are done between any two members of adjacent

groups.

Step 3: form third column. Again combine any two new minterms in

the second column which differ from each other by only one variable and

dash position are the same. Differed variable is replaced by a new dash.

Combined minterms are marked again.

Process of forming further columns is continued until no new

combination can be done.Step 4: prime-implicants are these terms that unmarked from the first

to the last column.

Example: simplify the following function:

∑= )15,11,10,9,8,7,6,4,1(),,,( DC B AF


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Step 1 ABCD No. Step2 Step3

1

0001 1 √ -001 (1,9) 10- - (8,9,10,11)

0100 4 √ 01-0 (4,6) 10- - (8,9,10,11)

1000 8 √ 100- (8,9) √

2

0110 6 √ 10-0 (8,10) √

1001 9 √ 011- (6,7)

1010 10 √ 10-1 (9,11) √

30111 7 √ 101- (10,11) √

1011 11 √ -111 (7,15)

4 1111 15 √ 1-11 (11,15)

For the above example prime-implicant are (-001, 01-0, 011-, -111, 1-11,

10--) or ( DC B , D B A , BC A , BCD , ACD , B A ).

=),,,( DC B AF DC B + D B A + BC A + BCD + ACD + B A

NOTE: first part of tabulation method not necessary give

minimum expression of a function, therefore we need to

progress to the second part of the method.

Selection of prime-implicants (part 2)

Sum of all prime-implicants obtained in first part of the method. In

some cases these terms can be farther reduced. To get an expression with

least literals, a selection must be done. The selection of prime-implicants

that form the minimized function is made from a prime-implicants table. In

this table, each prime-implicants is represented in a row and each minterm in

a column (Step1), as shown.

Step2: for each prime-implicants row, crosses are placed to indicate

minterms covered by this prime-implicants.

Step 3: inspect complete prime-implicants table for columns containing only

a single cross. In our example there are four minterms whose columns have

single cross: 1, 4, 8, and 10. Prime-implicants that cover minterms with

single cross in their columns are called essential prime-implicants and must

selected. A check mark is placed in the table next to the essential prime-

implicants to indicate that they have been selected. Essential prime-

implicants must be included in the final simplified expression.


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STEP 1 and 2

Terms No. 1 4 6 7 8 9 10 11 15

DC B 1,9 X X

D B A 4,6 X X

BC A 6,7 X X

BCD 7,15 X X

ACD 11,15 X X

B A 8,9,10,11 X X X X

STEP 3

Step 4: check each column whose minterms is covered by essential prime-

implicants. A check is inserted in the bottom of the columns.

Step 5: uncovered minterms must be included by selecting one or more of

prime-implicants. In our example, we have two minterms (7, 15) uncovered

and three unchecked prime-implicants ( BC A , BCD , ACD ). Selecting BCD

only will lead to covered all minterms; therefore it must be included in the

final simplified expression in addition to essential prime-implicants terms.

=),,,( DC B AF DC B + D B A + BCD + B A

Terms No. 1 4 6 7 8 9 10 11 15

√ DC B 1,9 X X

√ D B A 4,6 X X

BC A 6,7 X X

BCD 7,15 X X

ACD 11,15 X X

√ B A 8,9,10,11 X X X X


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STEP 4

STEP 5

NOTES

1) We can use decimal number instead of binary numbers

2) Tabulation method can be adopted to give a simplified expression in

product of sums. As in the map method, we have to start with the

complement of the function by taking the 0’s as the initial list of

minterms. This list contains those minterms not included in the

original function which are numerically equal to the maxterms of the

function. The tabulation process is carried out with 0’s of the function

Terms No. 1 4 6 7 8 9 10 11 15

√ DC B 1,9 X X

√ D B A 4,6 X X

BC A 6,7 X X

BCD 7,15 X X

ACD 11,15 X X

√ B A 8,9,10,11 X X X X

√ √ √ ? √ √ √ √ ?

Terms No. 1 4 6 7 8 9 10 11 15

√ DC B 1,9 X X

√ D B A 4,6 X X

BC A 6,7 X X

√ BCD 7,15 X X

ACD 11,15 X X

√ B A 8,9,10,11 X X X X

√ √ √ √ √ √ √ √ √


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and terminates with a simplified expression in sum of products of the

complement of the function. By taking the complement again, we

obtain the simplified product of sums expression.

3)

A function with don’t-care conditions can be simplified by thetabulation method after a slight modification. The don’t-care terms

are included in the list of minterms when the prime-implicants are

determined. This allows the derivation of prime-implicants with least

number of literals. The don’t-care terms are not included in the list of

minterms when prime-implicants table is set up, because don’t-care

terms do not have to be covered by the selected prime-implicants.


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Dr Oday A.L.A Ridha 29

NAND and NOR implementation

Digital circuits are more frequently construct with NAND or NOR

gates than with AND and OR gates. NAND and NOR gates are easier tofabricate with electronic components and are the basic gates used in all IC

digital logic families.

Not equivalent

OR equivalent

AND equivalent

Example: implement the following logic circuit using NAND gates only


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Solution:

Step 1:

Step 2:

Properties of exclusive OR and Equivalence

Exclusive-OR and equivalence, denoted by ⊕ and Θ , respectively.

The two operations are complements of each other. Each is

commutative and associative.

C B AC B AC B A ⊕⊕=⊕⊕=⊕⊕ )()(

An n-variable XOR expression is equal to the Boolean function with

2/2n

minterms whose equivalent binary numbers have an odd

numbers of 1’s.

An n-variable equivalence is equal to the Boolean function with 2/2n

minterms whose equivalent binary numbers have an even numbers of

0’s.

When the number of variables in a function is odd the minterms withan even number of 0’s are the same as the minterms with odd number


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of 1’s, therefore an XOR expression is equal to Equivalence

expression when both have the same odd number of variables.

C B AC B A ΘΘ=⊕⊕

When the minterms of a function with an odd number of variables

have an even number of 1’s (or equivalently, an odd number of 0’s),

the function can be expressed as the complement of either an

exclusive-OR or an equivalence expression.

C B AC B AC B A ⊕Θ=Θ⊕=′⊕⊕ )(

C B AC B AC B A Θ⊕=⊕Θ=′ΘΘ )(

Complement one of the inputs of XOR or equivalence function isequal to complement the same function. (Prove that ).

Exclusive-OR and Equivalence functions very useful in system

requiring error-detection and error-correction codes. Parity bit is a

scheme for detecting errors during transmission of binary information. A

parity bit is an extra bit included with a binary message to make the

number of 1’s either odd or even. The message included the parity bit, is

transmitted and then checked at receiving end for error.

Example: design a 3-bit odd parity generator

3-bit

message Parity bit

GeneratedPA B C

0 0 0 1

0 0 1 0

0 1 0 00 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

BC

A 00 01 11 10

0 1 1

1 1 1

C B AC B AP Θ⊕=′⊕⊕= )(


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Example: design an odd parity checker for 4-bit pattern

Parallel adder

4-bit parallel binary adder

4-bit message Check

EA B C P

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 10 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 0

1 1 1 0 01 1 1 1 1

AB

CP 00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

PC B A E ΘΘΘ=

FA4

A4 B4

S4

C4 FA1

A1 B1

S1

C1 FA2

A2 B2

S2

C2 FA3

A3 B3

S3

C3 C5


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Carry propagation

Time required to propagate a carry from C1 to Cn+1 in an n-bit parallel

adder is equal to 2n times propagation delay time of one gate.

Look-ahead Carry

The carry propagation time is a limiting factor on the speed with

which two numbers are added in parallel. There are several techniques for

reducing the carry propagation time in a parallel adder. The most widely

used technique employs the principle of look-ahead carry.

Consider the full-adder shown in the figure below. If we define two

new binary variables:

i B AP ii ⊕=

iii B AG =

S2

C3

Sn

Cn+1

HAHA

FA 1

A1 B1

C1 S1

C2

HAHA

FA 2

A2 B2

C2

HAHA

FA n

An Bn

Cn


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The output sum and carry can be expresses as:

iC PS ii ⊕=

iC PGC iii +=+1

Now we can write the Boolean function for the carry output of eachstage and substitute for each its value from the previous equations:

1112 C PGC +=

112122111222223 )( C PPGPGC PGPGC PGC ++=++=+=

11231232333334 C PPPGPPGPGC PGC +++=+=

Since the Boolean function for each output carry is expressed in sum

of products, each function can be implemented with one level of AND gates

follows by an OR gate. Note that Cn does not have to wait for Cn-1, Cn-2, ...,

and C1 to propagate; in fact, Cn is propagated at the same time as C1, and C2.

BCD adder

Is a circuit that adds two BCD digits with a possible carry from previous

stage, in parallel, and produces a sum digit also in BCD. Since each input

digit doesn’t exceed 9, the output sum cannot be greater 19, (9+9+1).

Suppose we apply two BCD digits to a 4-bit binary adder. The adder

will form the sum in binary and produce a result which may range from 0 to

19. These binary numbers are listed in the table below and are labeled by

symbols K, Z8, Z4, Z2, Z1. K is the carry, and subscripts under the letter Z

represent the weights that can be assigned to the four bits in the BCD code.

The first column in the table lists the binary sums as they appear in the

outputs of a 4-bit binary adder. The output sum of two decimal digits must

P1

G1

A1 B1

G2

A2 B2

P3A3 B3

P4

G4

A4 B4

C1

P1

P2

P3

P4

S1

S2

S3

S4

C5

C4

C3

Look-

ahead carry

generator

C5

C1

C2P2

G3


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be represented in BCD and should appear in the form listed in the second

column of the table.

Binary sum BCD sumDecimalK Z8 Z4 Z2 Z1 C S8 S4 S2 S1

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 0 0 0 1 0 0 4

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 110 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18

1 0 0 1 1 1 1 0 0 1 19

In examination the contents of the table, it is apparent that when the sum is

equal or less than 9, the corresponding BCD number is identical, andtherefore no conversion is needed. When the binary sum is greater than 9,

we obtain a nonvalid BCD representation. The addition of 6 to the binary

sum converts it to the correct BCD representation and also produces an

output carry as required.

The logic circuit that detects the necessary correction can be derived from

the table entries. It obvious that correction is needed when the binary sum

has an output carry K=1. The other six combinations from 1010 to 1111 that

need a correction have a 1 in position Z8. To distinguish them from binary

1000 and 1001 which also have a 1 in position Z8, we specify further that

either Z4 or Z2 must have a 1. The condition for a correction and an outputcarry can be expressed by the Boolean function:

2848 Z Z Z Z K C ++=

When C=1, it is necessary to add 6 to the binary sum and provide an output

carry for next stage.


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Magnitude Comparator

The comparison of two numbers is an operation that determines if one

number is greater than, less than, or equal to the other number. A magnitude

comparator is a combinational circuit that compares two numbers, A and B,and determines their relative magnitude. The outcome of the comparison is

specified by three binary variables that indicate whether A>B, A=B, or A

00123112322333)( B A x x x B A x x B A x B A B A ′+′+′+′=<

Exercise: draw the logic circuit of 3-bit magnitude binary comparator

4-bit binary adder

Z8 Z4 Z2 Z1

Carry in

K

4-bit binary adder

S8 S4 S2 S1

0

Output Carry

Addend Augend


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Decoders

Discrete quantities of information are represented in digital system with

binary codes. A binary code of n bits is capable of representing up 2n distinct

elements of the coded information. Decoder is a combinational circuit thatconverts binary information from n input lines to a maximum of 2n unique

output lines. If n-bit decoded information has unused or don’t-care

conditions, the output decoder will have less than 2n output. The name

decoder is also used in conjunction with some code converters such as BCD-

to-seven-segment decoder.

Inputs Outputs

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Truth table of 3-to-8 lined decoder

Observe that the output variables are mutually exclusive because only one

output can be equal to 1 at any time. The output line whose value is equal to1 represents the minterm equivalent of the binary number presently available

in the input lines.

We can construct a more big line decoder using small decoders

Example: construct a 4-to-8 (4×16) line decoder using 3-to-8 decoder.

D0

D2D1

D3D4

D6D5

D7En

3×8

Decoder

D8

D2D9

D11D12

D14D13

D15En

3×8

Decoder

A

B

C

D


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Exercise1: Design BCD-to-decimal decoder.

Exercise2: Design BCD-to-seven-segment decoder.

Exercise3: Implement a full-adder circuit using 3-to-8 decoder.

Encoders

An Encoder is a digital function that produces a reverse operation from that

of decoder.

OutputsInputs

X Y ZD0 D1 D2 D3 D4 D5 D6 D7

0 0 010000000

0 0 101000000

0 1 000100000

0 1 1000100001 0 000001000

1 0 100000100

1 1 000000010

1 1 100000001

Truth table of 8-to-3 encoder

Multiplexers

Multiplexing means transmitting a large number of information units over a

smaller number of channels or lines. A digital multiplexer is a combinational

circuit that selects binary information from one of many input lines anddirects it to single output line. The selection of particular input line is

controlled by a set of selection lines. Normally, there are 2n input lines and n

selection lines whose bit combinations determine which input is selected.

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Boolean function implementation using multiplexers

If we have a Boolean function of n+ 1 variables, we take n of these variables

and connect them to the selection lines of the multiplexer. The remaining

single variable of the function is used for the inputs of the multiplexer. If A

is this single variable, the inputs of the multiplexer are chosen to be either A

or A’ or 1 or 0. By judicious use of these four values for the inputs and by

connecting the other variables to the selection lines, one can implement any

S0 S1

Y

01

2

3

4×1

MUX

I0 I1

I2 I3

OutputInputs

Select


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Boolean function with a multiplexer. In this way it is possible to generate

any function of n+1 variables with a 2n –to-1 multiplexer.

Procedure

1)

express the function in its sum of minterms form, Assume that theordered sequence of variables chosen for minterms is ABCD…, where

A is leftmost variable in the ordered sequence of n and BCD… are the

remaining n-1 variables. Connect the n-1 variables to the selection lines

of the multiplexer with B connected to high-order selection line, C to

the next lower selection line and so on down to the last variable.

2) List the inputs of the multiplexer and under them list all the minterms in

two rows. The first row lists all those minterms where A is

complemented, and the second row all the minterms with A

uncomplemented.3)

Circle all the minterms of the function and inspect each column

separately.

a)

If the two minterms in a column are not circled, apply 0 to the

corresponding multiplexer input.

b)

If the two minterms are circled, apply 1 to the corresponding

multiplexer input.

c) If the bottom minterm is circled and the top is not circled, apply

A to the corresponding multiplexer input.

d)

If the top minterm is circled and the bottom is not circled, apply

A’ to the corresponding multiplexer input.

Example: Implement ( )∑= 15,9,8,4,3,1,0),,,( DC B AF with a multiplexer

Solution

I0 I1 I2 I3 I4 I5 I6 I7

A’ 0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

1 1 0 A’ A’ 0 0 A

D

I0

I1

I2 I3

I4

I5

I6

I7

Y F8×1

MUX

0

1

A

BC


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Demultiplexers

It is a combinational logic circuit that receives information on a single line

and transmits this information on one of 2n possible output lines. The

selection of a specific output line is controlled by the bit values of nselection lines. A decoder with an enable input can function as a

demultiplexer.

Read-only memory (ROM)We know that a decoder can generate 2n minterms of the n input variables.

By inserting OR gates to sum the minterms of Boolean functions, we were

able to generate any desired combinational circuit. A read-only memory

(ROM) is a device that includes both the decoder and the OR gates within a

single IC package. The connections between the outputs of the decoder and

the inputs of the OR gates can be specified for each particular configuration

by “programming” the ROM. The ROM is very often used to implement a

complex combinational circuit in one IC package and thus eliminate all

interconnecting wires.

Memory size=2n×m

E A B D0 D1 D2 D3

0 X X 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

A B D0 D1 D2 D3

0 0 E 0 0 0

0 1 0 E 0 0

1 0 0 0 E 0

1 1 0 0 0 E

m Outputs

(Data)

n Inputs

(Address)

2n×m

ROM

E

Input

Select

D0

D1

D2

D3

1×4

Demultiplexer

D0

D1

D2

D3

A B

2×4

Decoder

A

B

E

Enable


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ROM types

1)

Mask programming ROM

2)

Programmable ROM (PROM)

3)

Erasable Programmable ROM (EPROM)4)

Electrically Erasable Programmable ROM (E2PROM)

Example: Design a combinational circuit that accept a 3-bit number and

generates an output binary number equal to the square of the input number.

Use a minimum ROM size.

Solution:

Inputs Outputs

X Y Z D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 10 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 1 0 1 1 0 0 1

1 1 0 1 0 0 1 0 0

1 1 1 1 1 0 0 0 1

D4

D5

D3

D2

23×4

ROM

D1D0

Z

Y

X

0


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Dr Oday A.LA Ridha 42

Sequential logic circuit

Introduction Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As

soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics

circuits have no memory. In many applications, information regarding input values at a certain instant of timeis required at some future time. Although every digital system is likely to have combinational circuits, most

systems encountered in practice also include memory elements, which require that the system be described in

terms of sequential logic. Circuits whose outputs depends not only on the present input value but also the

past input value are known as sequential logic circuits. A general block diagram of a sequential circuit is

shown below.

Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a feedback

path. The memory elements are devices capable of storing binary information within them. Thecombinational part of the circuit receives two sets of input signals: one is primary (coming from the circuit

environment) and secondary (coming from memory elements). The particular combination of secondary

input variables at a given time is called the present state of the circuit. The secondary input variables are

also know as the state variables.

The block diagram shows that the external outputs in a sequential circuit are a function not only of external

inputs but also of the present state of the memory elements. The next state of the memory elements is also a

function of external inputs and the present state. Thus a sequential circuit is specified by a time sequence of

inputs, outputs, and internal states.


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Synchronous and Asynchronous Operation

Sequential circuits are divided into two main types: synchronous and asynchronous. Their classification

depends on the timing of their signals.

Synchronous sequential circuits change their states and output values at discrete instants of time, which are

specified by the rising and falling edge of a free-running clock signal. The clock signal is generally some

form of square wave as shown below.

Clock Signal

From the diagram you can see that the clock period is the time between successive transitions in the samedirection, that is, between two rising or two falling edges. State transitions in synchronous sequential circuits

are made to take place at times when the clock is making a transition from 0 to 1 (rising edge) or from 1 to 0

(falling edge). Between successive clock pulses there is no change in the information stored in memory.

The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined as the

time during which the value of the clock signal is equal to 1. The ratio of the clock width and clock period isreferred to as the duty cycle. A clock signal is said to be active high if the state changes occur at the clock's

rising edge or during the clock width. Otherwise, the clock is said to be active low. Synchronous sequential

circuits are also known as clocked sequential circuits.

The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits are binary

cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for the normal valueand one for the complement value of the bit stored in it. Binary information can enter a flip-flop in a variety

of ways, a fact which give rise to the different types of flip-flops.

In asynchronous sequential circuits, the transition from one state to another is initiated by the change in the primary inputs; there is no external synchronization. The memory commonly used in asynchronous

sequential circuits are time-delayed devices, usually implemented by feedback among logic gates. Thus,

asynchronous sequential circuits may be regarded as combinational circuits with feedback. Because of the

feedback among logic gates, asynchronous sequential circuits may, at times, become unstable due to transient

conditions. The instability problem imposes many difficulties on the designer. Hence, they are not ascommonly used as synchronous systems.


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Flip-flops types

1) RS Flip-Flop

Basic flip-flop circuit with NOR gates

S R Q Q’

1 0 1 0

0 0 1 0 after SR=10

0 1 0 1

0 0 0 1 after SR=01

1 1 0 0

Truth table

Basic flip-flop circuit with NAND gates

S R Q Q’

1 0 0 1

1 1 0 1 after SR=10

0 1 1 0

1 1 1 0 after SR=01

0 0 1 1

Truth table

2) Clocked RS Flip-Flop

Qi S R Qi+1

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 indeterminate

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 indeterminate

Characteristic table


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3) D-type Flip-Flop

Qi D Qi+1

0 0 0

0 1 1

1 0 0

1 1 1


4) JK Flip-Flop

Qi J K Qi+1

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0


5) T Flip-Flop

Qi T Qi+1 0 0 0

0 1 1

1 0 1

1 1 0



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S

R

Q

Q

Master

S

R

Q

Q

Slave

Q

Q

S

R

CLK

Y

Y

CLK

S

Y

Q

Timing relationships in a master-slave flip-flop

Valid

CLK

D

tS tH

tS Setup time

tH Hold time

Q Valid

6) Master-slave Flip-Flop

The master-slave combination can be constructed for any type of flip-flop by adding a clock RS flip-flop with

an inverted clock to form the slave

7) Edge-triggered Flip-Flop

Setup time is a definite time in which D input must be maintained at a constant value prior to the application

of the clock pulse.

Hold time is a definite time that D input must be not change after application of positive going transition of

the clock pulse.


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Summary of the Types of Flip-flop Behavior

Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior ofvarious flip-flop types before proceeding further.

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and

in the response invoked by different value of input signals. The four types of flip-flops are defined in Table

below.

FLIP-

FLOP

NAME

FLIP-FLOP

SYMBOL

CHARACTERISTIC

TABLE

CHARACTERISTIC

EQUATIONEXCITATION TABLE

SR

S R Q(next)

0 0 Q

0 1 0

1 0 1

1 1 ?

Q(next) = S + R'Q

SR = 0 (condition)

Q Q(next) S R0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

JK

J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q'

Q(next) = JQ' + K'Q

Q Q(next) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

D

D Q(next)

0 0

1 1

Q(next) = D

Q Q(next) D

0 0 0

0 1 1

1 0 0

1 1 1

T

T Q(next)

0 Q

1 Q'

Q(next) = TQ' + T'Q

Q

Q(next) T

0 0 0

0 1 1

1 0 1

1 1 0

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its

characteristic equation or excitation table. All flip-flops have output signals Q and Q'.


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The characteristic table in the third column of the table defines the state of each flip-flop as a function of itsinputs and previous state. Q refers to the present state and Q(next) refers to the next state after the

occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is equal to

the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse clears the flip-flop.

When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next state when S and R are both

equal to 1 designates an indeterminate next state.

The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S and

R respectively, except for the indeterminate case. When both J and K are equal to 1, the next state is equal to

the complement of the present state, that is, Q(next) = Q'.

The next state of the D flip-flop is completely dependent on the input D and independent of the present state.

The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.

The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop inputsare known and we want to find the value of the flip-flop output Q after the rising edge of the clock signal. As

with any other truth table, we can use the map method to derive the characteristic equation for each flip-flop,

which are shown in the third column of the table.

During the design process we usually know the transition from present state to the next state and wish to findthe flip-flop input conditions that will cause the required transition. For this reason we will need a table that

lists the required inputs for a given change of state. Such a list is called the excitation table, which is shownin the fourth column of the table. There are four possible transitions from present state to the next state. The

required input conditions are derived from the information available in the characteristic table. The symbol Xin the table represents a "don't care" condition, that is, it does not matter whether the input is 1 or 0.


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Analysis of Sequential Circuits

The behavior of a sequential circuit is determined from the inputs, the outputs and the states of its flip-flops.

Both the output and the next state are a function of the inputs and the present state. The suggested analysis procedure of a sequential circuit is set out in the Figure below.

Analysis procedure of sequential circuits


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We start with the logic schematic from which we can derive excitation equations for each flip-flop input.

Then, to obtain next-state equations, we insert the excitation equations into the characteristic equations. Theoutput equations can be derived from the schematic, and once we have our output and next-state equations,

we can generate the next-state and output tables as well as state diagrams. When we reach this stage, we use

either the table or the state diagram to develop a timing diagram which can be verified through simulation.

Now let's look at some examples, using these procedures to analyze a sequential circuit.

This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997, p.230.

Example Modulo-4 counter Derive the state table and state diagram for the sequential circuit shown in the Figure below.

Logic schematic of a sequential circuit

SOLUTION:

STEP 1: First we derive the Boolean expressions for the inputs of each flip-flops in the schematic, in

terms of external input Cnt and the flip-flop outputs Q1 and Q0. Since there are two D flip-flops in this

example, we derive two expressions for D1 and D0:

D0 = Cnt Q0 = Cnt'.Q0 + Cnt.Q0'

D1 = Cnt'.Q1 Cnt.Q1'.Q0 Cnt.Q1.Q0'

These Boolean expressions are called excitation equations since they represent the inputs to the flip-flops ofthe sequential circuit in the next clock cycle.

STEP 2: Derive the next-state equations by converting these excitation equations into flip-flop

characteristic equations. In the case of D flip-flops, Q(next) = D. Therefore the next state equal the excitationequations.

Q0(next) = D0 = Cnt'.Q0 + Cnt.Q0'

Q1(next) = D1 = Cnt'.Q1 Cnt.Q1'.Q0 Cnt.Q1.Q0'


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STEP 3: Now convert these next-state equations into tabular form called the next-state table.

Present State

Q1Q0

Next State

Cnt = 0 Cnt = 1

0 0

0 1

1 0

1 1

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

Each row is corresponding to a state of the sequential circuit and each column represents one set of input

values. Since we have two flip-flops, the number of possible states is four - that is, Q1Q0 can be equal to 00,

01, 10, or 11. These are present states as shown in the table.

For the next state part of the table, each entry defines the value of the sequential circuit in the next clockcycle after the rising edge of the CLK. Since this value depends on the present state and the value of the

input signals, the next state table will contain one column for each assignment of binary values to the inputsignals. In this example, since there is only one input signal, Cnt, the next-state table shown has only two

columns, corresponding to Cnt = 0 and Cnt = 1.

Note that each entry in the next-state table indicates the values of the flip-flops in the next state if their valuein the present state is in the row header and the input values in the column header.

Each of these next-state values has been computed from the next-state equations in STEP 2.

STEP 4: The state diagram is generated directly from the next-state table, shown in the Figure below.

State diagram

Each arc is labeled with the values of the input signals that cause the transition from the present state (the

source of the arc) to the next state (the destination of the arc).


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In general, the number of states in a next-state table or a state diagram will equal 2m

, where m is the number

of flip-flops. Similarly, the number of arcs will equal 2m

x 2k , where k is the number of binary input signals.

Therefore, in the state diagram, there must be four states and eight transitions. Following these transition

arcs, we can see that as long as Cnt = 1, the sequential circuit goes through the states in the following

sequence: 0, 1, 2, 3, 0, 1, 2,.... On the other hand, when Cnt = 0, the circuit stays in its present state until Cntchanges to 1, at which the counting continues.

Since this sequence is characteristic of modulo-4 counting, we can conclude that the given sequential circuit

is a modulo-4 counter with one control signal, Cnt, which enables counting when Cnt = 1 and disables itwhen Cnt = 0.

Below, we show a timing diagram, representing four clock cycles, which enables us to observe the behavior

of the counter in greater detail.

Timing Diagram

In this timing diagram we have assumed that Cnt is asserted in clock cycle 0 at t0 and is disserted in clockcycle 3 at time t4. We have also assumed that the counter is in state Q1Q0 = 00 in the clock cycle 0. Note that

on the clock's rising edge, at t1, the counter will go to state Q1Q0 = 01 with a slight propagation delay; in

cycle 2, after t2, to Q1Q0 = 10; and in cycle 3, after t3 to Q1Q0 = 11. Since Cnt becomes 0 at t4, we know thatthe counter will stay in state Q1Q0 = 11 in the next clock cycle.

In the previous Example, we demonstrated the analysis of a sequential circuit that has no outputs bydeveloping a next-state table and state diagram which describes only the states and the transitions from one

state to the next. In the next example we complicate our analysis by adding output signals, which means that

we have to upgrade the next-state table and the state diagram to identify the value of output signals in eachstate.

This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997, p.234.

Example Derive the next state, the output table and the state diagram for the sequential circuit shown in theFigure below.


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Logic schematic of a sequential circuit.

SOLUTION:

The input combinational logic in the above Figure is the same as in the previous example, so the excitation

and the next-state equations will be the same.

Excitation equations:

D0 = Cnt Q0 = Cnt'.Q0 + Cnt.Q0'

D1 = Cnt'.Q1 Cnt.Q1'.Q0 Cnt.Q1.Q0'

Next-state equations:

Q0(next) = D0 = Cnt'.Q0 + Cnt.Q0'

Q1(next) = D1 = Cnt'.Q1 Cnt.Q1'*Q0 Cnt.Q1.Q0'

In addition, however, we have computed the output equation.

Output equation: Y = Q1Q0

As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 = 11, and it will stay 1as long as the counter stays in that state.

Next-state and output table:

Present State

Q1 Q0

Next State

Cnt=0 Cnt=1

Output

Y

0 0

0 1

1 0

1 1

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

0

0

0

1


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State diagram:

State diagram of the sequential circuit

Timing diagram of the sequential circuit

Note that the counter will reach the state Q1Q0 = 11 only in the third clock cycle, so the output Y will equal1 after Q0 changes to 1. Since counting is disabled in the third clock cycle, the counter will stay in the state

Q1Q0 = 11 and Y will stay asserted in all succeeding clock cycles until counting is enabled again.

Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic

diagram or a list of Boolean functions from which a logic diagram can be obtained. In contrast to a

combinational logic, which is fully specified by a truth table, a sequential circuit requires a state table for its


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specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence

representation, such as a state diagram.

A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit

consists of choosing the flip-flops and then finding the combinational structure which, together with the flip-flops, produces a circuit that fulfils the required specifications. The number of flip-flops is determined from

the number of states needed in the circuit.

The recommended steps for the design of sequential circuits are set out below.

Sequential circuit design steps


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STEP 2

State Diagram

STEP 3

Present State

Q0 Q1

Next State

x = 0 x = 1

0 0

0 1

1 0

1 1

0 0 0 1

1 0 0 1

1 0 1 1

1 1 0 0

STEP 4 State Reduction

Any design process must consider the problem of minimizing the cost of the final circuit. The two most

obvious cost reductions are reductions in the number of flip-flops and the number of gates.The number of states in a sequential circuit is closely related to the complexity of the resulting circuit. It is

therefore desirable to know when two or more states are equivalent in all aspects. The process of eliminatingthe equivalent or redundant states from a state table/diagram is known as state reduction. Two states are

said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send

the circuit either to the same state or to an equivalent state. When two states are equivalent, one of them

can be removed without altering the input-output relationships.

Example: Let us consider the state table of a sequential circuit shown below.

Present State Next State

x = 0 x = 1

Output

x = 0 x = 1

A

B

C

D

E

F

B C

F D

D E

F E

A D

B C

1 0

0 0

1 1

0 1

0 0

1 0


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It can be seen from the table that the present state A and F both have the same next states, B (when x=0) and

C (when x=1). They also produce the same output 1 (when x=0) and 0 (when x=1). Therefore states A and Fare equivalent. Thus one of the states, A or F can be removed from the state table. For example, if we remove

row F from the table and replace all F's by A's in the columns, the state table is modified as shown in the

table below.


x = 0 x = 1

Output

x = 0 x = 1

A

B

C

D

E

B C

A D

D E

A E

A D

1 0

0 0

1 1

0 1

0 0

State F removed

It is apparent that states B and E are equivalent. Removing E and replacing E's by B's results in the reduce

table below..


x = 0 x = 1

Output

x = 0 x = 1

A

BC

D

B C

A DD B

A B

1 0

0 01 1

0 1

Reduced state table

The removal of equivalent states has reduced the number of states in the circuit from six to four. Two states

are considered to be equivalent if and only if for every input sequence the circuit produces the same output

sequence irrespective of which one of the two states is the starting state.

Note: A circuit with m flip-flops would have 2m

states. There are occasions when a sequential circuit may useless than this maximum number of states. States that are not used in specifying the sequential circuit are not

listed in state table. When simplifying the input functions to flip-flops, the unused states can be treated as

don’t conditions.

Design of Sequential Circuits Examples

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.

Example 1 We wish to design a synchronous sequential circuit whose state diagram is shown below. Thetype of flip-flop to be use is J-K.


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State diagram

From the state diagram, we can generate the state table shown in Table 9. Note that there is no output section

for this circuit. Two flip-flops are needed to represent the four states and are designated Q0Q1. The input

variable is labeled x.

Present State

Q0 Q1

Next State

x = 0 x = 1

0 0

0 1

1 0

1 1

0 0 0 1

1 0 0 1

1 0 1 1

1 1 0 0

State table.

We shall now derive the excitation table and the combinational structure. The table is now arranged in a

different form shown in the table below, where the present state and input variables are arranged in the form

of a truth table. Remember, the excitable for the JK flip-flop was derive in the table.

Excitation table for JK flip-flop

Output Transitions

QQ(next)

Flip-flop inputs

J K

0 0

0 1

1 0

1 1

0 X

1 X

X 1

X 0


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Excitation table of the circuit

Present State

Q0 Q1

Next State

Q0 Q1

Input

x

Flip-flop Inputs

J0K0 J1K1

0 0

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

0 1

1 0

0 1

1 0

1 1

1 1

0 0

0

1

0

1

0

1

0

1

0 X 0 X

0 X 1 X

1 X X 1

0 X X 0

X 0 0 X

X 0 1 X

X 0 X 0

X 1 X 1

In the first row of the above table, we have a transition for flip-flop Q0 from 0 in the present state to 0 in thenext state. In the table we find that a transition of states from 0 to 0 requires that input J = 0 and input K = X.So 0 and X are copied in the first row under J0 and K0 respectively. Since the first row also shows a

transition for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are copied in the first

row under J1 and K1. This process is continued for each row of the table and for each flip-flop, with the input

conditions as specified in the table.

The simplified Boolean functions for the combinational circuit can now be derived. The input variables are

Q0, Q1, and x; the outputs are the variables J0, K0, J1 and K1. The information from the truth table is plotted

on the Karnaugh maps shown in the figure below.

Karnaugh Maps

The flip-flop input functions are derived:

J0 = Q1.x' K0 = Q1.x

J1 = x K1 = Q0'.x' + Q0.x = Q0 x


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The logic diagram is drawn in the figure below.

Logic diagram of

the sequential

circuit.

Example 2 Design a sequential circuit whose state tables are specified in the table below, using D flip-flops.

This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996,

p.176.

State table of a sequential circuit.

Present State

Q0 Q1

Next State

x = 0 x = 1

Output

x = 0 x = 1

0 0

0 1

1 0

1 1

0 0 0 1

0 0 1 0

1 1 1 0

0 0 0 1

0 0

0 0

0 0

0 1

Excitation table for a D flip-flop.

Output Transitions

Q Q(next)

Flip-flop inputs

D

0 0

0 1

1 0

1 1

0

1

0

1


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Next step is to derive the excitation table for the design circuit, which is shown in the table below. The output

of the circuit is labeled Z.

Present StateQ0 Q1

Next StateQ0 Q1

Inputx

Flip-flop

Inputs

D0 D1

OutputZ

0 0

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

0 1

0 0

1 0

1 1

1 0

0 0

0 1

0

1

0

1

0

1

0

1

0 0

0 1

0 0

1 0

1 1

1 0

0 0

0 1

0

0

0

0

0

0

0

1

Excitation table

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions,

which is shown in Figure below.

Karnaugh maps

The simplified Boolean expressions are:

D0 = Q0.Q1' + Q0'.Q1.x

D1 = Q0'.Q1'.x + Q0.Q1.x + Q0.Q1'.x'

Z = Q0.Q1.x

Finally, draw the logic diagram.


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Logic diagram of the sequential circuit.

Example 3 A counter is first described by a state diagram, which is shows the sequence of states throughwhich the counter advances when it is clocked. Figure below shows a state diagram of a 3-bit binary counter.

This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan Publishing, 1990,

p.395.

State diagram of a 3-bit binary counter

The circuit has no inputs other than the clock pulse and no outputs other than its internal state (outputs are

taken off each flip-flop in the counter). The next state of the counter depends entirely on its present state, and

the state transition occurs every time the clock pulse occurs. Figure below shows the sequences of count aftereach clock pulse.


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Once the sequential circuit is defined by the state diagram, the next step is to obtain the next-state table,

which is derived from the state diagram in the above Figure and is shown in the Table below.

State table

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

Since there are eight states, the number of flip-flops required would be three. Now we want to implement the

counter design using JK flip-flops.

Next step is to develop an excitation table from the state table, which is shown in the table below


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Excitation table

Output State Transitions Flip-flop inputs

J2 K2 J1 K1 J0 K0Present StateQ2 Q1 Q0 Next StateQ2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

0 X 0 X 1 X

0 X 1 X X 1

0 X X 0 1 X

1 X X 1 X 1

X 0 0 X 1 X

X 0 1 X X 1

X 0 X 0 1 X

X 1 X 1 X 1

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a

simplified Boolean expression for each flip-flop input. This is shown in the Figure below.

The 1s in the Karnaugh maps of the above Figure are grouped with "don't cares" and the following

expressions for the J and K inputs of each flip-flop are obtained:

J0 = K0 = 1

J1 = K1 = Q0


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J2 = K2 = Q1.Q0

The final step is to implement the combinational logic from the equations and connect the flip-flops to form

the sequential circuit. The complete logic of a 3-bit binary counter is shown in the Figure below.

Logic diagram of a

3-bit binary counter.

Example 4 Design a counter specified by the state diagram in Example 3 using T flip-flops. The statediagram is shown here again in the Figure below.

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.


The state table will be the same as in Example 3.

Now derive the excitation table from the state table, which is shown in the Table below.


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Excitation table.

Output State Transitions Flip-flop inputs

T2 T1 T0Present State

Q2 Q1 Q0 Next StateQ2 Q1 Q0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

0 0 1

0 1 1

0 0 1

1 1 1

0 0 1

0 1 1

0 0 1

1 1 1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean

expressions, which is shown in the Figure below.

The following expressions are obtained:

T0 = 1; T1 = Q0; T2 = Q1.Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of

the counter is shown in the Figure below.

Logic diagram of 3-bit binary counter.


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Registers Registers: is a group of binary storage cells suitable for holding binary information.

Simple register

Shift Registers: it is a register that capable of shifting its binary contents either to the left orright.

Shift-right register

Bidirectional shift register with parallel load

D

Q

D

Q

D

Q

D

Q

I4

O4

I3

O3

I2

O2

I1

O1

Load

D Q D Q D Q D QSerial in

O4 O3 O2 O1

Shift right

Serial Out

D

Q

D

Q

D

Q

D

Q

O4 O3 O2 O1

4×1

3 2 1 0

4×1

3 2 1 0

4×1

3 2 1 0

4×1

3 2 1 0

S1 S0

SIfor shift left

SI

for shift rightI4 I3 I2 I1

Clear CLK

S1S0=00 no change, S1S0=01 Shift right

S1S0=10 Shift left, S1S0=11 parallel load


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Serial addition

Two binary numbers must be first loaded to the shift registers. Shift right signal must

be asserted for one word time. Otherwise incorrect results obtained.

Exercises

1) Design a sequential circuit whose state table is shown below. Use JK flip-flops for the

design.

Present State

Q1 Q0

Next State

x=0 x=1

Output

x=0 x=1

0 0

0 1

1 0

1 1

0 0 0 1

0 1 0 0

1 0 0 1

1 1 0 0

0 0

0 1

0 0

0 1

2)

Using sequential circuit design procedure design k-bit serial adder

3) Design a logic circuit that count the number of occurs of the sequence 00 11 10 01 11

Shift register A

Shift register B

F.A

S

C

X

Y

Z

DQ

Clear

LoadShift right

CLK

Shift register A

Shift register B

Serial adder Shift register C

a

b

c


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CountersCounters come in two categories: ripples counters and synchronous counters.

1)

Ripple Counters

a)

Binary ripple counter

b) BCD ripple counter

The following are the conditions for each F.F transition:

Q1 is complemented on the negative edge of every count pulse;

Q2 is complemented if Q8=0 and Q1 goes from 1 to 0, Q2 is cleared if Q8=1 and Q2 is

cleared if Q8=1 and Q1 goes from 1 to 0;

Q4 is complemented when Q2 goes from 1 to 0;

Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to 0. Q8 is cleared if either

Q4 or Q2 is 0 and Q1 goes from 1 to 0.

Three Digits BCD ripple counter

Count

Pulses

Q1 Q2 Q4 Q8

BCD Counter

100 Digit

Q1 Q2 Q4 Q8

BCD Counter

101

Digit

Q1 Q2 Q4 Q8

BCD Counter

102Digit

1

Q1

J

K

Q

CLK

1J

K

Q

CLK

1

J

K

Q

CLK

1J

K

Q

CLK

Q2 Q4 Q8

Count

PulsesQ 11

1

A1

J

K

Q

CLK

1J

K

Q

CLK

1J

K

Q

CLK

1J

K

Q

CLK

1

A2 A3 A4

Count

Pulses

To next

Stage111


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4-bit counter

Load

Clear

Up/Down

Enable

CLK

Carry

A4 A3 A2 A1

I4 I3 I2 I1

2) Synchronous Counters

Synchronous counters are distinguished from ripple counters in that clock pulses are

applied to the CLK inputs of all flip-flops. The common pulse triggers all flip-flops

simultaneously, rather than one at a time in succession as in ripple counters.

a) Synchronous binary counter

b)

Universal binary up/down counters with a parallel load (see Morris Mano p.282)

Signal name Function description

LoadClear

Up/Down

Enable

Carry

Load counter with I4I3I2I1 1 Clear the content of counter

1 makes counter count up, 0 makes counter count down

1 make counter count, 0 stop counting

1 Generated when the counter reaches the maximum count

A1

J

K

Q

CLK

J

K

Q

CLK

J

K

Q

CLK

J

K

Q

CLK

A2 A3 A4

To next

stageCount

enable

CLK


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4-bit counter

Load=0

Clear

Up/Down=1

Enable=1

CLK

Max/Min

A4 A3 A2 A1

I4 I3 I2 I1

Exercise: Construct a mod-6 counter using universal counter

a) count sequence “0,1,2,3,4,5”

b)

“10,11,12,13,14,15”

c)

“3,4,5,6,7,8”

(a)

Johnson Counter

Ring Counter

Load counter with an initial value=1000

Counting sequence is “1000, 0100,0010,0001,1000, and so on”

CLK Content

0

1

2

3

4

5

6

7

8

0000

1000

1100

1110

1111

0111

0011

0001

0000

D Q D Q D Q D Q

O4 O3 O2 O1

CLK

Q

Shift Register with parallel loadLoadShift Right

CLK


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Sequential circuit implementation

1) Sequential logic circuit can be implemented using a register and a combinational

circuit as shown below:

Register and combinational parts is constructed from discrete components.

2) Sequential logic circuit can be implemented using a register and a ROM as shown

below:

3) Sequential logic circuit can be implemented using Programmable logic devices (PLD)

One of the most popular PLD in our university is generic array logic (GAL). This type

of PLD can be used to implement either combinational or sequential logic circuits. There are

number of GAL IC’s, like PALCE20V8 and PALCE16V8, which can be erased and

reprogrammed electrically. The general structure of PALCE20V8 is shown in the figure

below:

RegisterCombinational

circuitCLK

OutputsInputs

RegisterROM

CLK

OutputsInputs


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GAL consists of micro cells (MC0-MC7). Each micro cell has a general structure is shown

below:

Moreover, Micro cells can be configured to work in one of the

ninth modes. Cells configuration is done through setting control

bits (SG1, SG0, SL1x, and SL0x). The table below shows the

different configurations. SL1x control bit, where x represents

micro cell number, is used to program the output polarity of cell,

i.e., output is active low or active high.

Figures below represent the different possible configurations of micro cells


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Overall block diagram of PALCE20V8


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ALGORITHMIC STATE MACHINE (ASM)

The binary information stored in a digital system can be classified as either data or

control information. Data are discrete elements of information that are manipulated to

perform arithmetic, logic, shift, and other similar data processing tasks. These operations are

implemented with digital components such as adders, decoders, multiplexers, counter, andshift registers. Control information provides command signals that supervise the various

operations in the data section in order to accomplish the desired data-processing tasks. The

logic design of a digital system can be divided into two distinct parts. One part is concerned

with the design of the digital circuits that perform the data-processing operations. The other

part is concerned with the design of the control circuit that supervises the operations and their

sequence.

The relationship between the control logic and the data processor in a digital system is

shown in the figure below.

The control sequence and data-processing tasks of a digital system are specified by a

mean of a hardware algorithm, a finite number of procedural steps that specify how to obtain

a solution to a problem. The most challenging and creative part of a digital design is theformulation of hardware algorithms for achieving required objectives.

A flowchart is a convenient way to specify the sequence of procedural steps and

decision paths for an algorithm. A special flowchart that has been developed specially to

define digital hardware algorithms is called Algorithmic state machine (ASM) chart.

The chart is composed of three basic elements: the state box, the decision box, and the

conditional box. A state in the control sequence is indicated by state box. The shape of the

state box is rectangle within wh

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Digital System Design lectures