Digital Systems Design 2

Digital Systems Design 2

VHDL: Modeling BehaviourRef. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998

April 24, 2023 Veton Këpuska 2

Modeling Behavior with VHDL Presented VHDL constructs (e.g., CSAs) are

limited in modeling only certain class of digital components. In order to be able to describe and model a larger set of digital components a more powerful language construct is needed.

The process construct of VHDL provides the basis for these descriptions. It is a construct that can model:

the behavior of components that are much more complex than delay elements through CSA constructs, and

systems at higher level of abstraction.


VHDL- Process Construct Up to this point, presented VHDL language and modeling concepts

were derived from the operational characteristics of digital circuits (where the design is represented as a schematic of concurrently operating components).

Each component is characterized by the generation of events on output signals in response to events on input signals.

These output events may occur after a component dependent propagation delay.

This relationship is captured by CSA statement that explicitly relates input signals, output signals, and propagation delays.

CSAs are convenient constructs for cases when components correspond to gates or switch level models of transistors.

For constructing models of complex components such as CPUs, memory modules, or communication protocols, such a model of behavior can be quite limiting.


VHDL- Process Construct For modeling components such as memories, the state

information is necessary to be retained and being able just to compute output signals as function of values of the input signals is not sufficient.

Memory Model:

MemoryDI

DO

ADDR

R W


VHDL Process example: Memory Model Memory can be implemented using

conventional sequential programming constructs: Memory can be implemented as an array. Address value can be used to index this array. Depending on the value of the control signals

one can determine read from array or write into array operation. This behavior can be realized in VHDL by using sequential statements in the process construct.


VHDL Process example: Memory Model Generic process declaration and syntax.

process_name: process (signal1, signal2, …, signalN)

-- declarative regionvariable variable-names: variable-type;type type-name is (value-list);constant constant-name: type-name := value;

begin-- process body region where conventional programming

constructs can be used.end process process_name;


VHDL – Memory Examplelibrary IEEE;use IEEE.std_logic_1164.all;use WORK.std_logic_arith.all;

entity memory isport (address, write_data: in

std_logic_vector(31 downto 0);MemWrite, MemRead: in std_logic;read_data: out std_logic_vector(31 downto 0)

end memory;

architecture memory_func of memory istype mem_array is array(0 to 7) of

std_logic_vector(31 downto 0);

begin -- for architecture

mem_process: process (address, write_data)variable data_mem: mem_array := (to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”),to_stdlogicvector(X”00000000”));

variable addr: integer;

begin -- for process-- the following conversion function is in WORK.std_logic_arith

package

addr := to_integer (address (2 downto 0));

if MemWrite = ‘1’ thendata_mem(addr) := write_data;

elsif MemRead = ‘1’ then read_data <= data_mem(addr) after 10 ns;

end if;

end process mem_process;

end memory_func;


VHDL – Process Construct Some important remarks to be noted:

All standard data type may be used. Variable assignment, using “:=“ operator, takes

effect immediately. The value of a variable is visible to all following

statements within that same process. Control flow within a process is strictly sequential

and is altered only by constructs such as if-then-else and loop.

Additional distinguishing feature of VHDL process is that assignments can be made to signals declared external to the process.

The statements within a process are executed sequentially and are referred to as sequential statements.


VHDL – Process Construct CSA statements are executed when an event occurs

on a signal on its right hand side. When a process gets executed?

Similarly, process gets executed when an event takes place on any of the signals on its input list. This list is thus referred to as sensitivity list. Once a process gets started it executes in zero

(simulated) time. It can generate a new set of events on output signals,

which in turn may trigger a number of processes and/or CSAs associated with them.

Note: VHDL CSAs are special (and less capable) processes.


Programming Constructs Syntax of VHDL if

statements: if boolean-expression

thensequential-statement

end if;

if boolean-expression then

sequential-statement

elsesequential-statement

end if;

if boolean-expression then

sequential-statement

elsif boolean-expression thensequential-statement

…elsif boolean-

expression thensequential-statement

elsesequential-statement

end if;


Programming Constructs Syntax of Case Statement

case expression iswhen choices => sequential-statement;…when choices => sequential-statement;

end case;


Programming Constructs Concurrent Processes and the

Case Statementlibrary IEEE;use IEEE.std_logic_1164.all;

entity half_adder isport (a,b: in std_logic;

sum,carry: out std_logicend half_adder;

architecture half_adder_func of half_adder is

begin

sum_process: process(a,b)begin if (a=b) then

sum <= ‘0’ after 5 ns; else

sum <= (a or b) after 5 ns; endifend process sum_process;

carry_process: process(a,b)begin case a is

when ‘0’ =>carry <= a after 5 ns;when ‘1’ =>carry <= b after 5 ns;when others =>carry <= ‘X’ after 5 ns;

end case;end process;

end half_adder_func;


Programming Constructs Loop construct

while boolean-expression loopsequential-statement;…sequential-statement;

end loop;

For constructfor boolean-expression in range loop

sequential-statement;…sequential-statement;

end loop;


Example of the use of the loop constructs Long multiplication using base 2 arithmetic.

Successive addition is simple for binary representation of numbers: The multiplicand is added once or not added at all for

each multiplier bit.

0110X 0101---------- 0110+ 0000+ 0110+0000---------- 0011110


Long multiplication using base 2 arithmetic.

0110MD

0000AC

|0101MQ MultiplierMultiplicand

0110+

0110 |0101 ADD0011 0|010 SHIFT0000+

0011 0|010 ADD0001 10|01 SHIFT0110+

0111 10|01 ADD0011 110|0 SHIFT0000+

0011 110|0 ADD0001 1110| SHIFT


Example of the use of the loop constructslibrary IEEE;use IEEE.std_logic_1164.all;use WORK.std_logic_arith.all;

entity mult32 isport (multiplicant, multiplier: in

std_logic_vector(31 downto 0);product: out std_logic_vector(63 downto 0)

end mult32;

architecture mult32_func of mult32 isconstant module_delay: Time := 10 ns;

begin -- architecture

mult_process: process (multiplicand, multiplier)variable product_register: std_logic_vector(63

downto 0) := x’0000000000000000’;variable product_register: std_logic_vector(31

downto 0) := x’00000000’;

begin -- process

multiplicant_reregister := multiplicant; product_register(63 downto 0) :=

x’00000000’& multiplier; -- -- repeated shift-and-add loop -- for index in 1 to 32 loop if product_register(0) = ‘1’ then product_register(63 downto 32) :=

product_register(63 downto 32)+multiplicant_register(31 downto 0);

end if; --perform right shift with zero fill product_register(63 downto 0) := ‘0’ &

product_register (63 downto 1); end loop;

-- write result to output port product <= product_register after

module_delay;

end process mult_process;end mult32_func;


More on Processes Upon initialization all processes are executed once. Thereafter

processes are executed in a data-driven manner: activated by events on signals in the sensitivity list of the process, or by waiting for the occurrence of specific event using the wait

statement.

All of the ports of the entity and the signals declared within an architecture are visible within a process: this means that they can be read or assigned values from within a process. The process may read or write any of the signals declared in the

architecture or any of the ports on the entity. This feature implies that a process (e.g., A) may trigger execution

of another process (e.g., B) by changing the state of a signal which is in the sensitivity list of this other process (B). In turn the process B may change the state of a signal that triggers the event that executes the process A. This is powerful mechanism that supports process communication.


Example of communicating process model of a full adderlibrary IEEE;use IEEE.std_logic_1164.all;

entity full_adder isport (in1,in2, c_in: in std_logic;

sum,c_out: out std_logicend full_adder;

architecture full_adder_func of full_adder is

signal s1, s2, s3: std_logic;constant delay : Time := 5 ns;begin HA1: process (in1, in2) -- process

describing the first half adder begin

s1 <= (in1 xor in2) after delay; s2 <= (in1 and in2) after delay;

end process HA1;

HA2: process (s1, c_in) -- process describing the second half adder

begins1 <= (s1 xor c_in) after delay; s2 <= (s1 and c_in) after delay;

end process HA2;

OR1: process (s2, s3) -- process describing two input-or gate

beginc_out <= (s2 xor s3) after delay;

end process OR1;

end full_adder_func;

HA1In1

In2

s1

s3

HA2s1

c_in

sum

s2

In1

In2

c_inO1

c_out

sum


The Wait Statement Presented examples describe behavior of

models that is data-driven: Events on the input signals initiated execution of

processes. Processes are suspended until next event on a

signal defined it its sensitivity list.

Fits well with the behavior of real combinational logic circuits.

Fails to address behavior when circuits compute outputs only at specific point in time independent of events on the inputs.


The Wait Statement More specifically: in synchronous sequential circuts,

the clock signal determines when the outputs may change or when inputs are read.

Such behavior requires us to be able to specify in a more general mannaer the conditions under which the circuit outputs must be (re-)computed.

In VHDL context, this means that there should be mechanisms in the language that in more general way allow specifications when a process is executed or suspended pending the occurrence of an event or events.

This capability is provided in VHDL by wait statement.


The Wait Statement Forms of wait statements:

wait for time-expression Causes suspension of the process for a period of

time given by time-expression: wait for 20 ns;

wait on signal Process suspends execution until an event

occurs on one or more signals in a group of signals:

wait on clk,reset,satus; wait until condition

Process is suspended until condition evaluates to a Boolean value (TRUE or FALSE).


The Wait Statement Wait statements provide mechanisms

that allow construction of models where a process is suspended at multiple points within the process and not just at the beginning (as provided by sensitivity list).

Example of Positive Edge-Triggered D Flip-Flop.


Positive Edge-Triggered D Flip-Flop D Flip-Flop samples its D input on the rising/falling edge of the

clock signal. Its input value is transferred to output at these specific and discrete points in time.

Q

QSET

CLR

DD

Clk

Q

Qbar

S

R

S R Clk D Q Qbar

1 0 X X 1 00 1 X X 0 10 0 R 1 1 00 0 R 0 0 11 1 X X ? ?


D Flip-Flop with Asynchronous Set and Reset inputslibrary IEEE;use IEEE.std_logic_1164.all;

entity asynch_dff isport (R,S,D,Clk: in

std_logic; Q,Qbar: out std_logic

end asynch_dff;

architecture asynch_dff _func of asynch_dff is

beginDff_process: process

(R,S,Clk)begin

if (R = ‘1’) then Q <= ‘0’ after 5 ns;Qbar <= ‘1’ after 5 ns;

elsif (S = ‘1’) thenQ <= ‘1’ after 5 ns;Qbar <= ‘0’ after 5 ns;

elsif (Clk’event and Clk=‘1’) thenQ <= D after 5 ns;Qbar <= (not D) after 5 ns;

endif;end process Dff_process;end asynch_dff_func;


Example of Asynchronous Communication RQ – request signal ACK – acknowledgment transmit_data -

Transmit data signal

Following example illustrates The use of wait

statement to control asynchronous communication between processes.

The ability to suspend the execution of a process at multiple points within the VHDL code.

4-phase handshake

RQ

ACK


Example of Asynchronous Communicationlibrary IEEE;use IEEE.std_logic_1164.all;

entity handshake isport (input_data: in

std_logic_vector(31 downto 0);end handshake;

architecture handshake _func of handshake is

signal transmit_data: std_logic_vector(31 downto 0);

signal RQ,ACK: std_logic; begin

producer: processbegin-- wait until input data becomes availablewait until input_data’event;-- provide data as producertransmit_data <= input_data; RQ <= ‘1’;wait until ACK = ‘1’;RQ <= ‘0’;wait until ACK = ‘0’;end process producer;consumer: processvariable receive_data: std_logic_vector(31

downto 0); begin-- wait until producer makes the data availablewait until RQ = ‘1’;receive_data := transmit_data; -- read the

datatransmit_data <= input_data; ACK <= ‘1’;wait until RQ = ‘0’;ACK <= ‘0’;end process consumer;end handshake _func;


Attributes D flip-flop example introduced the idea of an attribute

of a signal. Attributes can be used to return various types of information about the signal. Example:

Determining if an event has occurred, Amount of time that has elapsed since the last event

occurred on the signal: Clk’last_event

etc. In effect, when simulator executes the above

statement a function call occurs that checks this property. This function returns the time since the last event occurred on signal clk. Such attributes are referred to as function attributes.


Some useful Function AttributesFunction attribute Function

signal_name’event Function returning a Boolean signifying a change in value on this signal.

signal_name’active Function returning a Boolean signifying an assignment made to this signal. This assignment may not be a new value.

signal_name’last_event Function returning the time since the last event on this signal.

signal_name’last_active Function returning the time since the signal was last active.

signal_name’last_value Function returning the previous value of this signal.


Attributes There are numerous other classes of

attributes. Only one additional one will be described in this section: value attribute.

These attributes return values.


Some useful Value AttributesValue attribute Valuescalar_name’left Returns the left most value of

scalar_name in its defined range.

scalar_name’right Returns the right most value of scalar_name in its defined range.

scalar_name’high Returns the highest value of scalar_name in its range.

scalar_name’low Returns the lowest value of scalar_name in its range.

scalar_name’ascending Returns true if scalar_name has an ascending range of values.

array_name’length Returns the number of elements in the array array_name.


Attributes Example 1: Memory model described

earlier contains the definition of a new type as follows:type mem_array is array(0 to 7) of

std_logic_vector(31 downto 0);

mem_array’left = 0; mem_array’ascending = true; mem_array’length = 8;


Attributes Example 2: When describing models

of state machines it is useful to have the following data type (enumerated) defined:type state_type is

(state0,state1,state2,state3);

state_type’left = state0; state_type’right = state3;


Attributes Example 3: A very useful attribute of arrays

is the range attribute. Consider a loop that scans all of the elements in an array value_array. The index range is returned by the value_array’range:

for i in value_array’range loop…my_var := value_array(i);…end loop;


Generating Clocks and Periodic Waveforms Wait statements provide the programmer with explicit

control over the reactivation of processes. Thus they can be used for generating periodic waveforms as shown in following example.

Example of Generating Periodic Waveforms: We have seen previously that we can assign to

signals several future events as in this example:

signal <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;

This signal can be used within a process to be executed repeatedly thus producing a periodic waveform as presented in the next slide.

Note that in VHDL upon initialization of the model all processes are executed.


Generating Clocks and Periodic Waveformslibrary IEEE;use IEEE.std_logic_1164.all;

entity periodic isport (Z: out std_logic);end periodic;

architecture periodic_func of periodic isbeginprocessbegin

Z <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;wait for 50 ns;

end process;end periodic_func;


Generating Clocks and Periodic Waveforms Example of a Two-Phase Clock:

Following VHDL code depicts an example of generation of non-overlapping clocks and reset pulses.


Generating Clocks and Periodic Waveformslibrary IEEE;use IEEE.std_logic_1164.all;

entity two_phase isport (phi1,phi2,reset: out std_logic);end two_phase;

architecture two_phase_func of two_phase is

beginreset_process: reset <= ‘1’, ‘0’

after 10 ns;

clock_process: process begin

phi1 <= ‘1’, ‘0’ after 10 ns; phi2 <= ‘0’, ‘1’ after 12 ns, ‘0’

after 18 ns; wait for 20 ns;

end process clock_process;end two_phase_func;

Two phase non-overlapping clocks

0 10 20 30 40 50 60

reset

phi1

phi2


Modeling State Machines The examples described up to now used only

combinational and sequential circuits in isolation. Processes that model combinational circuits are

sensitive to the inputs; and are activated whenever an event occurs on an input signal.

Sequential devices on the other hand retain information stored in internal devices (e.g., flip-flops and latches) and their outputs depends on their current state as well as current inputs. Sequential devices typically update their values at

discrete points in time determined by a periodic signal (e.g., clock).

With finite number of storage elements, the number of unique states is finite and such circuits are referred to as finite state machines.


General Finite State Machine

CombinationalLogic

Outputs

SequentialCircuit

Inputs

Clk


Example of Finite State Machine Convention: Input/Output

s0

s1

0/1

1/0

1/0 0/1


Example of Finite State MachineSynchronous Implementationlibrary IEEE;use IEEE.std_logic_1164.all;

entity state_machine isport (reset,clk,x: in

std_logic; z: out std_logic;

end state_machine;

architecture state_machine _func of state_machine is

type state_type is (state0, state1);

signal state,next_state: state_type := state0;

begin

comb_process: process (state, x)begincase state is

when state0 => if x = ‘0’ then next_state <= state1; z <= ‘1’; else next_state <= state0; z <= ‘0’; endif

when state1 => if x = ‘1’ then next_state <= state0; z <= ‘0’; else next_state <= state1; z <= ‘1’; endif

end case;end process comb_process;


Example of Finite State Machine (cont.)clk_process: processbegin-- wait until raising edgewait until (clk’event and clk = ‘1’); -- check for reset if reset = ‘1’ then

state <= state_type’left; else

state <= next_state; end if;end process clk_process;end state_machine_func;


Example of Finite State MachineAsynchronous Implementationlibrary IEEE;use IEEE.std_logic_1164.all;

entity state_machine isport (reset,clk,x: in

std_logic; z: out std_logic;

end state_machine;

architecture state_machine _func of state_machine is

type state_type is (state0, state1);

signal state,next_state: state_type := state0;

begin

output_process: process (state, x)

begincase state is

when state0 => if x = ‘1’ then z <= ‘0’; else z <= ‘1’; endif

when state1 => if x = ‘1’ then z <= ‘0’; else z <= ‘1’; endif

end case;end process output_process;


Example of Finite State Machine (cont.)next_state_process: processbegin-- set next_state depending upon -- the current state and input signalcase state iswhen state0 => if x = ‘1’ then next_state <= state0; else next_state <= state1; endif

when state1 => if x = ‘1’ then next_state <= state0; else next_state <= state1; endifend case;

end process next_state_process;

clk_process: processbegin-- wait until raising edgewait until (clk’evnet and clk =

‘1’); -- check for reset if reset = ‘1’ then

state <= state_type’left; else

state <= next_state; end if;end process clk_process;end state_machine_func;


Digression on Finite State Machines The most general model of sequential

circuit has inputs, outputs and internal states.

Two types of models are distinguished based on the way the output is generated: Mealy model and Moore model

In the Mealy model the output is a function of both the present state and the input.

In the Moore model the output is a function of present state only.

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Digital Systems Design 2