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1Agilent Technologies
Diode Modeling Strategy
From DC -> CV -> Spar -> Spectrum
Agilent Technologies
2Agilent Technologies
What we are going to model:
Spectrum
DC reverse DC forward
CV
... a real, measured diode which cannot be modeled with a simple SPICE diode model ...
S-Parameter
reverse
forward
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Introducing the SPICE Diode DC model
IS
slope ~ 1/N
RS
BVIBV
Unfortunately, this is not the reality !!!
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Therefore, we will use a sub-circuit for modeling the diode, consisting
of several diode *LEGO* pieces
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DC forward Parameter Extraction
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applied to a diode DC characteristic:higher current at a given vD means a parallel diode
DMAI
NDLOW
ΔI
RS
DMAINDLOW
vD
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RS
... and a higher voltage at a given iD means a series diode
DSAT
DMAI
N
ΔV
RS
DSAT
DMAIN iD
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3. DSAT
Developing the customized DC forward Model
1. DLO
W
4. RS
RS
DSAT
DMAINDLOW
stepping from low to high voltage bias,a real diode exhibits a
-> recombination range-> MAIN diode range-> transition to ohmic-> ohmic range⎥
⎦
⎤⎢⎣
⎡−⎟
⎠⎞
⎜⎝⎛
⋅⋅= 1
NvtiexpIS)v(ia a
a
ideal diode model:2.
DM
AIN
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.SUBCKT LED 1=A 2=C
*forward bias modelingRS 1 11 1m
DSAT 11 12 DSATDMAIN 12 2 DMAINDLOW 12 2 DLOW
*model cards.MODEL DLOW D IS=1E-20 N=3.MODEL DMAIN D IS=1E-27 N=1.MODEL DSAT D IS=.01 N=.7
.ENDS
This leads to the "DC forward" subcircuit-> The subcircuit is based
on the measurements.
-> The extraction strategy followsout of that.
-> The parameters of the 3 diodesare extracted from the individualdiode sub-range
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recombination diode modeled
MAIN diode modeled
serialdiode modeled
series resistormodeled
DC Forward Modeling step-by-step
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MAIN
in negative biased modefrom low to high current,our diode exhibits a -> MAIN diode range,-> transition to ohmic,-> ohmic range
DC reverse Modeling
ohmic
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.SUBCKT LED 1=A 2=C
*forward bias modelingRS 1 11 1mDSAT 11 12 DSATDMAIN 12 2 DMAINDLOW 12 2 DLOW
*reverse bias modelingDREV 2 21 DREVRSREV 21 1 1m
*model cards.MODEL DLOW D IS=1E-20 N=3.MODEL DMAIN D IS=1E-27 N=3.MODEL DSAT D IS=.01 N=.7.MODEL DREV D IS=1E-15 N=5
.ENDS
This enhances the subcircuit further to:
corresponding to themeasurements,the subcircuit
i.e. THE MODELis enhanced
and the model parametersare extracted.
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21
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DC reverse Parameter Extraction
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reverseseries resistor
modeled
reverse MAIN diode modeled
(pA range ignored,meas.resolution!)
DC ReverseModeling step-by-step
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CV Modeling
CJO
VJ
M
Parameter CJO corresponds to CV(Vac=0V).
M models the CV slope in the OFF state
VJ models the CV slope in the ON state
M
VvJO
ac
J
ac
C)v(Cac⎟⎠⎞⎜
⎝⎛ −
=1
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Junction Capacitance Formula
1.6p
0.8p
1.2p
1-1-3 vD (V)
CJ
0
VJ FC*VJ
slope: MJ
Cs (pF)
j
j
DM
Vv
jDs
C)v(C
⎟⎠⎞
⎜⎝⎛ −
=
1
LCRZ meter
( )( ) ( ) ⎥⎦
⎤⎢⎣
⎡++−
−=
+ J
DJJCM
C
JDs V
v*MM*F*F
C)v(CJ
111 1
For vD < FC * VJ there is :
and else :
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Linearizing the CV formula (for vD < FC*VJ):
A logarithmic conversion of equation (1) yields
ln(Cs) = ln(CJ) - MJ ln[1 - vD / VJ ] (2)
This equation can be linearized following
ylin = b + m xlin (3)when substituting:
ylin = ln(Cs) (4a)b = ln(CJ) (4b)
m = - MJ (4c)xlin = ln[1 - vD / VJ] (4d)
JM
J
D
Js
Vv1
CC
⎟⎟⎠
⎞⎜⎜⎝
⎛−
= (1)CV curve
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.SUBCKT LED 1=A 2=C
*forward bias modelingRS 1 11 1mDSAT 11 12 DSATDMAIN 12 2 DMAINDLOW 12 2 DLOW
*reverse bias modelingDREV 2 21 DREVRSREV 21 1 1m
*model cards.MODEL DLOW D IS=1E-20 N=3.MODEL DMAIN D IS=1E-27 N=3 CJO=1f M=.4 VJ=2 FC=.5.MODEL DSAT D IS=.01 N=.7 CJO=1m.MODEL DREV D IS=1E-15 N=5
.ENDS
This enhances the subcircuit further to:
QUIZ: explain why a DSAT.CJO=1m is required !!!
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CV Parameter Extraction
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CV Modeling step-by-step
Click a box around those meas. data which are below the expected FC*VJ. This is typically a ‘vac‘ which corresponds to a ‘cac.m‘ not bigger than 2-3 times CJO (y-axis intersect of ‘cac.m‘), and execute Transform ‘br_CJO_VJ_M‘.
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QUIZ:-> where is the locus curve for neg.DC bias ?-> what explains the shift of the curves starting points
to the right ?
S-parameter Modeling
vd
freq
- the starting points are determined by
the DC fitting
- the traces vs. frequency are
determined by the capacitance
-> usually, only fine-tuning is
required for the DC and CV
(not loosing DC and CV accuracy of course !!)
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S-Parameter DC-Off Modeling
The parasitic Anode-Groundand Cathode-Ground capacitors show up and will be modeled, together with their tan-delta losses (RA0, RC0).
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CC0
CA0CAC
The Off-State S-parameters have been converted to Y-pars, and the paras. caps CC0 and CA0 are fitted
NOTE: CAC was modeled in the CV-modeling section, at 1MHz. Therefore, it matches nicely (at low freq.).The C(freq) curve from S-pars, however, exhibits an increase of capacitance vs. freq. This is an indicatation for the presence of a series inductor (see S-par On-State-modeling in the next slides).
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The capacitor losses (RA0 and RC0)are fitted too, from S->Y converted S-params
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S-Parameter DC-On Modeling
The screenshot above: see the Transform README in Setup ‘Spar_mdlg/off_state‘
The diode Transit Timeand Series Inductor (Package)show up and will be modeled.
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TT=0
TT=1p
Converting S-parameters to CV plots:The influence of the diode transit time TT to the CV curve
D
DD
DTD
vig
withg*TC
∂∂
=
=
Diffusion Capacitance:
Quiz: what causes the CV curve to collapse at pos. DC bias ?
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influence of diode conductivity on CV curve
the parallel diode conductance'kills' the capacitance
rdiodeCV
RS
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DISCUSSION:-> TT shifts Sxx and Sxy for medium DC bias
TT=1p
The influence of the diode transit time TT to S-parameters
TT=0TT=0
TT=1p
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.SUBCKT LED 1=A 2=C
*forward bias modelingRS 1 11 1mDSAT 11 12 DSATDMAIN 12 2 DMAINDLOW 12 2 DLOW
*reverse bias modelingDREV 2 21 DREVRSREV 21 1 1m
*model cards.MODEL DLOW D IS=1E-20 N=3.MODEL DMAIN D IS=1E-27 N=3 CJO=1f M=.4 VJ=2 FC=.5 TT=1p.MODEL DSAT D IS=.01 N=.7 CJO=1m.MODEL DREV D IS=1E-15 N=5
.ENDS
This enhances the diode subcircuit further to:
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- the additional phase shift stems from the package series inductance
freq
LS
Package Modeling
blue: without LSred: including LS
vd
freq
LS
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.SUBCKT LED 1=A 2=C LS 1 10 1p
*forward bias modelingRS 10 11 1mDSAT 11 12 DSATDMAIN 12 2 DMAINDLOW 12 2 DLOW
*reverse bias modelingDREV 2 21 DREVRSREV 21 10 1m
*model cards.MODEL DLOW D IS=1E-20 N=3.MODEL DMAIN D IS=1E-27 N=3 CJO=1f M=.4 VJ=2 FC=.5 TT=1p.MODEL DSAT D IS=.01 N=.7 CJO=1m.MODEL DREV D IS=1E-15 N=5
.ENDS
This gives the final DC-CV-Spar-Modeling subcircuit:
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Synthesized Source
PA Bias ‘T’
Bias ‘T’
DC Source
Spectrum Analyzer
Controller
Synthesized Source
PA Bias ‘T’
Bias ‘T’
DC Source
Spectrum Analyzer
Diode
Controller
Z S
• Measurement setup for harmonic distortion (HD) characteristics (fundamental, 2nd, 3rd and 4th harmonics) for the PIN diodes
• in the ON state (ID= 10mA), the power levels are swept between -20dBm and +20dBm
• same power levels for the HD characteristics in OFF state (VD= -3V to 0V).
50Ω matching to bechecked carefully
Z L
Large-Signal RF Modelingfine-tuning the model by spectrum modeling
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OFF State Spectrum Modeling @ -1.5V-20dBm .. 20dBm power range
M
CJO
CJO models the level of the fundamentalM and VJ model the level of the harmonics
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-20dBm
va
ia
OFF-state time domain locus curve @ -1.5V
va
ia+20dBm
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ON state spectrum modeling @ 0.9V-20dBm .. 20dBm power range
TT and LSThe fundamental is modeled by the DC paramsTT and LS model the level of the harmonics
DC params
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va
ia
ON-state time domain locus curve @ 0.9V
-20dBm +20dBm
va
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Spectrum
DC reverse DC forward
CV
S-Parameter
THE FINAL RESULT DC – CV – Spar - LargeSignalRF:
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CONCLUSIONSWith the example of a diode,a typical device modeling sequence fromDC -> CV -> Spar -> Spectrum was demonstrated.
Such strategies can be applied also to- all kinds of transistors- and passive components like
spiral inductorsvaractor diodesresistors etc.
The open architecture of IC-CAP, together with ADS, is an ideal tool for modeling engineers to successfully develop accurate models quickly.