DIVISION Of CirCUiTs aND sYsTeMs · for integrated Circuits and systems (CiCs) are in three areas, namely rf integrated Circuits and systems, analog/Mixed-signal iC, and vLsi Design

DIVISION OfCirCUiTs aND sYsTeMs

INTRODUCTION

The Division of Circuits and Systems continues to do well in attracting external research funding especially from the IC design industry despite the current economic slowdown. This is because IC design companies are more agile in adapting to fast changing market environment and are more resilient in weathering the inherently cyclical global downturn of the electronic industry. In �008, we work with Chartered Semiconductor Manufacturing Ltd, Panasonic, MediaTek, Broadcom and Infineon, just to name a few, to provide a total of near 50 training opportunities under the SMP (Specialist Manpower Programme) and the JIP (Joint Industry Postgraduate Programme) in Integrated Circuit (IC) Design for our undergraduate and postgraduate students. With externally funded research infrastructures such as Advanced RfIC (aRfic) and Electromagnetic Effects Research Laboratory (EMERL), as well as the establishment of Institute for Sustainable Nanoelectronics (ISNE), the division continues to build up its core research competency in Low-voltage Low-Power system-on-Chip (soC). The division’s strong research in SoC has resulted in high quality publications in top journals. In �00�-�007, in terms of total number of publications, we ranked �st in IEEE Transactions on Circuits and Systems I and II, �0th in IEEE Transactions on Microwave Theory and Techniques and �4th in IEEE Transactions on VLSI Systems.

Through strong collaborating with our research partners, several research breakthroughs have been achieved by our colleagues. These breakthroughs enable us to realize SoC in much smaller size and much lower power consumption.

One of the obstacles for size reduction in SoC is the antenna. Emerging highly-integrated radios require novel antenna solutions for efficient transmission and reception of radio signals for wireless communications. Together with A*STAR-SIMTech, A/P Zhang Yue Ping, has developed antenna elements that can be integrated in chip package. The group has overcome the design challenges to handle interconnects from the radio die to the integrated antenna and still maintain very good isolation performance between the antenna radiation and on-chip passives. This antenna-in-Package (aiP) technology that integrates an antenna with a single-chip radio die into a standard surface mounted device represents an innovative and important development in the miniaturization of radio systems in recent years. The AiP technology originated from the division was featured on the front cover page of Antenna Systems and Technology Magazine (USA) as an antenna technology breakthrough. It was also highly regarded as an innovative development in antenna technology

Antenna-in-Package (AiP) technology for UWB applications

AiP technology for �0-GHz applications

by European Network of Antenna Excellence. One paper on the AiP received the Best Paper Prize at the �rd EEE Workshop on Antenna Technology held in Cambridge, UK.

Another challenge of SoC is low-power design. Working closely with Prof. Lars Wanhammar of Department of Electrical Engineering, Linköping Univeristy, Sweden, our colleagues A/P Gwee Bah Hwee and A/P Joseph Chang investigate and implement design methodologies for low-power asynchronous-logic digital systems. The asynchronous-logic digital design approach is an emerging design methodology, as opposed to the prevalent synchronous-logic approach. Asynchronous-logic digital systems without global clock signal offer potential advantages over its synchronous counterpart, including higher speed, lower energy dissipation and lower electromagnetic interference. They intend to realize a low-power digital signal processor (DSP) embodying these design methodologies targeted for low power portable biomedical and communication applications. It is going to be the world’s first asynchronous general purpose DSP.

DIVISION Of CIRCUITS AND SYSTEMS

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NANYANG TECHNOLOGICAL UNIVERSITY • SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING

Another research collaboration with Panasonic Singapore Laboratories Pte. Ltd. (PSL), initiated by A/P Chang Chip Hong, also aims to look into optimized algorithms and architectures for low voltage, low power custom-made arithmetic circuits to address the digital signal processing challenges arising from the stringent goals of increasing data rate, integration density and power budget in the wireless personal area network devices. A fully custom-made VLSI chip has been fabricated. A new algorithm for scalar product computation is mapped to a novel full bit parallel architecture of macrocell featuring low interconnect complexity, improved power efficiency and cost effective silicon utilization.

The ��5�0 transistors IP Core prototyped on CSM 0.�8µm CMOS process technology occupied �4�0µm by �5�0µm of core area, and ��00µm by �900µm of total chip area. It dissipates �5.0mW @ 50MHz �.8V and is capable of computing �� full width signed multiply-accumulations of ��-bit operands at �.9�ns @ �.8V. Several new design methodologies for optimizing the logic complexity and logic depth of multiplier-less fIR filters for wireless communications have been developed. An electronic design automation tool has also been developed to automatically generate the synthesizable VHDL codes from the filter specifications.

Microphotograph of the asynchronous-logic DSP Arithmetic-logic units

Packaged IC of the asynchronous-logic DSP Arithmetic-logic units

Low-voltage, Low-power Application-specific Arithmetic Circuits for High-Performance DSP


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The research activities of the Centre for integrated Circuits and systems (CiCs) are in three areas, namely rf integrated Circuits and systems, analog/Mixed-signal iC, and vLsi Design and embedded systems. Most projects deal with the design and analysis of devices, circuits and sub-systems of the final SoC (System on Chip) product with or without the embedded software. The main focuses are in high speed and low power performance. The ultimate achievement will be the ultra low power circuits and systems which can be powered by alternative energy harvesting storage devices such as kinetic, electromagnetic and solar cells for certain biomedical applications. With the push for green electronics, research in energy harvesting storage devices and circuits is expected to become a new major activity of the Centre. Some of the latest projects and significant achievements in �008 are described below.

Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

In a wireless Rf transceiver, the

CENTRE fOR INTEGRATED CIRCUITS AND SYSTEMS

Phase Locked Loop (PLL) frequency synthesizer is used as a stable local oscillator for the up and down frequency conversion between the baseband and Rf signals. This sub-system can consume one third of the total power consumed by the whole transceiver. The dual modulus prescaler consumes more than one third of the power used by the PLL. In the Giga-Hertz range, two types of CMOS circuits namely, true single phase clock (TSPC) and extended true single phase clock (E-TSPC) are used for designing frequency prescalers, where the TSPC consumes less power at the expense of lower speed. Based on our study, two new low power and improved speed TSPC �/� prescalers are proposed and silicon-verified. Compared with the conventional TSPC architectures designed under the same 0.�8µm CMOS technology at supply voltage of �.8V, both proposed �/� prescalers improve the operating speed by �.� times up to 5 GHz. The extremely low power consumption is achieved by radically decreasing the sizes of transistors and optimizing the embedded logic gates around the

D flip-flop (Dff) as in the Design I prescaler, and furthermore allowing the Dff to sleep when it is not in use as in the Design II prescaler. The accompanying table shows a reduction of the power consumption by almost 50% in Design I and �7% in Design II when compared to other state-of-the-art designs. A divide-by-��/�� dual modulus prescaler has also been implemented with the Design-II �/� prescaler using a Chartered 0.�8µm CMOS technology, and is capable of operating up to 4.5 GHz with a power consumption of �.4 mW.

Die photograph of the proposed prescalers

TaBLe i. PerfOrMaCe Of DiffereNT PresCaLers

Design Parameters Prescaler in [1] Prescaler in [2]Conventional TSPC 2/3 Prescaler

Proposed Design i of 2/3 Prescaler

Proposed Design ii of ultra low power 2/3 Prescaler

Process (µm) 0.25 0.18 0.18 0.18 0.18

Supply voltage(v) 2.5 1.8 1.8 1.8 1.8

Max. Frequency (ghz) (sim/measured ) 6.5 ghz / -- 8 ghz / -- 4.2 ghz / -- 5.5 ghz / 4.9

ghz5.5 ghz / 4.9

ghz

Power (mw) (sim/measured) (2.4ghz)

Divide-by-2 1.875/ -- 1.8/ -- 1.42/ -- 0.923/1.03 0.252/ 0.306

Divide-by-3 2.178/ -- 1.89/ -- 1.35/ -- 0.369/ 0.445 0.387/ 0.461

[1] X. P. yu, M. A. Do, w. M. lim, K. S. yeo and j. g. Ma, “Design and optimization of the extended True Single-Phase Clock-Based Prescaler”, ieee Trans. on Microwave theory and Techniques, vol. 54, no. 11, November 2006.

[2] S. Pellerano, S. levantino, C. Samori, and A. l. lacaita, “A 13.5-mw 5 ghz frequency synthesizer with dynamic-logic frequency divider”, ieee j. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb. 2004.


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A Possible Reality on battery-free Low-power Portable Electronics

The idea of harvesting electromagnetic energy and converting it to useful DC power is not new and has been researched in the context of high power beaming in the �950s. However, due to the concern of biological hazards, high power wireless transmissions are regulated by the telecommunication authorities. Because the transmitted power is restricted, harvesting radiated electromagnetic energy from the wireless transmission and converting it to a DC voltage comparable to a standard battery is a challenging task. The maximum converted DC voltage using the conventional harvesting technique, such as rectenna (antenna-rectifier combined circuit) arrays, could achieve at most a few hundred mV even with carefully designed matching between the antenna and the diode, due to the inherent losses in the rectification process. This voltage level is only good enough for extremely low power sensors but is insufficient for most practical electronic devices that operate at � V and above. We have realized a novel electromagnetic energy harvesting concept through a working circuit. The circuit designed and fabricated is capable of converting low power electromagnetic energy to a DC voltage level of more than �.5 V in a short time. The attached figures show the schematic of our circuit and the experimental output voltage of our circuit when it is placed in the open air with an EM source of 80MHz and 0.5�W output power at �m away from the circuit.

Antenna 1

Antenna 2

voltageAmplifier 1

voltageAmplifier 2

voltageAmplifier NAntenna N

incidentelectromagneticwave

Chargeleakage lock

Circuit

Circuit realization of the low power electromagnetic energy harvesting system

Output voltage result for charging system operating at �m in the ambient.


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Microphotograph of the PPf based frequency multiplier.

Measured Performance of frequency multiplier prototype.

Low-Jitter Frequency Multiplier for High-Speed Mixed-Signal Chips

Timing jitter is an important design parameter for most of the high-speed mixed-signal circuits and systems. A low-jitter frequency multiplier is one of the critical components for an integrated system design. Applications such as precision clock for high-speed data converters and clock generator for microprocessor/microcontroller based designs are good examples. Conventional phase-locked loop (PLL) clock multiplier architecture suffers from the jitter accumulation effect due to its narrow loop bandwidth required for the loop stability. Although improved jitter performance can be achieved through the use of delay locked loop (DLL) clock multiplier architecture, it still suffers from jitter accumulation in the cascade of the delay chain. An innovative approach is explored in the research. To circumvent the problem, the cascade structure of the delay chain, that defines the clock edges of the crystal oscillator for frequency multiplication, will be replaced with a passive RC polyphase filter having the low thermal noise characteristic. To reduce the static phase errors arising from the polyphase filter and devices mismatch effect, an analog phase error calibration circuit that is independent of delay sensing mismatch, is employed. The circuit technique leads to a new polyphase filter (PPf) clock multiplier. The preliminary experimental results of the prototype have shown that the unconventional architecture exhibits low-power low-jitter performance metrics, suggesting the potential of work for high-speed mixed-signal chip design.

Process Technology CMoS 0.13µm

Power Consumption @ 1.5 V 16.4 mw

Input/Output Frequency 25 Mhz/ 200 Mhz

Operating Frequency Range 136 Mhz – 280 Mhz

Rms Output Jitter 2.46 ps rms

Peak-to-peak Output Jitter 18.65 ps peak-to-peak

Maximum Phase Error 2.4 ps

Silicon Area 0.49 mm2


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STAff MEMBERS

1st row (From left to right)

Head of Division

1. yeo Kiat Seng Associate Professor

2. Alper Cabuk Teaching Fellow

3. Boon Chirn Chye Assistant Professor

4. Chan Pak Kwong Associate Professor

5. Chang Chip hong Associate Professor

6. Chang, joseph Sylvester * Associate Professor

7. Do Manh Anh Professor

8. goh wang ling Associate Professor

9. gwee Bah hwee Associate Professor

10. ho Duan juat Associate Professor

11. jong Ching Chuen Associate Professor

12. Koh liang Mong Associate Professor

13. Kong Zhi hui Teaching Fellow

2nd row (From left to right)

14. lam ying hung, yvonne Associate Professor

15. lau Kim Teen Associate Professor

16. lim Meng hiot Associate Professor

17. Ng lian Soon Associate Professor

18. ong Keng Sian, vincent Associate Professor

19. See Kye yak Associate Professor

20. Shi Xiaomeng Teaching Fellow

21. Siek liter @ hsueh liter Associate Professor

3rd row (From left to right)

22. Tan Cher Ming Associate Professor

23. Tan Meng Tong Assistant Professor

24. Tang hung Kei * Associate Professorial Fellow

25. Tiew Kei Tee Assistant Professor

26. yu yajun Assistant Professor

27. Zhang yue Ping Associate Professor

* Picture not available

1. 2. 3. 4. 5. 7. 8.

14. 15.


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STAff MEMBERS

9. 10. 11. 12. 13.

16. 17. 18. 19. 20. 21.

22. 23. 25. 26. 27.


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RESEARCH INTERESTS

1 . Boon Chirn Chye Assistant Professor rFiC devices, Circuits and systems design, rFiC biomedical, Consumer electronic.

2. Alper Cabuk Teaching Fellow rF iC Design, high Frequency Clock & Data recovery Circuits, SoNeT Systems

3. Chan Pak Kwong Associate Professor Sensor circuits and systems, Mixed-signal iC design.4. Chang Chip hong Associate Professor Computer arithmetic, vlSi design, Design automation, Digital

signal processing.5. Chang, joseph Sylvester Associate Professor Acoustics, Audiology, electronics, iC design, Analogue and

digital signal processing, Biomedical engineering,Psychophysics.6. Do Manh Anh Professor r.F. circuits and systems, Mixed-signal iC design, Acoustics.

7. goh wang ling Associate Professor Device processing, Device characterization and low-power digital iC design.

8. gwee Bah hwee Associate Professor Asynchronous & digital Class-D amplifier, iC designs, Acoustic noise reduction.

9. ho Duan juat Associate Professor video coding, System level digital design, ASiC design.

10. jong Ching Chuen Associate Professor high-level synthesis, Parallel computation and reconfigurable systems.

11. Koh liang Mong Associate Professor Machine vision, energy saving electronic converters.

12. Kong Zhi hui Teaching Fellow Design of memory circuits & systems, low-voltage low-power vlSi subsystem design, Probabilistic CMoS design

13. lam ying hung, yvonne Associate Professor Mixed-signal iC design, Analogue design automation.

14. lau Kim Teen Associate Professor low power iC design, Self-timed CMoS circuits,Sub-threshold CMoS circuits.

15. lim Meng hiot Associate Professor Computational intelligence, embedded systems, Ai in finance, fuzzy/neural hardware, combinatorial optimization.

16. Ng lian Soon Associate Professor Analogue CMoS circuits, DAC/ADC, Micro-power circuits, Analogue bipolar circuits.

17. ong Keng Sian, vincent Associate Professor Materials and device characterization, Analysis and modeling; electron beam techniques; eBiC metrology.

18. See Kye yak Associate Professor Computational electromagnetics, electromagnetic compatibility and signal integrity.

19. Shi Xiaomeng Teaching Fellow Device Modeling, iC Packaging and Testability of vlSi

20. Siek liter @ hsueh liter Associate Professor low-power low-voltage analog/mixed signal CMoS/Bipolar iC design.

21. Tan Cher Ming Associate Professor Nanoelectronics, ulSi interconnect reliability, wafer bonding, reliability and maintenance engineering.

22. Tan Meng Tong Assistant Professor vlSi design, Class D amplifiers, Analog and digital signal processing, Biomedical engineering.

23. Tang hung Kei Associate Professorial Fellow

Technopreneurship, Management of innovation and technology.

24. Tiew Kei Tee Assistant Professor Analog and mixed-signal iC design, delta-sigma modulators, bio-instrumentation.

25. yeo Kiat Seng Associate Professor Device modeling, rFiC design, low-voltage low-power iC design.

26. yu yajun Assistant Professor vlSi digital signal processing, vlSi circuits and systems design.

27. Zhang yue Ping Associate Professor wireless chip area network, single-chip radio, and radio bioelectronics.


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MEng & PhD DEGREES AWARDED IN �008

S/No. Project Title Student Supervisor/Co-Supervisor

MEng

1. voltage reference Circuits for low voltage Applications Chia leong yap goh wang ling ram Singh rana

2. Development of Power line Communications System with low electromagnetic radiation

Kamarul Azran Bin Ashari

See Kye yak

3. Analysis and Design of Analogue Class D Amplifier output Stages

Kwek Boon Kheng lawrence

Chang, joseph Sylvester Tan Meng Tong

4. The Multi-step Dynamic reference Analog-to Digital Converter

li Danping Siek liter

5. Critical investigation of Common-Mode radiation Mechanism from Power line Communication Network

Manish oswal See Kye yak

6. Modulo Adders, Multipliers and Shared-moduli Architectures for Moduli of Type {2n-1,2n,2n+1}

Shibu Menon Chang Chip hong

7. low-voltage ghz-range Frequency Synthesizer Sun yuan Siek liter

8. Novel Transistor Structures for Future Deep Submicron MoS Applications

Theng Ah leong goh wang ling lo guo-Qiang Patrick

PhD

1. rectilinear Polygon Partitioning for region Coverage using uAvs

Agarwal Amit lim Meng hiot

2. efficient and Accurate extraction of Full-wave equivalent Circuit for Printed Circuit Structures

Chua eng Kee See Kye yak

3. efficient Digital Beamforming for Medical ultrasound imaging

gao Changqing wong Moon Chung, eddie

4. Design and Analysis of redundant Binary Booth Multipliers

he yajuan Chang Chip hong

5. high Speed low voltage low Power embedded Analog-to-Digital Converters For wideband Transceivers

jiang Shan Do Manh Anh

6. CMoS Building Blocks for 10+ gb/s Clock Data recovery Circuit

liu haiqi goh wang ling

7. Design of CMoS Broadband Transimpedance Amplifiers for 10 gBit/s optical Communications

lu Zhenghao yeo Kiat Seng

8. Scalable and Configurable Array Architectures for Matrix Computation

luo jianwen jong Ching Chuen

9. A Study on electromigration by Driving Force Approach for Submicron Copper interconnect

roy Arijit Tan Cher Ming Chen Xian Tong

10. Parallel Memetic Algorithms for Solving large Scale Combinatorial optimization Problems

Tang jing lim Meng hiot

11. high level Synthesis of vlSi Systems for low Power Xing Xianwu jong Ching Chuen


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SELECTED PUBLICATIONS IN �008

1. A. v. Do, C. C. Boon, M. A. Do, K. S. yeo and A. Cabuk, “A Subthreshold low-Noise Amplifier optimized for ultra-low-Power Applications in the iSM Band”, ieee Trans. on Microwave Theory and Techniques, vol. 56, no. 2, pp. 286-292, February 2008.

2. P. K. Chan and j. Cui, “Design of Chopper-Stabilized Amplifiers with reduced offset for Sensor Applications”, ieee Sensors journal, vol. 8, no. 12, pp. 1968-1980, December 2008.

3. D. y. Chen and P. K. Chan, “An intelligent iSFeT Sensory System with Temperature and Drift Compensation for long Term Monitoring”, ieee Sensors journal, vol. 8, no. 12, pp. 1948-1959, December 2008.

4. j. K. yin and P. K. Chan, “A low-jitter Polyphase Filter Based Frequency Multiplier with Phase error Calibration”, ieee Trans. on Circuits and Systems, Part ii, vol. 55, no. 7, pp. 663-667, july 2008.

5. C. h. Chang, j. Chen and A. P. vinod, “information Theoretic Approach to Complexity reduction of Fir Filter De-sign,” ieee Trans. on Circuits and Systems, Part i, vol. 55, no. 8, pp. 2310-2321, September 2008

6. A. Cui, C. h. Chang and S. Tahar, “iP watermarking using incremental Technology Mapping at logic Synthesis level,” ieee Trans. on Computer-Aided Design of integrated Circuits and Systems, vol. 27, no. 9, pp 1565-1570, September 2008.

7. y. he and C. h. Chang, “A Power-Delay efficient hybrid Carry-lookahead/Carry-Select Based redundant Binary to Two's Complement Converter,” ieee Transactions on Circuits and Systems, part i, vol. 55, no. 1, pp. 336-346, February 2008.

8. S. jiang, M.A. Do, K.S. yeo and w.M. lim “An 8-bit 200 MSample/s Pipelined ADC with Mixed Mode Front-end S/h Circuit”, ieee Trans. on Circuits and Systems, Part i, vol. 55, no. 6, pp. 1430-1440, july 2008.

9. X. P. yu, w. M. lim, M. A. Do, X. l. yan and K. S. yeo, “A low Power CMoS Phase-Switching Prescaler for 1.8-2.4 ghz wireless Communications”, accepted, Analog integrated Circuits and Signal Processing, 2008.

10. X. P. yu, w. M. lim, M. A. Do, X. l. yan and K. S. yeo, “6.1 ghz 4.6 mw CMoS Divide-by-55/56 Prescaler”, accepted, ieT electronics letters, 2008.

11. A. l. Theng, w. l. goh, g. Q. lo, l. Chan and C. M. Ng, “Dual Nanowire Silicon MoSFeT with Silicon Bridge and TaN gate”, accepted, ieee Trans. on Nanotechnology, 2008

12. K. S. yeo, w. l. goh, M. w. Phyu, A. S. ong, and y. K Khaing, “ high-Performance low-Power Novel Single-/Dou-ble-edge explicit-Pulsed Triggered Flip-Flops via output Feedback”, accepted, ieT Proc. Computers and Digital Techniques, 2008.

13. B.h. gwee, j.S. Chang, y. Shi, C.C. Chua and K.S. Chong, “A low-voltage Micropower Asynchronous Multiplier with Shift-Add Multiplication Approach”, accepted, ieee Trans. on Circuits and Systems, Part i, 2008.

14. v. Adrian, j.S. Chang and B.h. gwee, “A low voltage Micropower Digital Class D Amplifier Modulator for hearing Aids”, accepted, ieee Trans. on Circuits and Systems, Part i, 2008.

15. C.F. law, B.h. gwee and j.S. Chang, “Asynchronous Control Network optimization using Fast Minimum Cycle Time Analysis”, ieee Trans. on Computer-Aided Design of integrated Circuits and Systems, vol. 27, no. 6, pp. 985-998, june 2008.

16. F. Xu, C. h. Chang and C. C. jong, ”Contention resolution - A New Approach to versatile Subexpressions Sharing in Multiple Constant Multiplications”, ieee Trans. on Circuits and Systems, Part i, vol. 55, no. 2, pp. 559-571, March 2008.

17. w. j. yang, y. Zhou and K. T. lau, “low Power Adiabatic Programmable logic Array with Single Clock iAPDl”, accepted, journal of Circuits, Systems and Computers, 2008.


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18. S. ramakrishnan and K. T. lau, “improved Dynamic Current Mode logic for low Power Applications”, journal of Circuits, Systems and Computers, vol. 17, no. 2, pp. 183-190, 2008.

19. K. K. lim, y. S. ong, M. h. lim and A. Agarwal, ”hybrid Ant Colony Algorithm for Path Planning in Sparse graphs”, accepted, Soft Computing journal, 2008.

20. o. Kurniawan and v.K.S. ong, ”Charge Collection from within a Collecting junction well”, ieee Trans. on electron Devices, vol. 55, no. 5, pp. 1220-1228, May 2008.

21. T. S. Pang, P. l. So, K.y. See and A. Kamarul, “Modeling and Analysis of Common-Mode Current Propagation in Broadband Power line Communication Networks”, ieee Trans. on Power Delivery, vol. 23, no. 1, pp 171-179, janu-ary 2008.

22. B. hu, K. y. See and w. y. Chang, “Measurement of eMi Suppression of Ferrite Core under realistic operating Con-ditions”, ieee eMC Society Newsletter, no. 218, pp. 60-65, August 2008.

23. y. ling and K. y. See, “Feasibility Study of using Porous Aluminum for Architectural electromagnetic Shielding”, accepted, ieee Trans. on electromagnetic Compatibility, 2008.

24. h. Q. liu, l. Siek, w. l. goh and w. M. lim, “A 7-ghz Multiloop ring oscillator in 0.18-µm CMoS Technology”, Ana-log integrated Circuits and Signal Processing, vol. 56, no. 3, pp. 179-184, September 2008.

25. C. Baudot and C. M. Tan, “Solubility, Dispersion and Bonding of Functionalized Carbon Nanotubes in epoxy resins, accepted, international journal of Nanotechnology, 2008.

26. C. M. Tan and N. raghavan, “A Framework to Practical Predictive Maintenance Modeling for Multi-State Systems”, reliability engineering and System Safety, vol. 93, no. 8 pp. 1138-1150, August 2008.

27. r. Arijit and C. M. Tan, ”very high Current Density Package level electromigration Test for Copper interconnects”, journal of Applied Physics, vol. 103, no. 9, pp. 093707-1-7, May 2008.

28. C. C. lim, K. S. yeo, K. w. Chew, A. Cabuk, j. M. gu, S. F. lim, C. C. Boon and M. A. Do, “Fully Symmetrical Mono-lithic Transformer (True 1:1) for Silicon rFiC”, accepted, ieee Trans. on Microwave Theory and Techniques, 2008.

29. X. Shi, K. S. yeo, j.g. Ma, M. A. Do and e. li, “Complex Shaped on-wafer interconnects Modeling for CMoS rFiCs”, ieee Trans. on very large Scale integration Systems, vol. 16, no. 7, pp. 922-926, july 2008.

30. K. S. yeo, Z. h. Kong, N. Nishant, h. Fu and w. Zeng, “integrated Circuit Design research ranking for worldwide universities”, journal of Circuits, Systems and Computers, vol. 17, no. 1, pp. 141-167, February 2008.

31. j, h. Cheong, y. y. h. lam, K. T. Tiew and l. M. Koh, “Sigma-Delta receive Beamformer Based on Cascaded recon-struction for ultrasound imaging Application”, ieee Trans. on ultrasonics, Ferroelectrics, and Frequency Control, vol. 55, no. 9, pp. 1935-1946, September 2008.

32. y j. yu, y. C. lim and D. Shi, “low Complexity Design of variable Bandedge linear Phase Fir Filters with Sharp Transition Band”, accepted, ieee Trans. on Signal Processing, 2008.

33. y. P. Zhang, “enrichment of Package Antenna Approach with Dual Feeds, guard ring, and Fences of vias”, accept-ed, ieee Trans. on Advanced Packaging, 2008.

34. y. P. Zhang, j. j. wang, Q. li and X. j. li, “Antenna and Transmit/receive Switch for Single-Chip radio Transceivers of Differential Architecture”, accepted, ieee Trans. on Circuits and Systems, Part i, 2008.

35. K. yang, w. y. yin, j. l. Shi, j. F. Mao and y. P. Zhang, “A Study of on-Chip Stacked Multi-loop Spiral inductors”, ieee Trans. on electron Devices, vol. 55, no. 11, pp. 3236-3245, November 2008.

SELECTED PUBLICATIONS IN �008


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Documents

DIVISION Of CirCUiTs aND sYsTeMs · for integrated Circuits and systems (CiCs) are in three areas, namely rf integrated Circuits and systems, analog/Mixed-signal iC, and vLsi Design