DLD&CO COURSE PLAN D.SRAVANTHI - J. B. Institute of

FACULTY DETAILS:

Name of the Faculty:: D.Sravanthi

Designation: Assistant professor

Department:: Information Technology

COURSE DETAILS

Name Of The Programme:: Batch::

Designation::

Year 2013-2014 Semester II year/ I-sem

Department:: IT

Title of The Subject : compute organization & digital logic design

Subject Code: 53037

No of Students :98

COURSE PLAN

2013-14

Regulation: R11

COURSE PLAN

2013-14

Regulation: R11

FACULTY DETAILS:

Name of the Faculty:: D.Sravanthi Designation: Assistant professor


1. TARGET

a) Percentage Pass:100%

b) Percentage I class:85-90%

2. COURSE PLAN

(Please write how you intend to cover the contents: i.e., coverage of Units by lectures, guest lectures, design exercises, solving numerical problems, demonstration of models, model preparation, or by assignments, etc.)

3. METHOD OF EVALUATION

3.1. Continuous Assessment Examinations (CAE 1, CAE 2)

3.2. Assignments / Seminars

3.3. Mini Projects

3.4. Quiz

3.5. Term End Examination

3.6. Others

4. List out any new topic(s) or any innovation you would like to introduce in teaching the subject in this Semester.

Signature of HOD Signature of Faculty Date: Date:

FACULTY DETAILS:




Guidelines for Preparing the Course:

Course Description:

The objective of this course is to master the basic hardware and software issues of computer organization. At the end of the course, the students are expected to know the inner workings of a computer and have the ability to analyze the hardware and software issues related to computers and the interface between the two. This allows the students to work out the tradeoffs involved in designing a modern computer.

Course Objectives:

1. Students will learn the fundamentals of computer organization and its relevance to classical

and modern problems of computer design 2. Students will be able to identify where, when and how enhancements of computer performance

can be accomplished. 3. Students will learn the sufficient background necessary to read more advance texts as well as

journal articles on the field. 4. Student will see how to use concepts of computer organization in real-life settings using

various PC performance improvements. 5. Students will also be introduced to more recent applications of computer organization in

advanced digital systems. 6. Student should be able to solve the binary conversion and logical gate digram and flip flops.

Learning Outcomes:

1. Student will learn the concepts of computer organization for several engineering applications. 2. Student will develop the ability and confidence to use the fundamentals of computer

organization as a tool in the engineering of digital systems.

GUIDELINES TO STUDY THE SUBJECT

2013-14

Regulation: R11

FACULTY DETAILS:




On completion of this Subject / Course the student shall be able to:

S.No. Objectives Outcomes

1. The Students will learn the fundamentals of computer organization and its relevance to classical and modern problems of computer design

2.

Students will be able to identify where, when and how enhancements of computer performance can be accomplished.

3.

Students will learn the sufficient background necessary to read more advance texts as well as journal articles on the field.

4.

Student will see how to use concepts of computer organization in real-life settings using various PC performance improvements.

5.

Students will also be introduced to more recent applications of computer organization in advanced digital systems.

6. Introduce the concept of digital and binary systems

7. Student should be able to design and analyze combinational logic circuits and sequential logic circuits

8. Understand the basic software tools for the design and implementation of digital circuits and systems

Signature of Faculty Date:

Note: For each of the OBJECTIVE indicate the appropriate OUTCOMES to be achieved.

Kindly refer Page 16, to know the illustrative verbs that can be used to state the objectives.

COURSE OBJECTIVES

2013-14

Regulation: R11

4

FACULTY DETAILS:




The expected outcomes of the Course / Subject are:

S.No. General Categories of Outcomes Specific Outcomes of the Course

A. An ability to apply knowledge of mathematics,

science, and engineering

B. An ability to design and conduct experiments, as

well as to analyze and interpret data

An ability to design a system, component, or

C. process to meet desired needs within realistic

Constraints such as economic, environmental,

social, political, ethical, health and safety,

Manufacturability and sustainability

D. An ability to function on multi-disciplinary teams

E. An ability to identify, formulate, and solve

engineering problems

F. An understanding of professional and ethical

responsibility

G. An ability to communicate effectively

The broad education necessary to understand the

H. impact of engineering solutions in a global,

economic, environmental, and societal context

I. A recognition of the need for, and an ability to

engage in life-long learning

J. A knowledge of contemporary issues

An ability to use the techniques, skills, and

K. modern engineering tools necessary for

engineering practice.

Objectives – Outcome Relationship Matrix (Indicate the relationships by � mark).

Outcomes A B C D E F G H I J K

Objectives

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

5

COURSE OUTCOMES

2013-14

Regulation: R11

FACULTY DETAILS:




The Schedule for the whole Course / Subject is::

S. No. Description Duration (Date) Total No.

From To of Periods

1.

Unit-I: Basic structure of computers: Introduction about computers, computer types, functional units, Basic operational concepts, Bus structures,softwares,performance,multiprocessors,multicomputers, computer generations, Binary numbers, Fixed point Representation, Floating point Representation, Number base conversions, Octal and Hexa decimal numbers, Complements ,signed binary numbers, Binary codes. 3/7/2013 16/7/2013 11

2.

Unit-II:Digital logic circuits-I: Basic logic function, Logic Gates, Universal Logic Gates, Minimization of Logic expression,FlipFlops 17/7/2013 31/7/2013 11

3.

Unit-III:Digital logic circuits-II: Registers, Shift Registers, binary Counters,Decoders,Multiplexers, Programmable Logic Devices 1/8/2013 8/8/2013

07

4.

Unit-IV: COMPUTER ARITHMETIC: Algorithm for Fixed point and Floating point Addition and subtraction, multiplication Algorithms, Division Algorithms, Hardware Implementation of arithmetic and Logic Operation, High performance Arithmetic. 13/8/2013 30/8/2013 11

5.

Unit-V:Instruction Set and Addressing: Memory Locations and Address, Machine Address and Sequencing, various addressing modes, Instruction formats, Basic machine Instructions, IA-32 Pentium Examples. 2/9/2013 12/9/2013 08

6.

Unit-VI: PROCESSOR ORGANIZATION: Introduction to CPU, Register Transfers, Execution of 13/9/2013 25/9/2013 09

COURSE SCHEDULE

2013-14

Regulation: R11

instructions, Multiple Bus organization, Hardwired control, Micro Programmed control.

7

Unit-VII: MEMORY ORGANIZATION: Concept Of Memory, RAM ,ROM memories, Memory Hierarchy, Cache Memories, Virtual Memory, Secondary Storage, Memory management Requirements, 26/9/2013 9/10/2013

09

8

Unit-VIII: INPUT-OUTPUT ORGANIZATION: Introduction to I/O ,interrupts Hardware, Enabling and Disabling interrupts, Device Control, Direct Memory access,Buses,interface circuits, standard I/O interfaces. 10/10/2013 18/10/2013 07

Total No. of Instructional periods available for the course: 73

Text Books (TB)

TB1: COMPUTER ORGANIZATION-Carl Hamacher, Zvonko Vranesic, safwat zaky, 5th

edition,

McGraw hill.

TB2: COMPUTER ARCHITECTURE AND ORGANIZATION- an integrated approach, miles

murdocca, Vincent heuring, second edition, wiley india

TB3: COMPUTER SYSTEMS ARCHITECTURE-M.Moris mano, 3rd

edition pearson

Suggested / Reference Books (RB)

RB1: computer organization and architecture- william stallings 6th

edition pearson

RB2:computer organization and design- david a.paterson and john l.hennessy-elsevier

RB3:fundamentals or computer organization and design- sivarama dandamudi springer int.

edition

RB4: digital design – 3rd

edition m.morris mano, pearson education/phi

RB5: fundamentals of logic design, roth, 5th

edition thomson

SCHEDULE OF INSTRUCTIONS

2013-14

UNIT - I Regulation: R11

FACULTY DETAILS:




The Schedule for the whole Course / Subject is:: DLD&CO

SI. No. of Objectives & References

Date Topics / Sub - Topics

Outcome (Text Book, Journal…)

No. Periods

Nos. Page No___ to ___

1

3/7/2013

1 Introduction about computers, computer types. TB-1

2

4/7/2013

3 functional units TB-1&TB-2

3

5/7/13

4

Basic operational concepts

TB-1

4

8/7/2013

5

Bus structures, software, performance

TB-1

5

9/7/13

6

Multiprocessors, multi computers

TB-1

6

10/7/13

7

Computer generations, binary numbers

TB-1

7

11/7/13

8

Fixed point representation, floating

point representation TB-1

8

12/7/13

10

Number base conversions, octal and

hexadecimal numbers, complements TB-1

9

16/7/13

11

Signed binary numbers, binary codes

Signature of Faculty Date

Note: 1. ENSURE THAT ALL TOPICS SPECIFIED IN THE COURSE ARE MENTIONED. 2. ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED BOLDLY. 3. MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUT COME NUMBERS AGAINST EACH TOPIC.


2013-14

UNIT - II Regulation: R11

FACULTY DETAILS:

Name of the Faculty:: D. Sravanthi







No. Periods


1

17/7/13

2

Basic logic functions,

TB-1

2

18/7/13

2

Logic gates

TB-1

3

23/7/13

2

Universal logic gates

TB-1

4

25/7/13

2

Minimization of logic expressions

TB-1

TB-1

5

3

Flip flops

TB-1


Note: 1. ENSURE THAT ALL TOPICS SPECIFIED IN THE COURSE ARE MENTIONED. 2. ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED BOLDLY.

MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUT COME NUMBERS AGAINST EACH TOPIC.


2013-14

UNIT - III Regulation: R11

FACULTY DETAILS:








No. Periods


1

1/8/13 1

Registers

TB-1&TB-3

2

2/8/13

2

Shift registers,

TB-1&TB-3

3

6/8/13

1

binary counters ,Decoders

TB-1&TB-3

4

7/8/13

1

multiplexers

TB-1&TB-3

5

8/8/13

2 Programmable logic devices TB-1&TB-3





2013-14

UNIT - IV Regulation: R11

FACULTY DETAILS:








No. Periods


1

13/8/13

1 Algorithms for fixed point addition with an examples TB-1&TB-3

2

14/8/13

1 Subtraction algorithm with an Examples TB-1&TB-3

3

15/8/13

1 Multiplication algorithm with an examples TB-1&TB-3

4

16/8/13

1 Division algorithm with an examples TB-1&TB-3

5

19/8/13

1 Floating point addition algorithm TB-1&TB-3

6

20/8/13

1 Subtraction and multiplication algorithm for floating point TB-1&TB-3

7

21/8/13

1 Division algorithm for floating point and with an example TB-1&TB-3

8

23/8/13

1 High Performance arithmetic TB-1&TB-3

9

24/8/13

1 logic operations TB-1&TB-3

10

30/8/13 1 Hardware implementation of arithmetic TB-1&TB-3





2013-14

UNIT - V Regulation: R11

FACULTY DETAILS:




The Schedule for the whole Course / Subject is:: DLD &CO




No. Periods


1

2/9/13 1

Memory locations and addresses

TB-1&TB-3

2

3/9/13

1

Machine addresses and sequencing

TB-1&TB-3

3

4/9/13 1

Various addressing modes

TB-1&TB-3

4

5/9/13 1

Instruction formats

TB-1&TB-3

5

6/9/13

2

Basic machine instructions

TB-1&TB-3

6

11/9/13

2 IA-32 Pentium example TB-1&TB-3





2013-14

UNIT - VI Regulation: R11

FACULTY DETAILS:








No. Periods


1

13/9/13 2

Introduction to CPU TB-1&TB-3&RB-1

2

17/9/13 2 register transfers TB-1&RB-1

3

20/9/13

1

Execution of instructions

TB-1&RB-1

4

23/9/13

1

Multiple bus organization

TB-1&RB-1

5

24/9/13

2

Hard wired control

TB-1&RB-1

6

25/9/13

1

Micro programmed control

TB-1&RB-1





2013-14

UNIT - VII Regulation: R11

FACULTY DETAILS:








No. Periods


1

26/9/13

1

Concept of memory

TB-1&RB-1

2

27/9/13

2

RAM ROM memories

TB-1&RB-1

3

2/10/13 1

Memory hierarchy

TB-1&RB-1

4

3/10/13 1 cache memories TB-1&RB-1

5

4/10/13

2

virtual memory

TB-1&RB-1

6

8/10/13

1

Secondary storage

TB-1&RB-1

7

9/10/13 1 memory management requirements TB-1&RB-1





2013-14

UNIT - VIII Regulation: R11

FACULTY DETAILS:








No. Periods


1

10/10/13

2

Introduction to I/O, interrupts hardware

TB-1&RB-1&2

2

17/10/13

2

Enabling and disabling interrupts, device

control TB-1&RB-1&2

3

18/10/13

3

Direct memory access, Buses, interfaces

circuits, standard I/O interfaces. TB-1&RB-1&2




COURSE COMPLETION STATUS

2013-14

Regulation: R11

FACULTY DETAILS:


Subject:: Computer Organization &Digital Logic Design

Subject Code

Department:: IT

Actual Date of Completion & Remarks, if any

Nos. of

Units Remarks Objectives

Achieved

Unit 1

Covered the syllabus as the per the course plan.

As per CP

Unit 2

As per CP


Unit 3

As per CP


Unit 4

As per CP


Unit 5

As per CP


Unit 6


As per CP

Unit 7


As per CP

Unit 8


As per CP

Signature of Dean of School Signature of Faculty Date: Date:

NOTE: AFTER THE COMPLETION OF EACH UNIT MENTION THE NUMBER OF OBJECTIVES ACHIEVED

FACULTY DETAILS:





Date:

This Tutorial corresponds to Unit Nos.1,2, Time:

Q1.Explain about Multiprocessors and Multicomputer with examples? Q2.Explain basic functional units of computer? Q3.explain fixed point representation and floating point representation with an example? Q4.Explain all conversion of binary numbers (example binary to octal number and hexa decimal to binary) with suitable examples? Q5.Explain logic gates and flip-flops? b. Write a short note on multilevel gate implementations c. Reduce the following function using Karnaugh map techniques. F(A,B,C)=∑m(0,1,3,7)+∑d(2,5) Q6.Simplify and implement the following SOP function using NOR gates F(A,B,C,D)=∑m(0,1,4,5,10,11,14,15)

Please write the Questions / Problems / Exercises which you would like to give to the students and also mention the

objectives to which these questions / Problems are related.


TUTORIAL SHEETS - I

2013-14

Regulation: R11

FACULTY DETAILS:





Date:

This Tutorial corresponds to Unit Nos. 3, 4, 5 Time:

Q1.Explain about Multiplexers and decoders with examples

Q2. Explain fixed point and floating point Multiplication algorithm with suitable examples?

Q3.Draw and explain about the instruction cycle state diagram?

Q4.Explain various addressing modes with an examples?

Q5.Disuss about functioning of micro programmed control unit? Q6.Explain Booth’s algorithm with its theoretical basis?




TUTORIAL SHEETS - II

2013-14

Regulation: R11

FACULTY DETAILS:




Date:

This Tutorial corresponds to Unit Nos.6,7,8 Time:

1. What are the different types mapping techniques used in the usage of cache memory?

2. Compare and contrast direct and associative mapping techniques

3. Describe the organization of DMA and write short notes an USB?

4. Discussing previous Question papers?




TUTORIAL SHEETS - II

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Regulation: R11

These verbs can also be used while framing questions for Continuous Assessment Examinations as well as for End – Semester (final) Examinations.

ILLUSTRATIVE VERBS FOR STATING GENERAL OBJECTIVES

Know Understand Analyze Generate

Comprehend Apply Design Evaluate

ILLUSTRATIVE VERBS FOR STATING SPECIFIC OBJECTIVES:

A. Cognitive Domain

1 2 3 4 5 6

Knowledge Comprehension

Application Analysis

Synthesis Evaluation

Understanding

of knowledge & of whole w.r.t. its combination of judgement

comprehension

constituents ideas/constituents

Define Convert Change Breakdown Categorize Appraise

Identify Defend Compute Differentiate Combine Compare

Label Describe (a Demonstrate Discriminate Compile Conclude

List procedure) Deduce Distinguish Compose Contrast

Match Distinguish Manipulate Separate Create Criticize

Reproduce Estimate Modify Subdivide Devise Justify

Select Explain why/how Predict Design Interpret

State Extend Prepare Generate Support

Generalize Relate Organize

Give examples Show Plan

Illustrate Solve Rearrange

Infer Reconstruct

Summarize Reorganize

Revise

B. Affective Domain C. Psychomotor Domain (skill development)

Adhere Resolve Bend Dissect Insert Perform Straighten

Assist Select Calibrate Draw Keep Prepare Strengthen

Attend Serve Compress Extend Elongate Remove Time

Change Share Conduct Feed Limit Replace Transfer

Develop Connect File Manipulate Report Type

Help Convert Grow Move preciselyReset Weigh

Influence Decrease Handle Operate Run

Initiate Demonstrate Increase Paint Set

ILLUSTRATIVE VERBS FOR STATING

INSTRUCTIONAL OBJECTIVES

2013-14

Regulation: R11

LESSON PLAN Unit-1

2013-14

Regulation: R11

Name of the Faculty: D.Sravanthi

Subject Computer Organization &Digital Logic Design

Subject Code 53037

Unit I

INSTRUCTIONAL OBJECTIVES:

On completion of this lesson the student shall be able to (Outcomes)

1. The Students will learn the fundamentals of computer organization 2. student should be understand the generation of computers and functional units 3. student shall be able to understand the binary code conversions 4. student shall be able to understand the what is signed bit number and unsigned

number

Session

No Topics to be covered

Time

Ref

Teaching

Method

1 Introduction about computers, computer types.

3/7/2013 TB-1

Lecture

2 functional units

TB-1&TB-2

3 Basic operational concepts 5/7/13

TB-1

4 Bus structures, software, performance 8/7/20

13 TB-1

5 Multiprocessors, multi computers 9/7/13

TB-1

6 Computer generations, binary numbers 10/7/1

3 TB-1

7 Fixed point representation, floating point representation 11/7/1

3 TB-1

8

Number base conversions, octal and hexadecimal numbers,

complements

12/7/13

TB-1

9 Signed binary numbers, binary codes 16/7/1

3

ASSIGNMENT Unit-I

2013-14

Regulation: R11

Assignment / Questions 1 Explain functional units and Basic operations of computer

2. Explain complements number and signed binary number with an example?

3. Convert binary number to octal number with examples?

4. Explain floating number with an example

Signature of Faculty Note: Mention for each question the relevant objectives and outcomes.

LESSON PLAN Unit-II

2013-14

Regulation: R11


Subject DLD&CO Subject Code 5303

Unit II


On completion of this lesson the student shall be able to

1 Student shall be able draw the logic diagrams 2 Student shall be able to draw the flip flops and where it is useful 3 Student shall be able understand minimization of logic expression

Session


Time

Ref

Teaching

Method

1 Basic logic functions,

17/7/13 TB-1 Lecture

2 Logic gates 18/7/13 TB-1

3 Universal logic gates 23/7/13 TB-1

4 Minimization of logic expressions TB-1

5 Flip flops 26/7/13 TB1-

ASSIGNMENT Unit-II

2013-14

Regulation: R11

Assignment / Questions

1. Explain logic function with example?

2. Draw the NAND and NOR and EX-OR gates

3. Explain JK flip-flops with example?

4. Simplify the k-map and draw the logic diagram?

5. F(A,B,C,D)=∑(2,5,6,9,10,15,8,4)


LESSON PLAN Unit-III

2013-14

Regulation: R11



Unit III


On completion of this lesson the student shall be able to(Outcomes)

1. Student should be understand the use of registers 2. Student should be understood the basic machine organization of fetch and decoder

and execution of a data. 3. Student shall be able to understand the use of multiplexers and programmable logic

gates

Session


Time

Ref

Teaching

Method

1 Registers 1/8/13 TB-

1&TB-3 Lecture

2

Shift registers, 2/8/13 TB-

1&TB-3

3

binary counters ,Decoders 6/8 TB-

1&TB-3

4

multiplexers 7/8 TB-

1&Tb-3

5 Programmable logic devices

8/8/13 TB-

1&TB-3

ASSIGNMENT Unit-III

2013-14

Regulation: R11


1. Design the full adder circuit using decoder and demultiplexers?

2. Implement following Boolean functions using PLA

3. F1(A,B,C)=∑m(0,1,3,5),F2(A,B,C)=∑(0,3,5,7)

4. What is PLA ?How it differs from PROM and PLA?

5. Explain the analysis for combinational circuits?


LESSON PLAN Unit-IV

2013-14

Regulation: R11



Unit IV



1. Student shall be able to understand the addition & division of two binary number 2. Student shall be to understand the arithmetic calculation of binary codes 3. Student shall be able understand the basic machine organization convert and adding

or division of binary number 4. Student shall be able to understand the hardware implementation of binary code

arithmetic’s

Session


Time

Ref

Teaching

Method

1 Algorithms for fixed point addition with an examples 13/8/13

TB-1&TB-3 Lecture

2 Subtraction algorithm with an Examples 14/8/13

TB-1&TB-3

3 Multiplication algorithm with an examples 15/8/13

TB-1&TB-3

4 Division algorithm with an examples 16/8/13

TB-1&TB-3

5 Floating point addition algorithm 19/8/13

TB-1&TB-3

6 Subtraction and multiplication algorithm for floating point 20/8/13

TB-1&TB-3

7 Division algorithm for floating point and with an example 21/8/13

TB-1&TB-3

8 High Performance arithmetic

23/8/13 TB-1&TB-3

9 logic operations

24/8/13 TB-1&TB-3

10 Hardware implementation of arithmetic 30/8/13 TB-1&TB-3

ASSIGNMENT Unit-IV

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Regulation: R11


1. Explain the Booth’s algorithm with example? 2. Write an algorithm to multiply binary number represented in normalized floating

point mode? 3. Explain Hardware implementation of integer addition and subtraction? 4. Write floating point division algorithm with example 5. Explain Hardware implementation of arithmetic operations? 6. Draw the foxed point algorithm for addition with example?


LESSON PLAN Unit-V

2013-14

Regulation: R11



Unit V



1. Student will see how to use concepts of computer organization in real-life settings using various PC performance improvements.

2. Student will see how to use the machine addressing modes and instruction sets 3. Student should understand the basic machine instruction and where it is placed 4. Student understand the IA-32 Pentium and functionalities and how to use

Session


Time

Ref

Teaching

Method

1 Memory locations and addresses

2/9/13 TB-1&TB-3

Lecture

2 Machine addresses and sequencing 3/9/13 TB-1&TB-3

3 Various addressing modes

4/9/13 TB-1&TB-3

4

Instruction formats

5/9/13

TB-1&TB-3

5 Basic machine instructions 6/9/13 TB-1&TB-3

6 IA-32 Pentium example

11/9/13 TB-1&TB-3

ASSIGNMENT Unit-V

2013-14

Regulation: R11


1. What do you mean by Big-Endian and Little-Endian?

2. Explain the process of instruction execution

3. Explain various addressing modes with help of example?

4. Draw and explain about instruction cycle state diagram?


LESSON PLAN Unit-VI

2013-14

Regulation: R11



Unit VI



1. Student shall be able to understand the working of CPU and how the data stored in the CPU

2. Student shall be able to understand the how data will be executed in the programs 3. Student shall be able to what is Hard wired control and micro programmed control 4. Student shall be able to understand the working of CPU and how data are stored in

the registers

Session


Time

Ref

Teaching

Method

1

Introduction to CPU 13/9/13

TB1&TB3& RB-1

Lecture

2 register transfers 17/9/13 TB1&RB-1

3 Execution of instructions 20/9/13

TB-1&RB-1

4 Multiple bus organization 23/9/13

TB-1&RB-1

5 Hard wired control 24/9/13

TB-1&RB-1

6 Micro programmed control 25/9/13

TB-1&RB-1

ASSIGNMENT Unit-VI

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Regulation: R11


1. Discuss about functioning of micro programmed control unit

2. Explain single bus organization of processor unit?

3. Draw and explain typical hard wired control unit?

4. Draw and explain the implementation one-bit register?


LESSON PLAN Unit-VII

2013-14

Regulation: R11



Unit VII



1. Student shall be able to understand the how the data stored in the memory and how to process the data using memory address register and memory data registers

2. Student shall be able to understand the what mean by Cache memory and what is

the use of cache memory 3. Student shall be able understand the what is virtual memory and secondary memory 4. Student should be able to manage the memory requirements

Session


Time

Ref

Teaching

Method

1 Concept of memory 26/9/13

TB-1&RB-1 Lecture

2 RAM ROM memories 27/9/13

TB-1&RB-1

3 Memory hierarchy

2/10/13 TB-1&RB-1

4 cache memories 3/10/13 TB-1&RB-1

5 virtual memory 4/10/13

TB-1&RB-1

6 Secondary storage 8/10/13

TB-1&RB-1

7 memory management requirements 9/10/13 TB-1&RB-1

ASSIGNMENT Unit-VII

2013-14

Regulation: R11


1. What are the different types of mapping techniques used in the cache memory?

2. Compare and contrasts direct and associative mapping?

3. Explain virtual and secondary memory?

4. Draw and explain the organization for ROM, PROM?

5. Write a short note on magnetic tapes and floppy disks and magnetic disks?

6. Explain replacement algorithm for cache memory?


LESSON PLAN Unit-VIII

2013-14

Regulation: R11


Subject Computer Organization &Digital Logic Design

Subject Code 53037

Unit VIII



1. Student shall be able to understand the input output organization and how to access I/O devices.

2. Student shall be able understand the what is interface and where it used 3. Student should be understand the what is direct memory and what are the interrupts

service and operations 4. Student shall be able to understand the what is input port and where it is used

Session


Time

Ref

Teaching

Method

1 Introduction to I/O, interrupts hardware 10/10/13 TB1&

RB-1&2 Lecture

2 Enabling and disabling interrupts, device control 17/10/13 TB-1&

RB-1&2

3

Direct memory access, Buses, interfaces circuits, standard

I/O interfaces.

18/10/13 TB-1& RB-1&2

ASSIGNMENT Unit-VIII

2013-14

Regulation: R11


1. What are the different modes of data transfer? Explain each mode in detail?

2. What is direct memory access and explain the working of DMA?

3. What are relative advantage and disadvantage of I/O communication techniques

explain?

4. Write a short note on USB hub?


Documents

DLD&CO COURSE PLAN D.SRAVANTHI - J. B. Institute of