Double-GateT.pdf

8/14/2019 Double-GateT.pdf

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Double-GateDouble-Gate MOSFETsMOSFETs

Kavitha Ramasamy, CristinaKavitha Ramasamy, Cristina CrespoCrespo

Portland State UniversityPortland State University

ECE 515ECE 515Winter 2003Winter 2003


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OverviewOverview

IntroductionIntroduction

General DGT Structure and OperationGeneral DGT Structure and Operation

DGT Design ObjectivesDGT Design Objectives

Short-Channel EffectsShort-Channel Effects

Advantages of DGT (Reduction ofAdvantages of DGT (Reduction of IIoffoff))

DGT Design Challenges (VDGT Design Challenges (VTTControl and DeviceControl and Device

Fabrication)Fabrication)Different DGT StructuresDifferent DGT Structures

Challenges AheadChallenges Ahead

ConclusionConclusion


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Silicon CMOS has emerged as the predominantSilicon CMOS has emerged as the predominanttechnology in the semiconductor industry.technology in the semiconductor industry.

The concept of device scaling has consistentlyThe concept of device scaling has consistently

resulted in better device density andresulted in better device density andperformance.performance.

In conventionalIn conventional MOSFETsMOSFETs, control of Ioff for, control of Ioff forscaled devices requires very thin gate dielectricsscaled devices requires very thin gate dielectricsand high doping concentrations.and high doping concentrations.

The industry roadmap for CMOS technologyThe industry roadmap for CMOS technologysuggests that we may be reaching somesuggests that we may be reaching somephysical limitations as well as practicalphysical limitations as well as practicaltechnological barriers to continuous scaling.technological barriers to continuous scaling.


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We are expected to reach the limit value of 35nm forWe are expected to reach the limit value of 35nm forthe gate length by 2010the gate length by 2010

[1]


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As the downscale of CMOS technologyAs the downscale of CMOS technologyapproaches physical limitations, the need arisesapproaches physical limitations, the need arisesfor alternative device structures.for alternative device structures.

Many novel structures have been proposed forMany novel structures have been proposed forthe nanoscale regime.the nanoscale regime.

One such structure is the Double-GateOne such structure is the Double-GateTransistor, proposed in the 1980s.Transistor, proposed in the 1980s.

Other possible solutions include SOI devices,Other possible solutions include SOI devices,strained-siliconstrained-silicon FETsFETs, carbon, carbon nanotube FETsnanotube FETs,,etc.etc.


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GeneralGeneral DGTDGTStructureStructure

DGT is comprised of a conducting channelDGT is comprised of a conducting channel

(usually undoped), surrounded by gate(usually undoped), surrounded by gateelectrodes on either side.electrodes on either side.

This ensures that no part of the channel is farThis ensures that no part of the channel is faraway from a gate electrode.away from a gate electrode.

[2]


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General DGT OperationGeneral DGT OperationThe voltage applied on the gate terminals controlsThe voltage applied on the gate terminals controlsthe electric field, determining the amount ofthe electric field, determining the amount ofcurrent flow through the channel.current flow through the channel.

The most common mode of operation is to switchThe most common mode of operation is to switch

both gates simultaneously.both gates simultaneously.Another mode is to switch only one gate andAnother mode is to switch only one gate andapply a bias to the second gate (this is calledapply a bias to the second gate (this is calledground planeground plane(GP) or(GP) or back-gateback-gate(BG))(BG))

[3]


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DGT Design ObjectivesDGT Design Objectives

Reduction of short channel effects (SCE)Reduction of short channel effects (SCE)

Increased IIncreased Ioffoffdue to DIBLdue to DIBL

Decreased VDecreased VTTdue to reduced channeldue to reduced channeldepletion chargedepletion charge

Maintaining good electrical characteristicsMaintaining good electrical characteristics

High IHigh Ionon/I/Ioffoffratioratio

Sharp I-V slopeSharp I-V slope

Keeping fabrication process simpleKeeping fabrication process simple

Addition of steps to existing processesAddition of steps to existing processes


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Short Channel EffectsShort Channel Effects

For small channel lengths,For small channel lengths,potential barrier at thepotential barrier at thedrain is lowered asdrain is lowered as VdsVdsincreases, allowing moreincreases, allowing more

electrons to flow into theelectrons to flow into thedrain.drain.

This effectively lowersThis effectively lowers

VVTT, causing a larger I, causing a larger Ioffoff..

[4]

[4]


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Advantages ofAdvantages of DGTsDGTs

Main advantage: Reduction of IMain advantage: Reduction of Ioffoff..

Undoped channel eliminates intrinsicUndoped channel eliminates intrinsic

parameter fluctuations and minimizesparameter fluctuations and minimizesimpurity scattering.impurity scattering.

Double gate allows for higher current driveDouble gate allows for higher current drive

capabilitycapability

Better control of short channel effects.Better control of short channel effects.


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Reduction of IReduction of IoffoffIIoffoffis defined as the drain current atis defined as the drain current at VgsVgs = 0 V= 0 V

andand VdsVds == VddVdd. Ideally, I. Ideally, Ioffoff= 0= 0

Sources of ISources of Ioffoff::

Thermionic emission (main)Thermionic emission (main) Quantum Mechanical TunnelingQuantum Mechanical Tunneling

Band-to-Band Tunneling (abruptBand-to-Band Tunneling (abrupt

doping profile)doping profile)

IIoffoffincreases as we move theincreases as we move thebody further away from thebody further away from the

control of the gate.control of the gate.

[5]


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Reduction of IReduction of IoffoffBy placing a second gate on the opposite side ofBy placing a second gate on the opposite side of

the device, the gate capacitance of the channelthe device, the gate capacitance of the channel

is doubled and the channel potential is betteris doubled and the channel potential is better

controlled by the gate electrode, thus limiting Icontrolled by the gate electrode, thus limiting Ioffoff

[2]


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Reduction of IReduction of IoffoffReducing the bodyReducing the bodythickness furtherthickness furtherdecreases Idecreases Ioffoff..

Reducing bodyReducing bodythickness has thethickness has thetradeoff of increasingtradeoff of increasingseries resistanceseries resistance

(R =(R = rrL/AL/A).).

RRseriesseriescan becan beminimized by using aminimized by using araised source/drainraised source/draintype of structure.type of structure.

[5]


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DGT Design ChallengesDGT Design Challenges

Main challenge: Control of VMain challenge: Control of VTT..

VVTTis defined as the value ofis defined as the value of VgsVgs needed toneeded tocause surface inversion, creating a conductingcause surface inversion, creating a conducting

channel.channel.Due to scaling ofDue to scaling of VddVdd, we want to have low, we want to have low(~0.2 V) and symmetrical ((~0.2 V) and symmetrical (VVTnTn= -= -VVTpTp) threshold) thresholdvoltages for both transistor types.voltages for both transistor types.

ForFor DGTsDGTs, V, VTTis primarily controlled byis primarily controlled by ffgategate ..

With a singleWith a single midgapmidgap material for both NMOSmaterial for both NMOSand PMOS, symmetricaland PMOS, symmetrical VVTTss can be achieved,can be achieved,but the value is too large (~0.8 V).but the value is too large (~0.8 V).


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VVTTControlControl

A possible solution would be the use of twoA possible solution would be the use of twodifferent values ofdifferent values of__gategate near the middle ofnear the middle of EgEgSiSi..(~0.45(~0.45 eVeV for NMOS and ~0.49for NMOS and ~0.49 eVeV for PMOSfor PMOSforfor VVTnTn == --VVTpTp= 0.2 V).= 0.2 V).

Difficulty: Need two materials that areDifficulty: Need two materials that arecompatible and can coexist on the same wafer.compatible and can coexist on the same wafer.

A dual-metal gate process has been proposed,A dual-metal gate process has been proposed,but turned out too complex.but turned out too complex.

Other solutions proposed: tunableOther solutions proposed: tunable ffgategate bybyaltering the chemistry of the material, metalaltering the chemistry of the material, metalinterdiffusion, and use of smallinterdiffusion, and use of small bandgapbandgapsemiconductor.semiconductor.


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VVTTControlControl

Another proposed solution to this problem isAnother proposed solution to this problem is

the use of asymmetrical devices, where a n+the use of asymmetrical devices, where a n+and a p+ gate are used.and a p+ gate are used.

Main problem with this structure is fabrication,Main problem with this structure is fabrication,since it requires alignment of the two gates.since it requires alignment of the two gates.

[6]


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VVTTControlControl

Previously,Previously,

reduction of bodyreduction of body

thickness wasthickness was

proposed as aproposed as ameans to control Imeans to control Ioffoff..

Another tradeoff isAnother tradeoff is

that reducing bodythat reducing body

thickness increasesthickness increasesthe value of Vthe value of VTT..

[5]


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Fabrication IssuesFabrication Issues

Fabrication of the DG-FET is difficult.Fabrication of the DG-FET is difficult.

Alignment of both gates is hard to achieve,Alignment of both gates is hard to achieve,but it is required for good devicebut it is required for good device

performance.performance.Misaligned gates result in extraMisaligned gates result in extracapacitance and loss of current drive.capacitance and loss of current drive.

Several different structures have beenSeveral different structures have beenproposed to deal with fabrication issues,proposed to deal with fabrication issues,including planar and quasi-planarincluding planar and quasi-planarstructures.structures.


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DGT Structures: PlanarDGT Structures: Planar

Advantages:Advantages: Better uniformity of Silicon channel thicknessBetter uniformity of Silicon channel thickness

Can take advantage of existing fabrication processesCan take advantage of existing fabrication processes

Disadvantages:Disadvantages: Fabrication of back gate and gate dielectric underneath theFabrication of back gate and gate dielectric underneath the

Silicon channel is difficultSilicon channel is difficult

Accessing bottom gate for device wiring is not easy (may impactAccessing bottom gate for device wiring is not easy (may impactdevice density)device density)

[7]


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DGT Structures: Non-planarDGT Structures: Non-planar

Advantages:Advantages:

Easier formation and access of both gates (wraparound gate)Easier formation and access of both gates (wraparound gate)

Increases device densityIncreases device density

Disadvantages:Disadvantages:

Channel thickness defined by lithography (poorer uniformity)Channel thickness defined by lithography (poorer uniformity)

Front and back gates cannot be independently biasedFront and back gates cannot be independently biased

Major departure from conventional fabrication processesMajor departure from conventional fabrication processes

[7]


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Challenges aheadChallenges ahead

Even though simulations have shown improvedEven though simulations have shown improvedperformance ofperformance of DGTsDGTs versus conventionalversus conventionalMOSFETsMOSFETs, many challenges remain., many challenges remain.

Standard fabrication process still to beStandard fabrication process still to be

developed.developed.Ability to set multiple threshold voltages on aAbility to set multiple threshold voltages on asingle chip not yet addressed successfully.single chip not yet addressed successfully.

Thin Silicon channel introducing seriesThin Silicon channel introducing seriesresistance is of particular concern.resistance is of particular concern.

Maintaining a thin, uniform Silicon channelMaintaining a thin, uniform Silicon channelthickness remains a major manufacturingthickness remains a major manufacturingobstacle.obstacle.


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ConclusionConclusion

Scaling trend in CMOS approaching physicalScaling trend in CMOS approaching physicallimits prompts the need for alternative devicelimits prompts the need for alternative devicestructures, such as DGT.structures, such as DGT.

DGT is more robust to SCE, such asDGT is more robust to SCE, such as

IIoffoff.

.

Major design challenge consists of achievingMajor design challenge consists of achievinggood Vgood VTTcontrol, while keeping lowcontrol, while keeping low RRseriesseries..

Several structures have been proposed: planar,Several structures have been proposed: planar,vertical, andvertical, and FinFETFinFET

FinFETFinFET structure is so far the most promising.structure is so far the most promising.Still major challenges remain ahead, speciallyStill major challenges remain ahead, speciallyissues related to fabrication.issues related to fabrication.


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ReferencesReferences

[1][1] http://www.intel.com/research/silicon/Marcyk_tri_gate_0902.pdfhttp://www.intel.com/research/silicon/Marcyk_tri_gate_0902.pdf[2] A. R. Brown et al.,[2] A. R. Brown et al., A 3-D Atomistic Study of Archetypal Double GateA 3-D Atomistic Study of Archetypal Double GateMOSFET Structures,MOSFET Structures,J. Comp. Elec., vol. 1, pp. 165-169, 2002J. Comp. Elec., vol. 1, pp. 165-169, 2002

[3] H.-S. P. Wong,[3] H.-S. P. Wong, Beyond the Conventional Transistor,Beyond the Conventional Transistor,IBM J. Res. &IBM J. Res. &Dev., vol. 46 No. 2/3, March/May 2002Dev., vol. 46 No. 2/3, March/May 2002

[4] http://www.ifm.liu.se/courses/tffy34/Tutorial3.pdf[4] http://www.ifm.liu.se/courses/tffy34/Tutorial3.pdf[5] L. Chang[5] L. Chang et alet al.,., Gate Length Scaling and Threshold Voltage Control ofGate Length Scaling and Threshold Voltage Control ofDouble-GateDouble-Gate MOSFETsMOSFETs,,IEDM pp. 719-722, 2000IEDM pp. 719-722, 2000[6] J.G.[6] J.G. FossumFossum et alet al.,., Extraordinarily high drive current in asymmetricalExtraordinarily high drive current in asymmetricaldouble-gatedouble-gate MOSFETsMOSFETs,,SuperlatticesSuperlattices and Microstructures., vol. 28 No. 5/6,and Microstructures., vol. 28 No. 5/6,20002000

[7] L.[7] L. GeppertGeppert,, The Amazing Vanishing Transistor Act,The Amazing Vanishing Transistor Act,IEEE Spectrum,IEEE Spectrum,October 2002October 2002[8] K.[8] K. KeunwooKeunwooet alet al.,., Double-Gate CMOS: Symmetrical- versusDouble-Gate CMOS: Symmetrical- versus

Asymmetrical-Gate Devices,Asymmetrical-Gate Devices,IEEE Trans. Elec. Dev., vol. 48 No. 2,IEEE Trans. Elec. Dev., vol. 48 No. 2,February 2001February 2001

[9] F.[9] F.AssadAssadet al.,et al., Performance limits of SiliconPerformance limits of Silicon MOSFETsMOSFETs,,IEDM,1999IEDM,1999

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Double-GateT.pdf