Dual Gate Bucket

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 9, SEPTEMBER 1980 1809

Dual-Gate Bucket-Brigade Devices

RADU M. BARSAN, MEMBER, IEEE

Abstract-The low charge-transfer efficiency of the basic bucket-brigade circuit and the speed limitation of th e tetrod e approach haveso far prevented bucket-brigadedevices (BBD’s), in spite of their greater

fabrication simplicity, from competing with charge-coupled devices,excepting for audio applications.

A novel charge-transfer device is presented and experimentally eval-uated. The dual-gate BBD” is wo-step-transferdevicea CCD

transfer followed by a BBD transfer), howing operational performances

comparable to surface-channel CCD’s and, at the same time, e njoyingthe fabrication simplicity proper to bucket-brigade circuits. The con-

cept is implemented using conventional p-channel aluminum-gate tech-

nology combined with an additionalshadowed-gap float-off process.The haracteristic eatures and theperformanc e apabilities of thedevice are discussed.

DI . NTRODUCTION

URING th e last decad e, charge-tran sfer devices (CTD’s)

[ l ] have developed from the laboratory concept into a

mature class of semiconductor devices with significant impact

in th e areas of sampled-d ata signal processing, maging, an d

memory.The CTD family ncludes harge-cou pled devices

(CCD’s) [ 2 ] an dbucket-brigad e devices BBD’s) [3 ]. Gener-

ally, CCD’s have better operational performan ces than BBD’s.

Atmoderate requencies,charge-transfer nefficiency nsur-

face-channel CCD’ss on heorderof ndon heorder

of lo-’ in buried-chan nel devices, whereas BBD’s are limited

to values greater than Darkurrentnd oisere also

smaller in CCD s and the packing density is greater than tha t

of BBD’s. In exchang e, CCD’s are more difficult t o fabricate.In order to achieve their full capabilities, CC Ds requ ire lead-

ingedge technologies, nvalidating heearlypredictions hat

their processing would be simp ler than onv ention al MOS

circuit technolog y. In contrast, BBD’s can be fabricated using

the simplest of the M OS processes, such as a p-channe l alumi-

num gate.

This paper describes a novel bucket-brigade tructure, termed

dual-gate BBD, which exhibits performan ce capabilities com-

parable to surface-chann el CCD’s. The device is fabricated

using ahigh-thresholdp-channel Al-gate technolog y with an

addit ional “float-o ff” process yielding self-aligned gates with

submicrometereparations.he device characteristicsre

discussed in Secti on I1 an d som e processing details are presentedin Section 111. Experimental results on device performance are

reported and interpreted in Section IV.

11. CHARACTERISTICSF THE DUAL-GATE BD

In he basicBBD shift register, shown n Fig. l(a) , charge

transfer takes place through the channel of a simple MOSFET

whosegate-draincapacitancehas been largely increased to

Manuscript received July 15 ,1 97 9; revised April 15,1980.The author is with the R and D Center for Semiconductors, Bucharest

72996, Rumania.

B I A S L I N E

I 1

1 1 !1

0 2j

( 4

Fig. 1. Schematic cross sections through a p-chan nel (a) simple BBD,(b) tetrode configuration, an d (c) novel dual-gate bucket brigade.

form on e of the storage elements in the delay line. The most

significant effects contributing to charge-transfer nefficiency

at owand ntermediate requenciesare he initedynamic

drain conductance, threshold-voltage modulation, storage-

capacitancemodulation 4] -[8] , an dsubthreshold leakage

[ 7 ] , [ 9 ] . A thigherclock ates, the ransfer inefficiency n-creases d ue t o t he finite time allotted for charge to flow from

one capacitor to the next [4] -[8] . This inherent limitation is

determined by he gain characteristicsof the ransistors, as

well as by the mag nitud e of the storage capacitances, and the

corresponding intrinsic inefficiency term [7] is given by

where 0 is the saturat ed MOSFET square-law factor, Vc the

clock voltage level, V, the hreshold voltage, &, the initial

source potential, C,, the storage capacitance, and f, he clock

frequency.Thedominating mechanisms at low ndnter-

mediaterequenciesre rimarily etermined by channel(barrier) ength mo dulatio n, a ypical exam ple being the dy -

namic drain conductance contrib ution to incomplete transfer,

given by

where g is the M OSFET saturation output conductance and

gm the transconductance.

A general me th od to educe the mo dulation effects inCTD’s

is to isolate th e source from the charge sink by means of an

0018-9383/80/009-1809$00.75 0 1980 IEEE



ir1tc:rmediate barri er egio n. Th e charge transfe r bec:omc:s in

t h i s way a wo-stepprocess nwhich he charge rom or e

sl:or,age capacitor is firstransferred to somenterrnec1ial:e

c,apacitor Cz and then to the next storage capacitor, during ;a

single transfercycle.Suchaprocedure educes hemodula-

tion erms by approximately he atio of the ntermediate

capacitance to he storage apacitance [7 ]. Application of

this principle to he simpleBBD has esulted n thi: te tr od e

strulcture [101 , [111 , hown in Fig. l(b). Here, the capacitance

CZ(t o th e left of t he activ e channel) cons ists of the dep1l:ti’on

capacitancebetween the ntermediate p island and hesub-strat.e C p , he gate capacitance of the first MOSFET Cgl , .nd

the ‘overlapcapacitance associated with the intermediate island

and the two adjacent gates, summed up into an overlap capaci-

tanceerm Cov. Consequently,hemodulation (feedback)

cont.ributions to incom plete transfer are reduced from those of

the ;simple BBD with the same storage capacitance, by a factor

The main drawback of the tetrode configuration is its low

speed of operatio n, as comp ared with th e basic circuit. The

effective intrinsic transfer rate term of a two -step transfer cell

is given appro xima tely [7] by

of ( ( 7 p + Cg1 -t Cov)/Cst *

where the ubscripts1and 2 refer to he firstand econd

transfer step, respectively. el i is given by (11) in which V, is

replaced by V B , he voltage applied to he bias line. e , j is

given b y a similar expression, in which C is replaced by Cz

an d Kn by the initial island p otentia l (whiclh is a func tion of

Kn, ,, an d &). Inorder to improve th e low-flrequen’cy

performance, C has to bemade large compared to CI=

C pt Cgl t C whichdrasticallyaffects el i. Inaddition,

noneof he wo channels of the etrode cell canbemade

shorter than the channel ofa simple BBD ceU.. Thus the better

low-frequency behavior of the tetrode con figuratio n is accom-

panied by a poor high-frequency performance. This limits the

usefulness of the tetrode conce pt to audio a.pplications (typi-

cally below 50 kHz).

The novel dual-gate BBD structure is shown schematically in

Fig. l(c). This onfiguration achieves the screening of the

source with respect to the drain of each MOSFET by a self-

aligned bias-gate lectrode btainedwith single level of

aluminum and a submicrom eter gapprocess.’ Thus each cell

contains a dual-gate MOSFET [121 , which has th e bias gate

located near the source and the active gate near the drain. In

contrast to th e tetro de stru cture discussed above, in which the

charge transfer s by twosuccessive “bucket-brigade’’ processes,the charge transfer n he dual-gateapproachconsistsofa

“bucket-briga de” rocessollowed by acharge-coupled”

process, provided the dc voltage applied to the bias gate is low

enough with respect to th e clock voltage to ensure a complete

charge-transfer mod e of operation of the “CCD” half cell.

The ntermediatecapa citanc e of the dual-gate BBD cell is

‘The same concept could also be implemented using overlapping-gatetechnolog ies but wh ich, beside increasing the capacitive loading of theclock lines, are mo re complex and, consequently, less suitable fo r cost-effective CTD’s.

n m d e u p clrlly o f th e effective gate capacitance associated with

t.heias-gs-te electrode c bg , , Consequently, all modulation

ef fects : do~nh~at in~ ;he low- and intermediate-frequency trans-

fe:: rle!ffi.c~.e:nc:y areeduc ed .by a facto r of c b g / c , , compared

t o th.e simple BBID, and by a fac tor of c b g / ( c p t C t Co,)

compa.red to the tetrode configuration. The first ratio may lay

in the range of 1/50-~1/100.Considering a tetrode cell and a

dulal-,gaie st:ll of :qlud chann el width s, the second factor can

be expaessed alpprorrimately as

bg

Cd e pr == (4)

(I, ;I-2 lo, t 2:x )- g l + 2 lovcox

wherle l ; b g is the affective length of the bias gate of the dual-

gate c1d1,Lgl the channel length of the first MOSFET in th e

tetroldt:cell., 1, theminimum nterelectrodespacing, Zo v the

minimu m overlap betw een gate and diffusion: xj the junction

depth , ‘Cde:p the depletion capacitance per unit area, and Cox

th e oxide ‘capacitance per unit area. Taking L b g = 4 pm, Lgl =10 pm , 1, =- 8 pm.,o, = 6 pm , xj = 2 pm, dep = COx/3 , the

factor r given by (4 ) is about 0.13 . These examples show that

the d.u.al-gate BBDI has a low -frequ ency transfe r ineff icienc yof

7-8 times smaller tha n a tetrod e BBD and up to t wo orders ofmagnitude smaller than the basic circuit.

Since the ntermediatecapacitanceof hedual-g ate cell is

reduced by a factor r from that of the tetrode ell, the storage

capacitamcle can be made r times smaller for the two structures

to ex.hibit similar low-frequ ency performances. This results in

a signifjicant high-frequenc y (intrinsic ransfer-efficie ncy) m -

provennent. Moreover, the high-frequency imit of he dua l-

gate device s further increased through the reduct ion of e Z i ,

whi ch,, n his calse, corresponcls to a CCD transferprocess.

Inadditio n, he activechannel. canbemade muc h smaller

while still avoiding short-ch annel effects [12] . In conclusion

of the preceding discussion, th e dual-gate BBD offers signifi-

cantly better transfer efficiency over a wide frequency range.

Furthe rmore , he possibility to reduce the cell dimensions,

combinedwithhe liminationof nterelectrode spacings,

result in improved packing density.

Another advantage of the dual-gatestructure over existing

BBD’s co ncerns th e dy namic range. First, the parasitic capaci-

tance between the pulsed gate and the source is reduced due t o

the shielding effec t of the self-aligned bias gate, so tha t larger

signal chargepackets can be ransferred 13] . Second, the

absence ofan interm ediate island reducesdarkcurrentand

noise. In ad dition, the in put and output stages can be designed

to reduce the effects of parasitic capacitances. The dual-gate

BBD technology is also co mpatible with improved peripheralamplifiers using dual-gate MOSFET’s [141 , whichcan be

attrac tive or signal-processing circuits ncorp oratin g nalog

delay functions.

The dlual-gate bucket-brigadeconcepthasbeenreduced to

practice using p-channel single-levelaluminum-gate technology.

The self-aligned metalpattern s were obtaine dwith a ub-

21f the tetr od e BBD is fabricated with self-aligned islands, Z = 0.This higher degree of process complex ity is no t required b y the dual-gate approach, so that comparison is made for the simplest of MOSprocesses.



BARSAN: BUCKET-BRIGADE DEVICES 1 8 1 1

Fig. 2. (a )Microphotograph f experim ental ud-gate BBD chip.Lower half of chip con tains an 80-stage shift register. Upper portio ncontains est transistors and capacitors. (b) Enlarged view of hetransfer struc ture. The horizontal narrow stripes form the bias lines(gates). They are separated from adjacent clock lines by submicrom-eter (0.5-firn) gaps.

microm eter-gap process similar to th e “shadow-etch” approach

described by Browne and Perkins [151, [16] ,yielding typically

0.5-pm gaps. A photograph of the complete chip is shown inFig. 2(a) and an enlarged view of some of the 80 cells of th e

BBD circuit is sho wn n Fig.2(b). Thepathof he signal

samples along th e delay line follows a serpentine, alternating

between the clock buses from cell to cell and turning around

every 10 stages. Beside theshift register, thechipcontains

several dual-g ate, as well as norm al, MOSFET’s and som e MOS

capacitors used for characterization and evaluation purposes.

A schematic diagram of th e dual-gate BBD shift register is

shown n Fig. 3 . The circuitconsists of an nput sampling

stage (sampling transi stor ST and capacitor C,), 80 identical

transferstages,aprechargeror eset ransistor ( R T ) , and a

..INPUT

+OUTPUT

Fig. 3. Dual-gate BBD circuit.

source follower (output transistor O T ) . Note that , in contrast

to he transfer ransistors, he nput dual-gate MOSFET has

the gate near the drain connected to the dc bias line (whose

voltage is VB) , he gate near the source being pulsedby one of

the clock phases (G1). The reason for this particular design is

as follows. When the npu t ransisto r is on , he voltage at

node A equals th e inp ut level qn. Upon switching ST off

(raising $1 an ddropping &), the voltage at no de A instan-

taneously changes by an amoun t

where VGis the amplitude of theclock pulses. If Cgus greater

than Cgs,he input signal can no longer vary from zero, but

only rom he level given by ( 5 ) . Consequ ently, he ideal

maxim um nput swing VB- V, is reducedby hisamount.

Du e to the shielding effect of th e bias gate , the parasitic capac-

itance Cgss mu ch lower than the capacitance between a diffu-

sion and the gate overlapping it. According to the preceding

discussion, if the gate near the drain of ST were connected to

G 1 , th edyn amic range would be educed.The lternative

shown in Fig. 3 is self-compensating with respect to parasitic

capacitancemism atch, since bo th gates adjacent to C, are

formed by the same bias line.Th edynam ic range salso limited by th e parasiticcapaci-

tances at the output tage C,, an d cd, (junction capacitances).

When RT is switchedof fand the ast ransfer ransistor is

switched on, the voltage at node B should ideally change from

the reference level VB - V, to V, -t V, - V,. However, due

to parasitics, the voltage changes by only a raction of VG,

given by

which is the max imu m allowable inpu t swing. The use of a

dual-gate precharge transistor reduces Cgs nd henc e, increases

the dynam ic range. In con clusio n, assuming the effect of para-sitic capacitances at the input stage to be negligible, the maxi-

m um inp ut signal for a dual-gate BBD delay ine is given by

V, - V, or ( 6 ) ,which ever is smaller.

111. PROCESSING ONSIDERA TIONS

The dual-gate BBD structures have been abricated using

standardp-channel Al-gate technolog ywith HCl gateoxide,

followed by a liftoff metal patten definition. Fig. 4 hows a

micro pho tograp h and a schema tic cross section of a dual-gate

cell.

After opening the contact windows, a first aluminu m film is



BIAS GATE

Fig. 4 . SEM photog raph and cross section of a dual-gate BBD cell. Lgis the effective length of the active channel and Lbg is the effectivelength of the channel under the ias gate.

evaporated and patterned to define he peripheral metalliza-

tions and the clock buses. By an additional photolithographic

step, the complement of the bias-gate pattern is printed. Using

thismask, thefirstmeta l is slightlyoveretched inorder to

produceshadowed edges [16] , Without removing the resist,

a second alumin um film s evaporatedwhich forms he bias

gates self-aligned with respect to th e active gates. Liftoff ofthe meta l from over the resist is subsequently made in acetone

ornitricacid,dependingon ts hickness. Since thesecond

layer metal pattern is surrounded b y shadowed spacings and

the bias line being accessed by an und erpas s, the only places

where the metal has to break over the resist step are narrow

termination s at the periphery of the BBD structure. The pro-

cessing s comp letedby hedeposition of an overlay oxid e,

or simply by a heat treatm ent (10 min in hydrogen and 10 min

in n ytrogen, b oth at 50°C).

A typical nterelectrode area is shown in Fig. 5 . Note he

steepness of the wet-etche d metal 1 wall, as compared to the

large slopeof themetal 2 pattern,produced by shadowed

evaporation naplanetary y stem.Th eupper edge of th eslope corresponds to the resist (shadow) edge and the distance

to th e first layer m etal wall shows the magn itude of overetch-

ing (the overhan g of the resist). Fig. 6(a) shows a schematic

crosssection hrough hestructureduring hedeposition of

the second aluminum ay er. On a geometrical basis, the size

of the gap g is determ ined by the thickness of the first metal

layer h, the degree of shadowing (overetching) e, and the most

obliqueevapo ration angle in theplanetarysystem amin. In

practic e, he resulted gap s smaller due to the migration of

Fig. 5. Scanning electron m icrograph (10 000 X ) of the region separat-ing the bias and clock metal buses (after final heat treatment). Metal1 is 0.8 pm thick and metal 2 is 0.7 pm thick. The gap size is abo ut6000 A and th e "shadow" (th e resist overhang) appears to have beenabout 1.5 pm. Lower right corner shows an area where aluminum hasbeen removed to prod uce a cross section throug h the metallization.

/'

2 3 L

O V E R E T C H I N G l y m )

(b)

Fig. 6 . (a) Cross section hrough the structure during the evaporationof the second m etal layer. (b) T he gap size as a function of the over-etching of the first metal pattern. Points represent measured valuesand solid lines are plotted according to (7).

aluminum atom s during evaporation (typically about 3000 A

[161) and during the final heat treatment or oxide dep osition(this was experimentally observed to be about 2000 A fo r

aluminum). Consequently, the gap size is given by

g = e - h cotan a m i n - m (7)

where m represents the gap reduction due to aluminum migra-

tion. For amin 60" an d m = 0.5 pm , good agreement exists

between (7 ) and the measured gaps, as shown in Fig. 6(b) for

tw o d ifferent thicknesses of th e first metal layer. As a result

of the investigation of gap formation, it was confirmed that



BARSAN: DUAL-GATE BUCKET-BRIGADE DEVICES 1813

5000 A is a ypical ower imit for he size of reproducible

gaps obtained using aluminum [16] . Since elatively table

devices have been fabricate d with gaps as large as 1.5 pm, the

0.5-pm margin is not a serious limitation from the standpoint

of device performan ces, tability, nd eproducibility.The

transfer nefficiencymeasured on 0.5-pm-gap hift egisters

showedweakdependence on background harge, which

means tha t very good con trol (absence of spurious barriers)

ofuc hnterele ctrode spacings is possible.However, the0.5-pm limit could become a problem when very small chan-

nels (<3 pm) aredesired,because uch sho rt gates ail to

con trol gap regions greater than a few tenths of a micrometer.

A variety of metal thicknesses for bo th aluminum films have

been tes ted. It was foun d that a difference of maximum 1000

A between the two is sufficient for easy liftoff of unwanted

second-layer metal from over the resist. From threshold volt-

age,etchingcontrolability,an dbondingconsiderations, he

thicknessof thefirstaluminum layer or the devices to be

characterized was chosen of 0.8 pm.The second ilm was

0.7 pm thickand he resulting gaps were ypically 0.5 pm .

Th eoxide hickness was in he rangeof 1200A-1300 A

(slightly hinnerunder he bias gatesdue to anadditionalcleaning sequence prior to the second aluminum deposition).

The average surface mpurityconcentration of the substrate

((1 11) orientation) was 2 -4 X 1015cm-’. The boron diffu-

sion yielded junction depths of about 1.6 pm.

The average effective surface mobility of holes was fou nd to

be 140 cm2/V - s. The threshold voltage was typically - 4 V

for MOSFET’s form ed by the first aluminum , and about - 4.5

V for those whose gates were formed by the second deposition.

IV. EXPERIMENTALESULTS A N D DISCUSSION

OF DEVICE PERFORMANCE

The principal parameters (after processing) of the 80-stage

dual-gate BBD’s which were characterized are

active channel length,L , = 8.5 pm;

bias-gate length,Lbg = 6 pm;

channel width,W = 32 pm;

storage capacitance,Cst= 1.4 pF.

The devices were operated with zero substrate bias and clock

voltageamplitudesof 20 V , at requencies varying between

1 kHz and 1 MHz. The max imum in put swing for 20-V square

clocks and a dc gate bias of -2 0 V was about 11V. Typical

device responses are shown in Fig. 7.The registers were characterized with respect to transfer effi-

ciency by the step-response meth od, whereby the incompletetransfer parameter E is determined from

L T = ( N - l ) E (8)

where N is the numb er of delay elements and L T the total

normalized loss, defined as the sum of all trailing p ulses divide d

by the steady -state outpu t level. Plots of experimentally de-

termined transfer inefficiency,as a function of clock frequency

(&), are show n in Fig. 8 for two different voltages applied tothe bias line. Also shown is the measured transfer inefficiency

ofa128-stagesimple BBD delay ine,which was processed

(b)

Fig. 7 . Ou tpu ts of t he BO-stage dual-gate BBD. Verticalscaleis 1V/div.(a) Step function response a t 26 0 kHz. (b) Impulse response at 100kHz. The inputword is a sequence of the form 10001000 . . .

together with the dual-gate devices. The observed dependence

of E on the bias gate voltage Vj is illustrated in Fig. 9.Let us first discuss the behaviorof hedual-gate BBD for

large bias gate voltages. It is clear in Fig. 8 that for this case

(VB = - 16 V) the dominant mechanisms responsible for trans-

fer inefficiency below abo ut 1 MHz are subthresho ld conduc-

tion (diffusion over the barrier) and the dynamic drain con-

ductance effect, since E is weakly dependent on clock frequency

and shows th e same dependence as the simple BBD (the two

curvesareparallel)which is surelyaffectedbymodulation

effects only (Lg = 5 pm), within this frequency range. With

regard to he relativemagnitude of he wo ransfer-ineffi-

ciency values, the first-orde r analysis in Section I1 predicts an

improvement of cb,/cst for the dual-gate device, compared to

the simplecircuit. By taking intoaccou nt he difference inchannel lengths, the above factor has to be multiplied by the

ratio of the simple BBD channel length to tha t of the dual-

gate device. The result is 0.023 , which is close to th e observed

improvem ent. Also no te (Fig. 9) that or V, in he range

VG- VT < V ,< V,, E increases with increasing V (absolute

value) for V, fixed. This is due to the reduction of the fring-

ing ieldbetween the bias and heactivegatewhen VB is

increased towards V, (when V, is higher tha n VG the channel

und ernea th the bias gate is no longer pinched off and acts as

a simple series resistance). In term s of saturation conductance,



1814 IEEE TRRXSACTIONS ON ELECTRON DEVICES,VOL.ED-27, NO. 9, SEPTEMBER 1980

t i

tVG i- 0

lo'

106 lo5 106

C L O C K FREQUENCY ( H z )

Fig. 8. Dual-gate bucket-brigade ransfer nefficiency as a functio:n ofclock freque ncy. The broken line corre spon ds to a simple BBD clhiftregister having 5-pm channels (40 pm wide) and a storage capacitanceof 0.4 F.

10-1 I I I I I I I I I

vo.-20v

$ lo-*-2 .

f c = 5 0 0 K H z

w .i!u -U

103:-E -wL C .v)

5 166:E .I-

1 0 - 5 ~ ~ ' ~ ~ ~ ' " .-10 -12 -l L -16 -10 -20

B I A S G A T EO L T A GE I V

Fig. 9. Measured transfer inefficiency versus bias gate voltage for th.reedifferent clock frequencies.

g& increaseswith V,, as will be illustrated ater on in this

section.The regime in which V, is not low enoughwith

respect to VG to pinch off he channel underneath he bias

gate corresponds to an incomplete (bias) charge-transfer mode

of oper ation of the "CCD" half cells of the dual-gate B13D.

When V, is reduced below approximately VG- V,, another

mechanism comes int o play at higher clock rates. TMIS s the

intrinsic transfer rate lim itation associated with the fir:;t trans-

fer in the dual-gate BBD cell, resulting in th e term el i in (3).

Indeed, the low bias voltage plot in Fig. 8 (V, = - 12V) showsa more rapid increase with clock frequency above abo ut 100

kHz. Also, the 5 00-kHz plot in Fig. 9' shows a decrease of e

with ncreasing VB for ow V values,which onfirms the

conclusion that he contribu tion of e l l is significantat low

bias gate voltages and high clock rates.

From the poin t of view of dynamic range, V, should be as

high as possible. Howe ver, as evidenc ed in Fig. 9, the choice ofV , only within an optim um range yields a minimum transfer

inefficiency. The upp er limit of this optimum range is on the

order of VG- V,. The choice of V, is critical only at higher

clock requencies, bu t sincenormally V, is derived on-chip

- 1 ' I

O 10 20 30 LO

G A T EV O L T A G E V I

Fig. 10. Dual-gate M OSFET outp ut cond uctan ce in saturation versusgate voltage for diffe rent bias gate voltages. L g = 8.5 pm, L b = 15pm, and W = 64 pm. The dashed line corresponds to a norm d t ran-sistor having the gatedefined by he secondaiuminumdeposition.The channel width s the same and the channelength is 11pm .

(from the VDD upply) it has to be set regardless of the oper-

ating rate. Concerning the clock frequency figures mention ed

in the preceding discussion, it shou ld be kept i n mind tha t the

dual-gate BBD under consideration has rather ong channels,

large storagecapacitances,anda owcarriermobility.Thus

other :structureswithmproved lectrical nd eom etrical

parameters mayexhibit ow-frequencycharacteristics up o

much higher clock rates.

In order t o get m ore insight into the behavior of the dual-

gatecell,measurementswereconducted on individualdual-

gate MOST'S on thesame chip. Emphasis was directed towa rds

the outp ut cond uctanc e in saturatio n, which is directly deter-

minedby hannel-lengthmodulation.Typical xperimental

results for gd, as a function of VG , with VB as a parameter,

are shown in Fig. 10. The dual-gate FET has the same L, as

the BBD half cell. T he brok en line stan ds for a normal single-

gate) transistor with a slightly longer channel.

Th eplots in Fig. 10 show that , incontrast to anormal

MOSFET whose g& increases uniformly with increasing gate

voltage,he aturation con du ctm ce of a ual-gate device

exhibits a maximum and hen decreases with ncreasing VG .It also depends on he dc voltage applied to the bias gate.

In he dual-gate ransistor, he urfacepotentialunder he

activegateacts as drain bias for he device under he irst

gate the irst ransistor) and is a unction of bot h VG an d

the actually applied drain voltage VD . Fo r VD fixed, a change

in VGresults in a modification of the effective drain potential

for he first ransistor.Thus or VG smaller than VB - V$

(where V$ is a hresholdvalue), he irstchannel is belowpinchoff and g& of the dual-gate MOSFET is practically th e

saturationconductanceof he econd ransistor, ncreasing

consequentlywith VG. As VG approaches V, - V$, gds

levels o ff, departing from normal ransistorbehavior.The

pointofmaximum g& approximately orresponds to the

saturatio n of the first transistor, which results n the "tetrode"

effect. The larger VB (absolute value), the more difficult it is

to pinch off the channel, so tha t the peak moves toward larger

gate voltages as VB is increased and obviously also ncreases.

Thisexplains the behavior of the dual-gate BBD cell with

respect t o bias gate oltage discussed earlier.Beyond the



BARSAN: DUAL-GATE BUCKET-BRIGADE DEVICES 1815

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J I / ,

0 - 5 -10 -15 -20 -25 -3 0

B I A S G A T E O L TA G E ( V I

Fig. 11. Dependence of the saturat ion output conductance gds on biasgate voltage VB , for hreediffere nt dual-gate transistors. All threehav e th e s q e channel width W = 64 elm. Transistors A an d B onlydiffer throu gh bias gate length, whereas B an d C have different activechannel lengths. The broken l ine shows the output conductance of anorma l MO SFET whose chann el length equals the sum of L , and Lb,of the dual-gate transistor B .

pincho ff point, he dual-gate MOSFET current is controlled

by he first ransistorwhoseeffective“drain”voltage is in-

creased by increasing VG (this being the operat ing regime of

the dual-gate BBD).As a onsequence, gds decreaseswith

increasing VG,normally going t o z ero orvery large gate

voltages,and his is shown to be the case formoderate VB

values. For bo th VGand VB arge (high current levels), a nega-

tiveconductanceeffect shows up n Fig. 10 . Thiscould be

explained b y the decrease of mobility with increasing tempera-

ture in the ocally heated channel at high power levels [171 .In o rder t o assess more clearly the effect of the bias gate,

experimental results for gds measured on different dual-gate

MOST’S are show n in Fig. 11 as functions of V B . The output

conductance increases linearly with VBup to t he point where

the first transistor of the dual-gate evice is no longer saturated.

A direct observation is that a longer bias gate allows bett er

cont rol of the dual-gate ransistorparameters, as exp ecte d.

However, even a 2.5-pm bias gate s able to significantly reduce

gds of an 8.5-pmdual-gate device from hat of anormal

MOSFET,provided VB is lower than VG. When VB equals

VG, he output conductance is abou t the same as that of the

normal transistor whose channel length is equal to L , t Lbg .

If the bias gate is muc h shorter than the active channel (case

C), gds tends to be less dependent on V B . It follows that the

relative length of the bias gate with respect to th e active gatealone is of consequence. Although he onger he bias gate,

the smaller theoutputconductance,our results how tha t

significant improvement over equivalent normal MOSFET’s

is possible even w ith bias gates 3 to 4 times shorter than the

active channel.

V. CONCLUSIONS

Due to a elativelyhighdegree of processingcomplexity,

CCD’s are less accessible CTD’s than BBD’s. On theother

h a n 4 BBD’s can be easily fabricated, but they offer poor per-

formances, mainly from the point ofiew of transfer efficiency.

A novel two-step transfer CTD concept (combining the BBD

and CCD principles)hasbeendescribedandexperimentally

verified. Th e dual-gate BBD achieves charge-transferperfor-

mancescomparable to surface-channel CCD’s. T heprincipal

advantage s of his new str uct ure over existing BBD’s can be

summarized as follows:

lower transfer inefficiency (more than an order of magni-

tude smaller than hat of simple BBD’s and up o an

order of magnitude smaller ha n that of tetrod e BBD’s);

larger high-frequenc y imit and higherpackingdensity

than tetro de BBD’s;

larger dynamic range (higher allowable inpu t swing and

lower noise).

conceptha sbeen mpleme nted using p-channel Al-gate

technologyn onjunctionwithhadowed-gaploat-off

processwhichyieldedself-alignednonoverlappingbiasgates

separated rom the clockbuses by reproducible ubmicron

gaps (typically 0.5 pm). The high yields proper to p-channel

aluminum-gate technology were not affected by the additional

process.ransfernefficiencieselowt 100 kHznd

below at MHz have beenurrentlybserved,espite

the low carrier mobility (140 cm 2 /V s).

The opera tion of the dual-gate BBD has been discussed andthe experimental results have been interpreted. Measurements

on individual dual-gate M OSFET’s having the active gate near

the drain thebuildingblocksof the novel CTD structure)

have revealed a dependence of the saturatio n output conduc-

tance on gate voltage diffe rent from that of single-gate tran -

sistors. The behavior of gdshas been explained and correlated

with the observed operational performances of he dual-gate

bucket brigade.

AC KNOWLEDGMENT

Theauthor wishes to han k A.Delibaltov who provided

invaluablehelpduring the developmentalprocessing tage.Th eassistanceof S . Prisecaru in the SEM evaluationsand

of G. Voicu in the measurements is appreciated. Continuous

supp ort and encouragement from C. Bulucea is also gratefully

acknowledged.

REFERENCES

[11 C. H. Skquin and M. F. Tompsett , Charge Transfer Devices, suppl.8 to Advances in Electronics and E lectron Physics. New York:Academic Press, 1975 .

[2] W. S. Boyle and G. E. Smith, “Charge coupled semiconductordevices,” Bell Syst. Tech. J . , vol. 49, pp. 587-593, Apr. 1970 .

[ 3 ] F. L. J. Sangster and K. Teer, “Bucket-brigade electronics-Newpossibilities for delay, timeaxis conversion, and imaging,” IEEEJ. Solid-state Circuits,vol. SC-4, pp. 131-136, Jun e 196 9.

[ 4 ] K. K. Thornber, “Incomplete charge ransfer in IGFET bucket-brigade sh ift registers,” IEEE Trans. Electron Devices,vol. ED-1 8,

[5] C. N. Berglund and H. J. Boll, “Performance limitations of theIGFET bucket-brigade shift register,” IEEE Trans. ElectronDevices, vol. ED -19, pp. 852-860, July 1972 .

[ 6 ] C . N. Berglund and K. K. Thorn ber, Incom plete transfer incharge-transfer devices,” IEEE J. Solid-state Circuits, vol. SC-8,

[ 7 ] -, “A fundamental comparisonof incom plete charge transferin charge transfer devices,” Bell Syst. Tech. J., vol. 5 2, pp. 147-182, Feb. 1973.

[ 8 ] W. J. Butler, M. B. Barron, and C.McD. Puckette, IV , “Practicalconsiderations for analog operation of bucket-brigade circuits,”IEEE J. Solid-state Circuits,vol. SC-8, pp. 157-168, Apr. 1973.

[91 D. D. Buss and W. M. Gosney, “The effect of subthreshold leakageon bucket-brigade device operation ,” presented at he Device

Research Conf., Edmonton, Alta., Canada, June 1972.

pp. 941-950, Oct. 1971 .

pp. 108-116, Apr. 1973.



1816 IEEE TRANSACTIONSN ELECTRONEVICES, VOL.D-27, NO. 9, SEPTEMBER 1980

[ l o ] F. L. J . Sanster, “Integrated bucket-briga de delay line using MOStetrodes,”PhiZips Tech. Rev., vol. 31, p. 266, Aug. 1970.

[ l l ] L. Boonstra and F. L. J. Sangster, “Progress in bucket-brigadecharge-transfer devices,” in IEEE Solid-state Conf., Dig. Tech.Papers, pp. 140-141, Feb. 1972.

[ 1 2 ] W. P. Noble, Jr., “Sho rt-channe l effects in dual-gate field effecttransistors,” in IEEE Int . Electron D evice Meet., T ech. Dig.,pp. 483-486, Dec. 1978.

[ 1 3 ] L. G. Heller and H. S. Lee, “Chargetransfer device modeling,”Semicond. Silicon, pp. 814-828, 1973.

[14 1 N. Weste and J. Mavor, “MOST amplifiers for performing periph-

eral integrated-circuit function s,” IEE J. Electron. Circuits Syst.,vol. 1, pp. 165-172, Sept. 1977.

[ I S ] V. A. Browne and K. D. Perkins, “Buried-channel CCD’s withsubmicron electrode spacings,” in Proc. Int. Charge-CoupZedDevices Conf., pp . 100-105, Oct . 1974.

[ 1 6 ] -, “A nonoverlapping ate harge-couplingechnology forserial memory and signal processing applications,” IEEE J . Solid-State Circuits, vol. SC-11, pp. 203-207, Feb. 197 6.

[ 17 1 D.Sharma, J . Gau tier, and G. M erckel, “Negative dynam ic resis-tance in MOS devices,” ZEEE J . Solid -state Circuits, vol. SC-13,pp. 378-380, June 1978.

Charge-Transfer Noise Theory for Surface-ChannelCharge-Coupled Devices

YASUHISA DMURA A N D KUNIKI OHWADA

Abstra ct-The detailed expression of charge-transfer noise or surface-

channel CCD’s is derived from the surfacegeneration-recombination

rate equation. Not on ly the charge fluctuation due to occupied inter-

face states but also th at due to unoccupied interface states are taken

into accou nt. The derived expression can explicitly predict he spec-

trum intensity dependences on the signal charge concentration and theclock frequency for various amounts of the fat-zero charge. The com -

parison betwee n th eory and experim ental esults shows good agreementover a wide range of signal charge concentration and clock frequency.

It is shown tha t charge-transfer noise depen ds heavily on the ratio

of the signal charge concentration to the clock frequencyand he

cap ture cross section in the absence of fat-zero charge. Fo r the small

ratio, the charge fluctuation is uled by the ransfer-process noise which

is determined from the amount of uno ccupied interface states. For the

very large ratio, the storage-processnoise which isdetermined rom

the interface s tate distribution over the b and gap ru les the charge fluc-

tuation. Fat-zero charge hardly reduce s he transfer-process noise forthe small ratio. For the large ratio, he fat-zero charge enhances the

total transfer noise.

I. I N T R O D U C T I O N

N OISE ORIGINS have been analyzed so far norder to

apply charge-coupled devices t o low-noise analog devices

[11 , [2 ] . Thornber and Tompsett [3] have propos ed that the

charge-transfer noise is attributedmain ly o transfer neffi-

ciency , and that there is a correlation between charge fluctua-

tion s in each pair of adjacent charge pack ets. They classified

charge fluctuat ions into the transfer-p rocess oise which is due

to correlation and the storage-process noise w hich is indepen-

dent of correlation. They derived the noise spectrum formula

Manuscript received November 1 , 197 9; revised April 20, 1980.The authors a re with Musashino Electrical Communication Labora-

tory, Nippon Telegraph and Telephone Public Corporation , Musashino-shi, Tokyo, 180 Japan.

which consists of the transfer-process noise spectrum and the

storag e-proc ess noise spectru m. Noise spectrum characteristics

were experimentally demonstrated for a high clock frequency

(-1 MHz) [4] , [SI. On the other hand,Carnes and K osonocky

[6] have estimated the storage-process noise and the transfer-

process noise on thebasis of the surface generation-recombina-

tion theory [7] , [8 ]. They have considered that the transfer-

process noise is onlydue to interfacestatesoccupied by a

fat-zero charge . However, it can be considered, n fact, hat

not only occupiednterface states but lso unoccupied interface

states contribute t o the charge fluctuation during a transfer-

in period and a transfer-out period.

In his paper, an advanced heory on charge-transfer noise

spectrum is presented as an explicit fun ction of signal charge

concentration, at-zero charge concentration,andclock fre-

quency or urface-channel harge-coupled devices. In this

theory, charge -transfer noise is also classified into the storage-

process noise and the transfer-process noise. Th ose are derived

from hesurfacegeneration-recombination ateequationon

the basis of he Shockley-Read -Hall statistics. It is regarded

that ransfer-process noise is notonlydue o heoccupied

interface tatesbu t also theunoccupied nterface tates. tis also regarded that the storage -process noise consists of the

charge fluc tuation with the signal charge under the electrodeand the charge fluc tuat ion due to the emission process during

the ransfer-out period. The comparison between he heory

andexpe rime nts is carried out over a wide ange of signal

charge concentration, fat-zero charge concentration, and clock

frequency for the verification of the theory. Physical origins

of charge-transfernoise, omeeffectsattributed to energy-

dependent profile of interface states, and noise dependence on

the captur e cross section are discussed in detail.

0018-9383/80/009-l.816$00.75 0 1980 IEEE

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Dual Gate Bucket