Dynamic Traffic Control

Group 2Chun Han ChenTimothy Kwan

Tom BoldsShang Yi Lin

ManagerRandal HongWed. Dec. 3

Project Objective :

Dynamic Control of Traffic Lights

Marketing Project Description Design Process Floor Plan Evolution Layout VerificationIssues Encountered Specifications

Presentation Outline

Marketing / Description

Tom Bolds

Current System

The current system has sensors that detects cars leaving their lanes Induction loops under the pavement Video cameras

Depending on the time of day, the intersection lets each arm go for a set amount of time

If no cars are present in one arm, the other arm is green

It cannot learn or adapt Cost for entire system: $35,000

A Better System

This system detects cars entering and leaving each arm

The time that an arm is green is determined in part, by past traffic

Exceptional traffic flow will change the system immediately

Cost for entire system: $24,000

Market

4 Million traffic lights in the USA few user inputs lets the system be

adjustable for different situationsRoads of different sizesDifferent space constraints

Price goes down and quality goes up

Goals

When the government is involved, cost needs to be low

Only 4 metal layers usedOptimized for small size

Could have gone the “all pseudo-nmos” route

We don’t want to use megawatts on a traffic light

Cmos logic to minimize size and power consumption

Goals

Even if it causes just a few accidents nobody will buy it, and we get sued

Design needs to be robust Handle power failures

Return to a known state Predictable behavior

People are used to driving a certain way No accidental switching

Minimum time for lights to change

Installation

The only change necessary would be the detectors for entering/leaving carsCurrent system has ground sensors or

video camera to detect the first car at an intersection

Could add another detector farther back, or use video/sound detection to determine where cars are

Traffic Flow

Sensors (Blue)To detect the car entered

Sensors (Red)To detect the car leaved

Traffic Light Flow

Whenever pedestrian push the button, then this light will insert in the end of this cycle.

ARM 1

ARM 2

Red

Green Y

Green (Straight + Right) Y Red+Green(Left)

Red

Y Red

Green (Straight + Right) Y Red+Green(Left) Y

Phase A

Phase C

Phase B Phase A Phase BARM1 ARM1 ARM2 ARM2

PED

We define three phases (A,B,C) for different operations.

Hold until n1 or n2 changes

Light favorsn1 or n2 ?

n1 n2

T<r1? T<r2?

T>= R1?

T>= R2?

n1=0?

n2=0?

f1<=0?

f2<=0?

Switch Light

ResetT = 0

No

Yes

Yes Yes

YesYes

Yes YesNoNo

No

No No

No

Yes

No

Light favorsarm1 or arm2 ?

n1 n2

T<rleft? T<rleft?

T>= Rleft? T>= Rleft?

No

Yes

Yes Yes

YesYesNo

No

Yes

Non1 not change in T = 5?

No

No

Control

reset Pedestrian For Green light

For Red + Left

T>= Rp ?

Yes

No

For Pedestrian

n2 not change in T = 5?

n1, n2 :# of carsT :Time spent in this phaseRi , ri : Max. and Min. time for each phasefi : the control functionf1 = α1*n1+ β1 – n2 f2 = α2*n2+ β2 – n1

SW – Switch light

G – Green

R – Red

Y – Yellow

T – Time for Yellow

PED – Pedestrian

SW (1bit)

ARM (1bit)

PED(1bit)

T (2bits)

Phase(2bits)FSM

Initial

G.R

Y.R

R+Left.R

Y.R

R.G

R.Y

R.Y

R.R+Left

PED

SW = 0 SW =0

SW = 1 SW = 1

T < 2 T < 2

T = 2 T = 2

SW = 1 SW = 1

SW =0

SW = 0

PED = 1

T = 2

PED = 1

T = 2

T<= 2 T<= 2

SW = 0

SW = 1

T = 2

PED = 0

T = 2

PED = 0

ARM = 0 ARM = 1

Init. Ped = 0Choose the Phase

Learning?

The way we learn is by changing beta To take out the division, multiply

everything else by Qlen

We are actually calculating f*Qlen, but it works since it only matters if it’s < 0

Qavg2Qlen

Qlen Qavg2

User Input Q

User Input R,r

Accum Reg

11

11

11ENTER

11

Accum Reg

1111

OUT /

LEFT

s0,s1: X 2

q0,q1: X 2

Reg X 10

1111

Reg X 10

2:1 MUX

110

110 11 X 10

11 X 9

11 X 1

q0q1

1111

11β

n1n0

11

1111

Q_len1111

16:1 MUX

4Sel

11

s0s111

11

1111

11

11

1111

1111

Sel4

N_avgαn0-n1

αn0

q0-s0

q1-s1

α0

α1

Q(αn0-n1)

ALU

2Sel_ALU

1:16 De-MUX

4

Sel

12 111

Reg X 9

12 bit

Reg X1

11 bit

n0n1

ROM

11

1111

β

2:1 MUX

12

n_avg

Q(αn0-n1)q1-s1

q0-s0

αn0

αn0-n1

11

F

α0,α1: X 2

ROM

Reg

Reg

8X8

8 X 8 8X8

11

11 11

8 X 8 : Dot Line to Comparator

R,r, RL,rl for Arm1 Arm2

11

½

2:1 MUX

Dot Lint to FSM

β

8 X 8

2 : 1 MUX

INT.

Compar1

FSMSW

ARM

CLK

Clear

FSM

1

Complete

ARM 1

ARM 2

PED1

2

2

½

11 11

ROM

11

11

User Input2:1 MUX

Reg11 11

Accmu8

1Clk Div.

8Accmu

1

Left-Turn Counter

T

8

88

Reg

Reg8

8

8

8

System Clock 1

PED 1

1

11

1

R & r, R_L& r_L

Sel_C

Ser_D

3

1

4X332 Sel_ALU

Sel_C

Sel

ARM

n0 = 0

n1 = 0

F <= 0

8 : 1 MUX

n0

n1

F

1 Sel_D

System Clock

Trigger, when cars go left turn

ARM

1

1 1

1

Shifting

Shifting1

Data Input

Initial Values

Clock

Operation

T, Left-Turn Counter

R, r, R_L, r_l

Flow Control FSM

Light Control FSM

Selection

Design Process

Shang-Yi Lin

Design Process – Objective

Goal - Compact Area

- Low Power Trade-Off - Performance

Behaviors / Flow Charts

Behavior Verilog / JAVA

Structural Verilog / Structure

Schematic / Cadence

Layout / Virtuso

Extracted RC / Simulation

Design Process - Overview

Finalize Chip Functionality- Make behaviors, function clear

Feasible & Reasonable Algorithm - Complex & Fast != Good Design

Design Process – Behaviors

Order of Traffic Light Traffic Light FSM Flow Control FSM

Design Process – Verilog / JAVABehavior Verilog & JAVA

Design Process – StructureBlock Diagram :

- Behavior Verilog to Structural Verilog - Data path and function blocks are determined- Initiate Floorplan

Floor Plan : - Routing Issue

Re-Use of Components :- Decrease Chip Area

Design Process – SchematicCompact Design :

- Minimize transistor count

Transistor Sizing :- Minimize transistor size- Equivalent Pull-Up & Pull-Down ability

Implementation : - Put reasonable output loads for simulation- Sized buffers for global control signals

Design Process – LayoutDefined the Metal Directionality :

- M1 & M2 : Local, power rails - M3 & M4 : Global, Control, Clock- Special Case : Depended

Focus on Compact Layout :- Floor plan keeps updating- Consider the interconnect between blocks

Global Routing :- Fixed height for most blocks - Use wider global wires- Leave wiring space

Block Level- Extracted RC simulation for each block - Combine multiple blocks to simulate

Chip Level- Ensure global signals integrity- Whole chip simulation

Design Process – Extract RC

Floorplan Evolution

Shang-Yi Lin

Floor Plan First Version

- Block Diagram- Sample Layout Size

Routing Issue Re-Use

Components

Register (1bit)2X1 MUX

16.613.5

6.5

6.6

InputGet q0 q1 s0 s1

Avg. q

½ , Q_L

FPU Output

Reuse

F , Ni

Give R,r Input PED, CLK

Compare T

Control Light

Floor Plan – 1st Version

Floor Plan – UpdateStructure : Logic components are determined

Layout : Refined Function Block

Floor Plan – Update

Refined LayoutMore Precise Layout Shape & Size

More and More

More and More…

Doing Global Routing

Final Layout

Layout / Verification

Chun Han Chen

Layout - ALU

Input Output

Layout – FSMs

Timing Control FSM

Light Control FSM

Counters

Shift Registers

MUX

Layout – Memory Devices & Interconnection Parts

Counters Shift Registers

and MUXs

Counters

Shift Registers

2:1 MUX

11-bits 16:1 MUX

Layout – Memory Devices & Interconnection Parts

Input

Select

Output

Layout – Memory Devices & Interconnection Parts

Real time counter, MUX, and, Comparator

Output to Timing Control FSM

Layout – Memory Devices & Interconnection Parts

Control + Registers

Control Logic

Output

Input from ALU

Layout – Whole Chip

Layout – Whole Chip

Verification – MethodologyFunctionality Validation

-Java V.S. Behavioral Verilog

-Behavioral Verilog V.S. Structural Verilog

Schematic Checks-Structure Verilog

V.S. SchematicLayout Verification

1.Whole chip extracted RC simulation by using Ultrasim

2.Comparing the results with schematic simulation

3.Separated simulations for pedestrian signal

Verification – Methodology Extracted RC for the whole chip

Verification – Light Switching

Switch

Continue

Verification – Pedestrian

Specification Issues Encountered

Timothy Kwan

Specifications Area = .146270 mm2

498.69 x 293.31 um^2 1:1.7002 Aspect Ratio

Transistors 18834 Total8613 pmos10221 nmos

Density .1288 transistors / um^2

Speed 10 MHz

I/O’s 74 inputs 5 outputs

Issues Encountered

MuxzillaLarge consecutive pass transistor muxes

Floor plan Increasing number of transistors led to larger

blocks12000 => 18834

Wire RoutingMetal DirectionalityLarge Number of WiresI/Os

Complicated FSM Logic and glitches

Issues Encountered

Large Fan Out in Some BlocksSystem Clock and Real Time Clock

Timing Issues Arithmetic Unit or Floating Point

UnitSimulation Issues

New vs. Old CadenceUltrasim vs. Spectre

?