[M2] Traffic Control

Group 2Chun Han ChenTimothy Kwan

Tom BoldsShang Yi Lin

ManagerRandal HongWed. Nov. 05

Overall Project Objective :

Dynamic Control The Traffic Lights

Status

Design Proposal Chip Architecture Behavioral Verilog Implementation Size estimates Floorplanning Behavioral Verilog simulated Gate Level Design Component Layout/Simulation Chip Layout Complete Simulation

User Input Q

User Input R,r

Accum Reg

11

11

11ENTER

11

Accum Reg

1111

OUT /

LEFT

s0,s1: X 2

q0,q1: X 2

Reg X 10

1111

Reg X 10

2:1 MUX

110

110 11 X 10

11 X 9

11 X 1

q0q1

1111

11β

n1n0

11

1111

Q_len1111

16:1 MUX

4Sel

11

s0s111

11

1111

11

11

1111

1111

Sel4

N_avgαn0-n1

αn0

q0-s0

q1-s1

α0

α1

Q(αn0-n1)

ALU

2Sel_ALU

1:16 De-MUX

4

Sel

12 111

Reg X 9

12 bit

Reg X1

11 bit

n0n1

ROM

11

1111

β

2:1 MUX

12

n_avg

Q(αn0-n1)q1-s1

q0-s0

αn0

αn0-n1

11

F

α0,α1: X 2

ROM

Reg

Reg

8X8

8 X 8 8X8

11

11 11

8 X 8 : Dot Line to Comparator

R,r, RL,rl for Arm1 Arm2

11

½

2:1 MUX

Dot Lint to FSM

β

8 X 8

2 : 1 MUX

INT.

Compar1

FSMSW

ARM

CLK

Clear

FSM

1

Complete

ARM 1

ARM 2

PED1

2

2

½

11 11

ROM

11

11

User Input2:1 MUX

Reg11 11

Accmu8

1Clk Div.

8Accmu

1

Left-Turn Counter

T

8

88

Reg

Reg8

8

8

8

System Clock 1

PED 1

1

11

1

R & r, R_L& r_L

Sel_C

Ser_D

3

1

4X332 Sel_ALU

Sel_C

Sel

ARM

n0 = 0

n1 = 0

F <= 0

8 : 1 MUX

n0

n1

F

1 Sel_D

System Clock

Trigger, when cars go left turn

ARM

1

1 1

1

Shifting

Shifting1

Data Input

Initial Values

Clock

Operation

T, Left-Turn Counter

R, r, R_L, r_l

Flow Control FSM

Light Control FSM

Selection

Old Version Wire routing on each block

Old

Version.2

Current

Version

16:1 MUX (11bits)

Data Input Routing

We think the current layout of 16:1MUX (11bits) is not good enough.

Because of the Data Inputs Routing, it is very complex, now. (you can see the Data input routing picture)

Maybe, we should refine the layout to this way. (16 inputs can pass thru single one 16:1 MUX,

Using the same metal for inputs (should be M3, Vertically. ) The overall size should be bigger than version_1, but it might decrease the complexity of global routing.

The floorplan would be a little bit different.

16:1 MUX 16:1 MUX16:1 MUXX 11bits

Some Global Routing IssuesThe outputs of Shift Registers are not fit

the inputs of 2:1 MUX It may waste some areas when we route

the wires between this two blocks

Tom’s FSM

Large blocks LVS, but not too significant, because they don’t have too much interconnect

What is significant is wiring it all together

Floorplan done for wiring the whole FSM together

Inputs from bottom, outputs bottom or left

Tom’s FSM

Layout for Light Control FSMAll blocks are connected together and

try to make them as compact as possible.

Need some time to do another layout for counter reset to fit in light control FSM.

DRC and LVS clean.

FSM Next State

•Fatter and shorter. Waste some area for routing but make the whole FSM more compact.

Previous UpdatedHeight:85.86umWidth:6.48um

Height:46.26umWidth:17.28um

FSM TOP

•Revised layout for light control FSM.•Height=68.94 ,Weight= 61.38.•Need some time to fit counter reset block into the FSM to make it more compact.

FSM TOP

•More detail in the layout. (Some additional lines are used for passing LVS) •DRC and LVS clean.

User defined inputs

Global signalsCLK,RESET etc.

Inputs from previous FSM

Outputs

Combinational Part

Sequential Part

IssueMaybe I can use the counter reset block

to fill the space to make it more compact. Need some time to modify it.

Maybe I should help others first before optimizing this FSM.

ALU Update

RCA Adder – 100% DRC + LVS completed

Array Multiplier – 65% Scrapped old one, too many wiring mistakes/missing many

wire interconnects, seemed more efficient to work from scratch

What’s left?A few more AND Gates connections to Full Adders

Only left enough room for 5-7 wires height wise…really need to get 12 wires(at worst) in there

Increasing Height => No, not going to double to height given Area is already close to initial estimate

Weird/Messy Wiring =>Yes, no otherway around it and it works

Attach HalfAdders+and to Array of Full adders+AndBus wire around the array to inputs

RCA Adder(DRC + LVS Clean)

4xRow Full Adder(Array Mult)DRC=Clean

LVS = Clean (minus AND Gates)

Close up on AND

Question ?