Ec 6211 Final From Ece

8/10/2019 Ec 6211 Final From Ece

1/106

Circuit Diagram:

PN-Junction Diode:

Forward Bias:

Reverse Bias:

Symbol:

1


2/106

E!t" No": Date:

C#aracteristics o$ PN-Junction Diode

%im:

To plot the forward and reverse bias characteristics of a PN diode and tocalculate cut-in voltage, forward resistance and reverse resistance.

%!!aratus Re&uired:

S" No 'tem Range (ty

1. Diode 1N4007 1

. !esistor 1"# 1

$. %olt&eter D' (0-1%) 1

4. *&&eter D' (0-$0&*) 1D' (0-+00*) 1

+. !P D' (0-$0)% 1

)#eory:

* diode is a PN unction for&ed b/ a la/er of a P t/pe and la/er of N t/pe

se&iconductors. nce for&ed the free electrons in the N region diffuse across the

unction and co&bine with holes in P region and so a depletion a/er is developed. The

depletion la/er consists of ions, which acts li2e a barrier for diffuse of charged be/ond

a certain li&it. The difference of potential across the depletion la/er is called the barrier

potential. *t .+ degree the barrier potential appro3i&atel/ eual to 0.7v for ilicon

diode and 0.$% for 5er&aniu& diode. 6hen the unction is forward biased, the

&aorit/ carrier acuired sufficient energ/ to overco&e the barrier and the diode

conducts. 6hen the unction is !everse iased the depletion la/er widens and the

barrier potential increases. 8ence the &aorit/ carrier cannot cross the unction and the

diode does not conduct. ut there will be a lea2age current due to &inorit/ carrier.


3/106

*odel +ra!#:

PN Diode ,-' C#aracteristics Curve

)abular Column:

Forward Bias:

S" No" Forward ,oltage ,f. Forward Current 'f.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

$


4/106

Procedure:

Forward Bias:

1. The connections are &ade as per the circuit diagra&.

. The positive ter&inal of power suppl/ is connected to anode of the diodeand negative ter&inal to cathode of the diode.

$. 9orward voltage %facross the diode is increased in s&all steps and the

forward current is noted.

4. The readings are tabulated and the graph is drawn for %fversus :f.

+. The forward resistance is found fro& the graph using the for&ular$ 9 ,$; '$"

Reverse Bias:

1. The connection as &ade as per the circuit diagra&.

. 9or reverse bias the positive ter&inal of the power suppl/ is connected

to cathode and negative ter&inal to anode of the diode.

$. The power suppl/ is switched N, the reverse bias voltage %f is

increased in steps and reverse current :ris noted in each steps.

4. The readings are tabulated and the graph is drawn for %r%ersus :r.

+. The reverse characteristics are appro3i&atel/ a straight line, inverse ofthe slope give the reverse resistance.

;. The reverse resistance is found fro& the graph using the for&ularr 9 ,r; 'r"

4


5/106

Reverse Bias:

S" No" Reverse ,oltage ,r. Reverse Current 'r.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

+


6/106

Result:

Thus the characteristic of PN-


7/106

Reverse Bias:

Symbol:

7


8/106

E!t" No": D%)E:

C#aracteristics o$ ener Diode

%im:

To plot the %: 'haracteristics of a >ener diode and to deter&ine the ?ener

brea2down voltage and >ener brea2 down current

%!!aratus Re&uired:

S" No 'tem Range (ty

1. >ener Diode > ;.@ % 1

. !esistor 1"# 1

$. %olt&eter D' (0-10%) 1

D' (0-1%) 1

4. *&&eter D' (0-+0&*) 1

+. !P (0-$0)% 1

)#eory:

>ener doide is a special diode with increased a&ounts of doping. This is to

co&pensate for the da&age that occurs in the case of a PN unction diode when the

reverse bias e3ceeds the brea2down voltage and thereb/ current increases at a rapid

rate.

*ppl/ing a positive potential to the anode and a negative potential to the

cathode of the ?ener diode establishes a forward bias condition. The forward

characteristic of the ?ener diode is sa&e as that of a pn unction diode i.e. as the applied

potential increases. The current increases e3ponentiall/. *ppl/ing a negative potential

to the anode and positive potential to the cathode reverse biases the ?ener diode. *s the

reverse bias increases the current increases rapidl/ in a direction opposite to that of the

positive voltage region. Thus under reverse bias condition brea2down occurs.

@


9/106

*odal +ra!#

ener Diode ,-' C#aracteristics Curve

)abulation:

Forward Bias:

S" No" Forward ,oltage ,f. Forward Current 'f.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

A


10/106

Procedure:

Forward Bias:

1. The connections are &ade as per the circuit diagra& for forward bias.

. The positive ter&inal of power suppl/ is connected to anode of the diodeand negative ter&inal to cathode of the diode.

$. 9orward voltage %facross the diode is increased in s&all steps and the

forward current is noted.4. The reading is tabulated.+. * graphs is drawn between %fand :f.

Reverse Bias:

1. The connections are &ade as per the circuit diagra& for reverse bias. The positive ter&inal of the power suppl/ is connected to cathode and

negative ter&inal to anode of the diode.$. The power suppl/ is switched N4. The reverse bias voltage %r is increased in steps and reverse current :r is

noted in each steps.+. The readings are tabulated.;. * graph is drawn between %r and :r. The reverse characteristics is

appro3i&atel/ as straight line, inverse of the slope give the reverse

resistance

10


11/106

Reverse Bias:

S" No" Forward ,oltage ,r. Forward Current 'r.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

11


12/106

Result:

Thus the characteristics of >ener diode were drawn and the followingpara&eters are deter&ined.

>ener rea2down %oltage= %

>ener rea2down 'urrent= &*

,',% (


13/106

Circuit Diagram:

Pin Diagram:

)o! view o$ BC 0/6

*odel C#aracteristics Curve:

a. 'n!ut Curve

1$


14/106

E!t" No": D%)E:

Common Emitter in!ut-out!ut C # a r a c t e r i s t ic s

% im :

To deter&ine the input and output characteristics of 'o&&on B&itter ('B)

configuration and 'alculate the h-para&eter values fro& the input and output

characteristic curves.

% ! ! a r a t us R e& u i r e d:

S" No" Name Range (ty

1 !P D' (0-$0)%

*&&eter

D' (0C10)&* 1

D' (0 C +00) ,* 1

$%olt&eter

D' (0C$0)% 1

D' (0C1)% 1

4 Transistor ' 107 1

+ !esistor 12#

; read oard - 1

7 'onnecting 6ires -*s per

reuire&ent.

)# eo r y :

ipolar


15/106

b. =ut!ut Curve

)a b u l a tion:

' n ! ut c # a r a c t e r i s t i c s :

1+

Sl" No%'B +% %'B 10%

%B(volts) :( &*) %B( volts) :( &*)

/0

/1

/2

/3

/4

/5

/6

/7

/8


16/106

Junction bias Condition:

S"No" Region Emitter Base Junction Collector Base Junction

1 *ctive 9orward ias !everse ias

aturation 9orward ias 9orward ias

$ 'ut off !everse ias !everse ias

:n 'B configuration, the B&itter ter&inal is connected

as co&&on ter&inal between the input and output circuit.

P r o c e dur e :

' n ! ut C # a ract e r is t i c s :

These 'urves give the relationship between the ase current (:) and ase to

B&itter voltage (%B) for a 'onstant 'ollector to B&itter voltage (%'B).

1. 'onnections are &ade as per the circuit diagra&.. *dust the 'ollector to B&itter voltage (%'B) to + volt. Then increase ase to

B&itter voltage (%B) in s&all suitable steps and record the corresponding

values of ase current (:) at each step.

$. Plot a graph with ase to B&itter voltage (%B) along E-a3is and the ase

current (:) along /-a3is. 6e shall obtain a curve &ar2ed %'B +% as shown

in fig.

4. * i&ilar procedure &a/ be used to obtain 'haracteristics at different values of

'ollector to B&itter voltage i.e., %'B 10%, 1+% etc.

= ut ! ut c # a r a ct e r is t i c s :

These 'urves give the relationship between the 'ollector current (:') and

'ollector to B&itter voltage (%'B) for a 'onstant ase 'urrent (:).

1. *dust the ase current (:) to 0* value. Then increase the 'ollector to

B&itter voltage (%'B) in nu&ber of steps and record the corresponding values

of 'ollector current (:') at each step.

. Plot a graph with 'ollector to B&itter voltage (%'B) along E-a3is and the

'ollector current (:') along /-a3is. 6e shall obtain a curve &ar2ed : 0*

as shown in fig.

$. * i&ilar procedure &a/ be used to obtain 'haracteristics at different values of

ase current (:) at 40*,;0* etc.= ut ! ut c # a r a ct e r is t i c s :

1;


17/106

17

Sl" No

: $0* : 40*

%'B(volts) :'( &*) %'B(volts) :'( &*)

/0

/1

/2

/3

/4

/5

/6

/7

/8


18/106

+ra!#ical Determination o$ #-!arameters $or CE:

1. :nput i&pedance hie F%B G F: ( for a constant %'B )

. !everse %oltage gain hre F%B G F%'B ( for a constant : )

$. 9orward 'urrent gain hfe F :' G F: ( for a constant %'B )

4. utput *d&ittance hoe F:' G F%'B ( for a constant : )

RES


19/106


20/106

E!t" No":

Date:

Common Base in!ut-out!ut C # a r a c t e r i s t i c s

% im :

To deter&ine the input and output characteristics of 'o&&on ase (')

configuration and 'alculate the h-para&eter values fro& the input and output

characteristic curves.


S"No" Name Range (ty

1 !P (0-$0)%

*&&eter

D' (0C10)Ha 1

D' (0 C 10) &* 1

$%olt&eter

D' (0C10)% 1

D' (0C1)% 1

4 Transistor ' 107 1

+ !esistor 12#

; read oard - 1

7 'onnecting 6ires -*s per

reuire&ent.

)# eo r y :

ipolar


21/106

called bias ing. There are three different wa/s of b ias ing a trans is tor ,

which are 2nown as &odes of transistor operation.

1


22/106

b. =ut!ut Curve

)a b u l a tion:

' n ! ut c # a r a c t e r i s t i c s :

Sl" No%' +% %' 10%

%B( volts) :B( &*) %B( volts) :B( &*)

/0

/1

/2

/3

/4

/5

/6

/7


23/106

Junction bias Condition:

S"No" Region Emitter Base Junction Collector Base Junction

1 *ctive 9orward ias !everse ias

aturation 9orward ias 9orward ias

$ 'ut off !everse ias !everse ias

:n ' configuration, the ase ter&inal is connected as

co&&on ter&inal between the input and output circuit.

P r o c e dur e :

' n ! ut C # a ract e r is t i c s :

These 'urves give the relationship between the B&itter current (:B) and ase to

B&itter voltage (%B) for a 'onstant 'ollector to base voltage (%').

1. 'onnections are &ade as per the circuit diagra&.. *dust the 'ollector to ase voltage (%') to + volt. Then increase ase to

B&itter voltage (%B) in s&all suitable steps and record the corresponding

values of B&itter current (:B) at each step.

$. Plot a graph with ase to B&itter voltage (%B) along E-a3is and the

B&itter current (:B) along /-a3is. 6e shall obtain a curve &ar2ed %'

+% as shown in fig.

4. * i&ilar procedure &a/ be used to obtain 'haracteristics at different

values of 'ollector to base voltage i.e., %'10%, 1+%.., etc.


These 'urves give the relationship between the 'ollector current (:') and

'ollector to base voltage (%') for a 'onstant B&itter 'urrent (:B).

1. *dust the B&itter current (:B) to &* value. Then increase the 'ollector to

base voltage (%') in nu&ber of steps and record the corresponding values of

'ollector current (:') at each step.

. Plot a graph with 'ollector to base voltage (%') along E-a3is and the

'ollector current (:') along /-a3is. 6e shall obtain a curve &ar2ed :B &* as

shown in fig.

$. * i&ilar procedure &a/ be used to obtain 'haracteristics at different values

of B&itter current (:B) at 4&*, ;&* etc.

$


24/106


4

Sl" No"

:B &* :B 4&*

%'( volts) :'( &*) %'( volts) :'( &*)

/0

/1

/2

/3

/4

/5

/6

/7


25/106

+ra!#ical Determination o$ #-!arameters $or CB:

1. :nput i&pedance hib F%B G F:B ( for a constant %' )

. !everse %oltage gain hrb F%B G F%' ( for a constant :B )

$.9orward 'urrent gain hfb F:' G F :B ( for a constant %' )

4. utput *d&ittance hob F:' G F%' (for a constant :B )

R es ult:

Thus the input and output characteristics of 'o&&on B&itter (')

configuration was plotted and the following h-para&eter values are deter&ined fro&

the input and output characteristic curves.

:nput i&pedance hib

!everse %oltage gain hrb

9orward 'urrent gain hfb

utput *d&ittance hob 9

,',% (


26/106

Circuit Diagram:

*odel +ra!#:

Drain C#aracteristics:

;


27/106

E!t" No":

Date:

C#aracteristics o$ Junction Field E$$ect )ransistor JFE).

%im :

To plot the transistor characteristics of


28/106

)rans$er c#aracteristics:

Drain C#aracteristics:

@

Sl" No"

,gs 9 /, ,gs 9 -0,

,DS ,. 'Dm%. ,DS ,. 'Dm%.

/0

/1

/2

/3

/4

/5

/6

/7


29/106

Procedure:

Drain C#aracteristics rd.:

0" 'onnections are &ade as per the circuit diagra&.1" ,+Sis 2ept constant (a/ -1%), ,DS is varied insteps of 1% and the

corresponding :D values are tabulated.2" The above procedure is repeated for ,+S0%.3" 5raph is plotted between ,DS and 'D for a constant ,+S4" The Drain resistance is found fro& the graph using the for&ula rd 9 ,DS; 'D"

)rans$er C#aracteristics gm.:

0" 'onnections are &ade as per the circuit diagra&.1" ,DSis 2ept constant (a/ +%), ,+S is varied insteps of 1% and the corresponding

:D values are tabulated.2" The above procedure is repeated for different values of ,DS910%, 1+%"3" 5raph is plotted between ,+S and 'D for a constant ,DS4" The Transconductance is found. 9ro& the graph.

g& F:DGF%5 # -1

%m!li$ication Factor G. :

*&plification factor () rdKg& (the a&plification factor value &ust not e3ceed

+0)

A


30/106

)rans$er C#aracteristics:

Sl"No

,DS9 4,

-,+S ,. 'Dm%.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

$0


31/106

Result:

Thus the Drain and Transfer 'haracteristic of


32/106

Pin diagram:

Symbol:

Circuit Diagram o$ SCR:

$


33/106

E!t" No": Date:

C # a r a c t e r is t i cs = $ Si li c o n C o n t r o ll e d R e ct i $ ie r

% i m:

To draw the %C: characteristics of the given '! and to deter&ine the gatecurrent for different anode voltage


.No. :te& Range Luantit/

1. !P (0-$0) %

. *&&eter

D' (0-10&*), 1

D' (0-100*) 1

D' (0-10&*) 1

$. %olt&eter D' (0-$0v) 14. '! '10; 1

+. read board - 1

;. !esistors 10"#, $$"# 1

7. 'onnecting 6ires - 1 set)#eory:

The '! consists of four la/ers of se&i conductor &aterial alternativel/ P t/pe

and N t/pe .:t can be brought of as an ordinar/ rectifier with a control ele&ent .The

control ele&ent is called 5ate. The gate current deter&ines the anode to cathodevoltage at which the device starts to conduct. The ter& N I 99 is used to represent

the conduction and bloc2ing &ode of '! respectivel/. nce switched N the gate

has no further control. To switch the '! the anode current has to be reduced below a

certain level called 8olding 'urrent. The '! can also be triggered N with the gate

open circuited with the anode to cathode voltage &ade large enough .:n conduction

state the '! behaves as an ordinar/ diode. The anode to cathode voltage at which the

'! conducts is called rea2 over %oltage or 9orward loc2ing %oltage.F o r w a rd C # a r a c t e r is t ic s :

6hen anode is positive w.r.t cathode, the curve between %-: is called forward

characteristic. :f the suppl/ voltage is increased fro& ?ero, a point is reached when

'!

$$


34/106

* o d e l + r a ! #:

$4


35/106

starts conducting. Mnder this condition, the voltage across '! suddenl/ drops and&ost of the voltage appears across the load resistance !. :f proper gate current is

&ade to flow, '!canclose at &uch s&aller suppl/ voltage.

R eve r s e C # a r a c t e r is t i c s :

6hen the anode is &ade negative w.r.t to cathode, the curve

between %I : is called reverse characteristics. :f the reverse voltage is increased,

avalanche brea2down occurs and the '! starts conducting heavil/ in reverse

direction. :t is si&ilar to the ordinar/ PN unction diode.

Procedure:

1. The connections are &ade as per circuit diagra&.. The switch is 2ept open.

$. The anode suppl/ is switched N and the forward voltage is set to so&edesired, value.(Bg 0 % )

4. There is no indication of current in the a&&eter and the '! is in 99state.

+. Now the 5ate suppl/ is switched N and the PT switch is closed.;. The gate bias voltage is increased slowl/.7. *t so&e value of gate current the '! will be triggering N and it is

indicated b/ the a&&eter in the anode circuit.@. *lso the voltage across the '! will suddenl/ fall to around 0.7 %. This

value of gate current reuired to trigger the '! is noted.A. Now with '! in N state the gate ter&inal is &ade open b/ opening

the PT witch The anode current is slowl/ reduced b/ reducing thesuppl/ voltage. *t so&e value of anode current the '! is turned 99.

10. This is indicated b/ a sudden rise in the volt&eter reading and the*&&eter reading will suddenl/ beco&e ?ero.

11. The anode current below which '! turns 99 is the 8D:N5'M!!BNT and is noted.

1. The '! is turned N once again and the anode current is reduced tothe 8olding level.

1$. The anode current is varied fro& holding current to 10 &* and in eachstep the forward voltage drop across '! is noted.

14. The readings are tabulated and the e3peri&ent is repeated with different

forward brea2 down voltage.

$+


36/106

)abulation $or SCR:

Sl" No"

'+ 9 G%

,%H,. '%m%.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

$;


37/106

1+. *s rea2 over voltage is increased, the gate current reuired to trigger

the '! will decrease.

1;. To deter&ine the lea2age current in the bloc2ing state the connectionsare &ade as per circuit diagra&.

17. The power suppl/ is witched N and the anode voltage is increased in

steps. The anode current is noted in each step and tabulated.

1@. The graph is plotted between forward voltage and forward current. The

brea2 over voltage and holding current are &ar2ed on the graph

Result:

Thus the given '! characteristics were drawn and the following para&etersare &easured.

8olding 'urrent (:8) &*.

rea2 over %oltage (%) %.

8olding %oltage (%8) %.

,',% (


38/106

C'PPERSPositive 'lipper=

F G

5 6 0

V o1 N 4 0 0 7

Negative 'lipper=

F G

5 6 0

1 N 4 0 0 7

V o

C%*PERS

Positive Clam!er:

F G

1 N 4 0 0 7

1 u F

V o

Negative 'la&per=

F G V o1 N 4 0 0 7

1 u F

$@


39/106

E"No: Date:

C'PPERS %ND C%*PERS

%'*:To construct and test clippers and cla&pers

%PP%R%)


40/106

Clam!ers: Cli!!ers:'n!ut Signal: 'n!ut Signal:

Positive Clam!ed =ut!ut: Negative Cli!!ed =ut!ut:

Negative Clam!ed =ut!ut: Positive Cli!!ed =ut!ut:

)abulationPositive Clam!er: Negative Clam!er:

%m!litudein volts.

Periodin sec.

%m!litudein volts.

Periodin sec.

'n!ut 'n!ut

=ut!ut =ut!ut

40


41/106

RES


42/106

Circuit Diagram

F>R wit# Filter

F>R wit#out Filter

E"No: Date:

4


43/106

F%,E REC)'F'ER >')I %ND >')I=


44/106

=ut!ut wave$orm:

)abular Column

F>R wit# Filter

,s 'n!ut ,oltage. 9-------------------

)9------------------ I

Rload

K.

,m

,.

,r!-!.

,.

,rms

9,r; 1

,dc9 ,mL,r!-!. ;1

,.

RF9,rms ;,dc

F>R wit#out Filter

Rload

K.

,m

,.

,dc9 1,m;M

,.

,rms9 ,m; 1

,.

RF9 ,rms;,dc .1-0. 0;1

44


45/106

Recti$ier wit#out $ilter

6hen no filter circuits is present, output voltage %dc %&GO.

The !H value of the secondar/ voltage of the transfor&er is

%r&s %&G

:& O:dc

Recti$ier wit# $ilter

5iven %dcand :dcwith a suitable si?e of capacitor in the circuit, the output D.'.level co&es to %& !ipple factor of 86! with capacitor filter is given b/

!.9 %acG%dc

Procedure

1. The circuit connections are &ade for the designed vales.. The suppl/ voltage is switched N.$. The D.' voltage and current are noted down.

Result:

Practical value of ripple factor (without filter) JJJJJJJJJJJJJ

Practical value of ripple factor (with filter) JJJJJJJJJJJJJ

8ence the 96! with and without filter is constructed for the design

specifications.

4+


46/106

Circuit Diagram:

9igure -1

)#evenins e&uivalent circuit:

9igure -

4;


47/106


48/106

)#eoretical Calculation $or )#evenins )#eorem:

)o calculate t#e )#evenins load current:

:

9igure -4

The current :1, :and :$are the three loop currents in figure-4 . The load current :is

sa&e as the current in loop-$.

i.e ::$

!efer figure-4 ./ appl/ing loop current &ethod ,we get the following Hatri3

SS

4.$" - (-$.$")

4@


49/106

U

4.$ V17.A-4.@4W U$.$ V-10.+;-0W U0

(4.$ 1$.0@ )- ($.$ V-10.+;W

+;.44 - $4.@4@ 10"285

S$S

(4.$ -(-$.$ )

U0

4.$ V@4 -$$ WU$.$ (-4A.+ -0)U0(7.; -0)

(4.$ +1 U($.$ 4A.+ U(0 7.; )

1A.$ -1;$.$+ U14+.

1/0"04

:$ (S$S G SS ) ((01.1+ ) G ( 1.$A; )) A.4 8"3 m%

)o calculate t#e )#evenins voltage ,t#: :

4A


50/106

9igure -+

/ loop anal/sis (&atri3 &ethod) calculate the two currents fro& loop-1 and loop- as

:1and :respectivel/.

!efer figure-+ ./ appl/ing loop current &ethod, we get the following Hatri3

SS 4.0@ - 10.@A 1$.1A

S1S 11 -4A.+ ;.+

SS -;4.+ U;; 1.+

:( SS G S1S) (1.+ G 1$.1A ) 00"3m%

%th (1+U : 3 . )

(1+U ( )3(. )

(1+U0.+1)

04"140 ,olts

)o calculate t#e )#evenins resistance Rt#:

+0


51/106


52/106


53/106

9igure -11

)o measure t#e ,:

9igure -1)o measure t#e ,t# :

+$


54/106

9igure -1$

Procedure:

5eneral 'ircuit find load current (:) and load %oltage= (%)(1) 'onnect the co&ponents as shown in the circuit diagra&.() Heasure the voltage across the load using a volt&eter or &ulti&eter after

witching on the power suppl/. et it be %.($) Heasure the current across the load :b/ connecting the co&ponents as

shown in the circuit diagra&.

To find Thevenins %oltage= (%T8)

(1) 'onnect the co&ponents as shown in the circuit diagra&.

() !e&ove the load resistance and &easure the open circuited voltage %T8

across the output ter&inal.

To find Thevenins !esistance= (!T8)


() !e&ove the voltage source and replace it with an internal resistance as

shown.

(4) Msing &ulti&eter in resistance &ode, &easure the resistance across the

output ter&inal.Thevenins Buivalent 'ircuit=

(1) 'onnect the power suppl/ of %T8and resistance of !T8in series as shown in

the circuit diagra&.() 'onnect the load resistance !and &easure % across the load resistance

using a volt&eter after switch on the power suppl/.($) 'onnect the power suppl/ of %T8and resistance of !T8in series with load

resistor as shown in the circuit diagra& and &easure the load current :.

+4


55/106

)o measure t#e )#evenins resistance Rt#:

9igure -14

)o measure t#e load current ':

9igure -1+

)o measure t#e ,:

++


56/106

9igure -1;

)abulation 0:

E0

volts.

E1

volts.

,volts.,)I

volts.

R)I

o#ms.

,

volts.

Theoretical

value0 1+ A.40$ 1+.+1 ;1.A1 A.40$

Practical

value

)abulation 1:

E0 volts. E1 volts. ' m%. ' m%.

Theoretical value 0 1+ A.40$ A.40$Practical value

Result:Thus the Thevenins Theore& is verified theoreticall/ and practicall/.

,iva ,oce (uestion:

1. State the Thevenins theorem.

2. tate the Nortons theore&.3. Give the formulae for converting the connections from star to

delta & delta to star.

4. Give an examle to transform voltage source to current source.!. Give an examle to transform current source to voltage source

+;


57/106

Circuit Diagram:

9igure -1

Nortons e&uivalent circuit:

+7


58/106

9igure -

+@


59/106

E!t" No: Date

b. ,eri$ication o$ Nortons )#eorem

%im:

To verif/ Nortons Theore& both anal/ticall/ and e3peri&entall/.%!!aratus Re&uired:

S"

No

E&ui!ments O

Com!onentsRange ; s!eci$ication (uantity

0 RPS /-2/. , 1

1 %mmeter /-0/. m%Q /-2/. m% Eac# one

2 ,oltmeter /-1/. , 0

3 Resistor 0H Q 1"1H Q0/H Q3"6H Q 1H Eac# one

4 Bread Board ------------------ 0

5 Connecting wires ------------------ %s re&uired

)#eory:

)#eorem Statement

Nortons theore& states that Qan/ two ter&inal linear networ2 having a nu&ber

of voltage, current sources and resistances can be replaced b/ an euivalent circuit

consisting of a single current source in parallel with a resistanceR. The value of the

current source is the short circuit current between the two ter&inals of the networ2, and

resistance is the euivalent resistance &easured between the ter&inals of the networ2

with all the energ/ sources replaced b/ their internal resistances.

=riginal NetworA=

9igure -$

+A


60/106

)#eoretical Calculation $or Nortons )#eorem:

)o calculate t#e 'se:

9igure -4

/ loop anal/sis (&atri3 &ethod) calculate the three currents fro& loop-1 and loop-

and loop -$ as :1, :and :$respectivel/.

SS

(4.$ -(-$.$ )

U03 )

(4.$ V1.$-4.@4W U $.$ V-7.;-0W U 0)

((4.$ )(7.4@ ) C ($.$ 7.; ))

SS ($.1;4 - $.A+@ 7"1/5

;0


61/106

S$S

4.$ - (-$.$ )

U0

4.$ V@4 -$$ W U $.$ (-4A.+ - 0) U 0(7.; -0)

(4.$ +1 ) U ( $.$ 4A.+ ) U (0 3 7.; )

(1A.$ - 1;$.$+ U 14+. )

01.1+

:se:$ S$S GSS (01.1+ G @.0; ) 0.04+ *13"4m%

)o calculate t#e )#evenins resistance Rt#:

9igure -+

R is t#e !arallel combination o$ 0A #and 2"2A # resistors"

9igure -;

R( )G($.$ U1 ) 7;7#

;1


62/106

Ry is t#e serise combination o$ R and 0// # resistors"

9igure -7

Ry (7;7#U100#) @;7#

Rt# is t#e !arallel combination o$ Ry and 1"1A # resistors"

Rt#(@;7#GG.310$)((@;7# 3.310$) G (@;7# U.310$)) 1A07400 G

$0;7

9 510"80K

)o calculate t#e ':

9igure -@

*fter calculating :se I !th, : can be calculated b/ appl/ing current division

techniue.

::se3 (!th G (!thU!) ) 9 0.04+ 3 (;1.A1 G (;1.A1U1000)) A.$A4310-$*

8"283 m%9 8"3 m%

;


63/106

9igure -A:can also be calculated fro& the above circuit i.e.figure-A b/ converting the current

source in parallel with resistance !th as euivalent voltage source in series with !th.

%e :se 3 !th 0.04+ 3 ;1.A1# 04"125 volts

: %e G (!thU!) 1+.$;G(;1.A1U1000)A.$A4 310 -$*8"283 m%9 8"3 m%

;$


64/106

Procedure :

5eneral 'ircuit find load current= (:)


() Heasure the current through the load using an a&&eter or &ulti&eter after

switch on the power suppl/. et it be :.

To find Nortons 'urrent= (:se)


() !e&ove the load resistance and short circuit the output ter&inal. Then

&easure the current through the short circuited ter&inals.

To find Nortons !esistance= (!th)


() !e&ove the voltage source and replace it with an internal resistance as

shown.

(4) Msing &ulti&eter in resistance &ode, &easure the resistance across the

output ter&inal.

Nortons euivalent 'ircuit=

(1) Draw the short circuit current source :sein parallel with !thas shown in the

circuit diagra&.() Draw the euivalent circuit b/ replacing the current source :se in parallel

with !thb/ a voltage source such that %e (:se3 !th)volts.($) Then connect the circuit as shown in figure A and &easure the load current

: through the load resistor !. This &ust be eual to :.

;4


65/106


66/106

9igure -1

9igure -1$

)abulation:

E0

volts.

E1

volts.

'

m%.

'se

m%.Rt#.

,e&9 'se"

Rt#volts.

'

m%.Theoretical

value1/ 04 8"3 8"3 510"80 04"125 8"3

Practical

value

Result:

Thus Nortons Theore& is verified theoreticall/ and practicall/.

Circuit Diagram:

;;


67/106

9igure -1

;7


68/106


69/106


70/106

Hirc##o$$s voltage law H,.:

"% states that Qthe algebraic su& of all the voltages around an/ closed loop in

a circuit euals ?eroR.

i.e., u& of voltage drops u& of voltage rises

:n a closed circuit Z e&f U Z :! 0.

)o Determine t#e sign o$ E*F Source

)o determine t#e sign o$ voltage across t#e Resistor"

:f the loop direction I the current direction are the sa&e then the voltage across

the i&pedance (i.e.,) the voltage drop is ta2en as negative. :f the loop direction I the

current direction are opposite to each other then the voltage across the i&pedance

(i.e.,) the voltage drop is ta2en as positive.

)#eoretical Calculation:

!efer figure-$ ./ appl/ing loop current &ethod ,we get the following Hatri3

:3, :/, :?are the currents of the loops1, and $ respectivel/ as shown in the figure.

:1, :, :$are the branch currents given in circuit

:1:E - :[

::/

:$:?

The other branch currents are :, :4 and :+as &ar2ed in figure.

70


71/106

SS (;.A U (4.7

U ( . )

(;.A V10.44 U (4.7 V @4.04 W U ( . ) @$.74

(@$1.0$; $A4.A@@ 1@4.@ )

9 140"71 .

3

S3S (10) (4.7

U ( . )

10 10.44 U 4.7 V1A@ W -. V-1+0 W

104.4 U A$0.; U$$0

9 1354 .

/

S/S - (10

U

71


72/106

S/S V

S/S (1$;;. )U(@40.04 (7.; )

y 91023"3

?

S?S -( )

U10

S?S V1+0 WU4.7 V$$ WU10V@$.74 W

S?S 10$+ U 1$$.1 U @$7.44

9 1/16"4

:ES3S G S S (4;+ ) G (+1.@ ) *A.7@ &*

:/S/S GS S (1$4 ) G (+1.@ ) *@.474 &*

:?S?S GS S (07.+ ) G (+1.@ ) *@.0+1 &*

:1 :E - :/ ( - ) 1.$1 310-$* 1.$1&*

: :/ *@.474 &*

:$ :? *@.0+1&*

:4:3-:? ( - ) 1.7$310-$* 1.7$ &*

:+:/-:? ( - ) 0.4$310-$* 0.4$ &*

9or 2irchoffs voltage laws, the voltage across each branch is

,0 (voltage across resistor . 2oh&) :43 . 310$(1.7$ 310-$*)( . 310$) $.@ %

,1 (voltage across resistor 102oh&) :+3 10 310$(0.4$310-$*)( 10 310$) 4.$ %

,2 (voltage across resistor 4.72oh&) :13 4.7 310$(1.$1310$ )( 4.7 310$) ;.1+ %

,3 (voltage across resistor 12oh&) :$3 1 310$( *)( 1 310$) @.0+1 %

,4 (voltage across resistor .2oh&) :3 310$( *)( 310$) 1;.A4%

7


73/106

9igure -4

9igure -+)abulation branc# current:

' m%. '0m%. '1m%. '2 m%. '3m%. '4m%.

)#eoreticalvalue

A.7@1 1.$1 @.474 @.0+1 1.7$ 0.4$

Practical value

7$


74/106


75/106

)abulation $or node current in HC:

S"No Name o$ t#enode

)#eoretical value Practical value

1Node P

A.7@1&* (@.0+1U1.7$ )&*::$U:4

Node L

1.7$&* (0.4$U 1.$1)&*:4:+U:1

$Node !

@.474&* (@.0+1U0.4$)&*::$U:+

9igure -;

)abulation $or branc# voltage:

,0volt.

,1volt.

,2volt.

,3volt.

,4volt.

)#eoreticalvalue

$.@ 4.$ ;.1+7 @.0+1 1;.A4@

Practical value

7+


76/106

)abulation $or loo! voltage:

S"No" Name o$ t#eloo!

)#eoretical value Practical value

01oop 1

10v ($.@ U;.1+7)v

B1%1U%$

0oop

1+U;.1+7-4.$-1;.A4@)v 0

BU%$-%-%+0

0$

oop $

@.0+1v ($.@U4.$)v%4%1U%

,iva voce (uestion

1. tate h&s law.. tate "irchhoffs current law I "irchhoffs voltage law.$. 6hat is &ean b/ Node I Hesh\4. 6rite the current I %oltage division rule.

+. Hesh current &ethod is based on "' and node voltage &ethod is based on "%-True or 9alse. \

Results:

Thus (i) "irchhoffs 'urrent aw I (ii) "irchhoffs %oltage aw are verified.

Circuit diagram:

7;

S"No"Name o$ t#e

Current)#eoretical value Practical value

01 :1


77/106

77


78/106

E!t" No": Date:

,eri$ication o$ Su!er Position )#eorem

%im =

To verif/ super position theore& practicall/ I theoreticall/ for the given D'

circuit.

%!!aratus Re&uired:

.No. 'o&ponents !ange Luantit/

01. !egulated Power suppl/(!P) (0-$0)%

0. *&&eter (0-$0)&* 1

0$. Hulti&eter --- 1

04. !esistors +;0# $0+. read board --- 1

0;. 'onnecting wires*s per

!euire&ent)#eory:

Su!er !osition )#eorem:

:n a networ2 of linear resistances, containing &ore than one source, the

resultant current flowing at an/ one point is the algebraic su& of currents that would

flow at that point, if each source is considered separatel/, and all the other sources are

replaced b/ their euivalent internal resistance .

This last step is carried out b/ short circuiting all sources of constant voltage I open-

circuiting all sources of constant current.

Procedure:

1. Ha2e connections as per the (fig b) circuit diagra&.

. %ar/ the !Pand set an input voltage of 10 % .

$. Note down the a&&eter reading :1in tabular colu&n 1.4. Ha2e connections as per the (fig c) circuit diagra&.

+. %ar/ the !P1and set an input voltage of 10 %.

;. Note down the a&&eter reading :in tabular colu&n .

7. Ha2e connections as per the (fig a) circuit diagra&.

@. 9ind the total load current ::1U:

A. %erif/ the sa&e using theoretical calculation

)#eoretical Calculation $or Su!er !osition t#eorem:

7@


79/106

Circuit diagram:

Ste! 0:hort circuit %.*ppl/ %10%

+ U1+ :1 0

-1+ 0 : 0

:1 1.4+ *] : 1.0A *] :T1 0.$; *

7A

!P (0-$0%) %1

-

U

+# 10#

1+#

:1:


80/106

Ste! 1:hort circuit %1.*ppl/ %1+%

+ U1+ :1 0

-1+ U0 : -1+

:1 -0.@1 * ] : -1.$;$ * ] :T 0.+4 *

Ste! 2:%1 I %are active. *ppl/ %10% I %1+%

+ U1+ :1 0

-1+ U+ : -1+

:1 0.;$ *] : -0.7 * ] :T 0.A0A *

Thus :T :T1U :T . uper Position Theore& is proved.

@0

::1

::1


81/106

Circuit Diagram $or Su!er Position )#eorem L Practical %nalysis:

Ste! 0:oth voltage sources are active.

Fig a.

Ste! 1= !P alone is active. :^^^^^

Fig b.

Ste! 2: !P1 alone is active. :1^^^^^

Fig c.

@1

!P1(10%) !P

(10%)

U U

U

-

- -

U

-U

-

10 # +#

1+#

* (0-10&*) H'

10 # +#

1+#

(0-10&*) H'

!P(10%)

*

(0-10&*)

!P1(10%)

10 # +#

1+#

* U

-

U

-


82/106

)abulation 0: )o measure ')0 O '0 (9or fig.b)

)abulation 1

)o measure ')1 O '1$or fig.c)

)abulation 2

)o measure bot# ')O '(9or fig. a)

,iva ,oce (uestion:

1. tate uper position theore&.2. "an the suer osition theorem is alied to solve electric circuits

#ith diodes resent in the circuit$ %h$3. Give an examle to transform current source to voltage source.4. %rite do#n the formula to convert a delta connected circuit to star

connected circuit.!. State the dualit theorem.

Result: Thus superposition theore& is verified practicall/ Itheoreticall/.

@

%oltage(volts)

Theoretical'urrent

:T(*)

Practical'urrent :

(*)

%oltage(volts)

Theoretical

'urrent

:T1(*)

Practical

'urrent :1

(*)

!P1%oltage

(%)

!P%oltage

(%)

Theoretical'urrent :T

(*)

Practical'urrent :

(*)

: :1U:(*)

:T :T1U:T(*)


83/106

Circuit Diagram *aimum Power )rans$er )#eorem:

Circuit t o $ind ,:

*odel +ra!#:

@$

1"#

1"# D! (! )!P (0-$0%)

%

1"#

1"#

D!

!P (0-$0%) % (0-$0%)H'

U

-

U

-

oad resistance, ! in #

P&a3

! !T8

Power,P

(&

6)


84/106


85/106

*odel Calculation:

Circuit Diagram:

Ste! 0: To find %T8

pen the circuit the load ter&inal !.

@+

Sl"No"

oad ResistanceQRH.

=ut!ut ,oltageQ ,/volts.

PowerQ Pm>.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

01

%s 1+%

12#

12# D!!

!112#


86/106

/ voltage distribution rule=

!BL 0.+# I %T8 %!1G (!1U!) 1+%

Ste! 1= To find !T8=

pen circuit the load ter&inal !.

pen circuit the current source and short circuit the voltage source.

!T8 !1! G (!1 U ! ) 0.+#

@;

!12#

%s 1+% %T8

!112#!12#

!T8


87/106

Ste! 2: Thevenins euivalent circuit for &a3i&u& power delivered.

: %T8 G (!U!BL) 1+ G (0.+ U 0.+) 1+ *

Ha3 power delivered at ! :! 11.+ 6

,iva ,oce (uestions:

1' State the (aximum o#er transfer theorem.

2' State the condition for maximum o#er transferred from source toload.

3' %hat is mean ) (esh or *oo$4' State the dualit theorem.!' Give the formulae for converting the connections from star to delta &

delta to star.

@7

%s 1+%

!T80.+#

! !T8:


88/106

Result:

Thus &a3i&u& power transfer theore& is verified practicall/ and theoreticall/.

@@


89/106

Reci!rocity )#eorem L Practical %nalysis

Circuit Diagram:

Ste! 0: To &easure the current at branch $-4.

Ste! 1: To &easure the current at branch 1-.

@A

!P (0-$0%)%$0%

1# #

;#

4#

!P (0-$0%)%$0%

1# #

4#

;#

(0-10&*)H'

U

-

U

-

U

-

:1

1

$

4

1

$

4

- !P (0-$0%)%$0%

(0-10&*) H'

U

-

U

1# #

;#

4#

:

1

4

$


90/106

E!t" No": Date:

b. ,eri$ication o$ Reci!rocity )#eorem

%im:

To verif/ the reciprocit/ theore& for the given circuit, practicall/ andtheoreticall/.

%!!aratus Re&uired:

S"No" Name o$ t#e a!!aratus Range;Rating (uantity

01. *&&eter (0-10)&* 1

0. !P (Power uppl/) (0-$0)% 1

0$. !esistor 1#, # ,4#,;# 1 each

04. 'onnecting wires -*s per the

reuire&ent

)#eory:

!eciprocit/ Theore& states that Qin any passive linear bilateral network,if the

single voltage source %in branch 3 produces the current response : [in branch /, then

the re&oval of the voltage source fro& branch 3 and its insertion in branch / willproduce the current :[ in branch 3.R

:n si&ple ter&s, Qinterchange of an ideal voltage source and an ideal a&&eter

in any passive, linear, bilateral circuitwill not change the a&&eter readingR.

Note= The reciprocit/ theore& is thus applicable onl/ to single source networ2. :t is,

therefore, not a theore& e&plo/ed in the anal/sis of &ulti-source networ2. :n other

words, the location of the voltage source and the resulting current &a/ be interchanged

without a change in current.

Procedure:

1. Ha2e connection as per the circuit diagra&.

. 'alculate the values of :1, b/ connecting the a&&eter at branch $-4 and

tabulate.

$. Now connect the power suppl/ at branch $-4 and &easure the current in the

a&&eter connected at branch 1-.tabulate the value as :.

4. 'o&pare the theoretical value and tabulated value of current to be the sa&e

to verif/ the reciprocit/ theore&.

A0


91/106

)abulation:

uppl/voltage,%

(volts)

'urrent atbranch $-4,:1

(&*)

'urrent atbranch 1-, :

(&*)

*odel Calculation:

Ste! 0: To &easure current :1at branch $-4

1@ ; : $09

-; 1 :1 0

:1 0.71 *

A1

1# #

;#

4#!P (0-$0%)%$0 v

:1:

1

$

4


92/106

Ste! 1:To &easure current :at branch 1-

07 5 : 0

-5 01 :1 9 -$0

: 0.71*

: :1 . Thus, !eciprocit/ Theore& is verified.

Result:

Thus the reciprocit/ theore& is verified theoreticall/ and practicall/.

A

1# #

;#

4#

!P (0-$0%)%$0 v

1

$

4


93/106

Circuit Diagram:

Parallel Resonance Circuit:

Series Resonance Circuit:

A$


94/106

E!t" No": Date:

Fre&uency Res!onse o$ Series and Parallel Resonance Circuit

%im:

To obtain the resonance freuenc/ and bandwidth of series and parallel

resonance circuits.

%!!aratus Re&uired:

S"No"Name o$ t#e

a!!aratusRange (uantity

01 !P Dual (0-$0) % 10 *&&eter *' (0-$0 ) &* 1

0$9unction

5enerator (0-$)H8?

1

04 !esistors 10#, +# 1

0+ 'apacitor 19 1

0; D: - 1

07 readboard - 1

0@'onnecting

wires

- *s per

!euire&ent

)#eory:

%t resonance E E'and i&pedance > !. 6here ! is the resistance of the

coil. The !andE of the coil deter&ines the ualit/ of the circuit which is given b/

L E G !

Point f1and fare located at 70.7 percent of the &a3i&u& current for the series

circuit. The/ are called as half power point and the freuenc/ difference between f1

(lower cut off freuenc/) and f(upper cut off freuenc/) is called the band width.

A4


95/106

*odel +ra!#:

eries !esonance=

Parallel !esonance=

A+

:&a3 G

:&a3

:&in

:&in .

freuenc/

9reuenc/

current

'urrent


96/106

The for&ula for calculating the band width is given b/

6 fC f1 .

and width is related to the ualit/ factor(L). :ts given b/

6 fr G L

!esonance freuenc/ of the series resonant circuit is calculated using the for&ula

fr 1 G O (').

Procedure:

1. 'onnections are given as per the circuit diagra&.

. The resonance freuenc/ is obtained b/ 2eeping the value of ,',! constant

$. The resonance freuenc/ is obtained using the for&ula fr 1 G O (').

4. %ar/ing the value of freuenc/ and note down the corresponding current flowin the circuit.

+. 5raph is plotted between freuenc/ (3 a3is) and current (/ a3is).

;. a&e procedure is to be followed for both series and parallel circuits.

A;


97/106

)abulation:

Series Resonance: Parallel Resonance:

A7

Sl" NoFre&uency

I.Current m%.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

01

02

Sl" NoFre&uency

I.Current m%.

/0

/1

/2

/3

/4

/5

/6

/7

/8

0/

00

01

02


98/106

Hodel 'alculation=

Parallel Resonance:

R9 0/Q 90 I C9 0TF

%dmittance o$ t#e !arallel resonance circuit is given by

1( )Y G jB G j C

L

= + = + ( where 5 is conductance and is susceptance)

%t resonance B9/

1CL

0

1

rf

LC=

1

r

fLC

= 1+A8?

1

r

QRC

= 100

andwidth rQ

10radGsec

( )

11

1 1 1

4

RCf

RC LC

= + + 7A.;8?

( )

1

1 1 1

4 RC

fRC LC

= + + 1;0.+8?

andwidth 1f f @0.A 8?

A@


99/106

Series Resonance:

R9 4Q 93/ m IQ C9 0TF

'm!edance o$ t#e series resonance circuit is given by

%t resonance:

LX L= =1

CXC

=

Therefore L 1

C(where _ Of)

Q factor 1 L

R C 40

andwidth

R

L 1A.@A8?

1

rf

LC= 7A;8?

14

r

Rf f

L= 7@;8?

4

r

Rf f

L= + @0; 8?

AA

( )L c

Z R j X X= +

1

r

fLC

=


100/106

RES


101/106

C'RC


102/106

E"No L

)R%NS'EN)%N%S'S=FR%NDRCC'RC


103/106


104/106

:n 9ig. when switch is closed, the response reaches the stead/ state

value after so&e ti&e interval. Thus the transient period is defined as the ti&e ta2en for the

current to reach the final value.

DCRESP=NSE=F%NR-C C'RC


105/106

Differentiate the above euation,

O =R

d

i

+

i -----------------------(@)d

t c

Divide the euation @ b/ !d

i + 1 i =0----------------------- (A)dt R

The above euation is a linear differential function with onl/ co&ple&entar/

solution. The solution for this euation is

i =Cet

G

Rc

---------------------- (10)6hen switch is closed at t0, the capacitor never allow sudden changes in

voltage, it will act as a short circuit. *t t0,i%G!. substitute this current to euation 4.

'%G!

The current euation beco&es,

i =V

et

GRC------------------------- (11)

R

:n9ig. 4 *fter 4T' the curve reaches the AA percent of it final value. :n that

solution euation +, the uantit/ 1G!' is ti&e constant and is denoted b/ Y

10+


106/106

PR=CED

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Ec 6211 Final From Ece