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TOPIC REVIEW FOR FINAL EXAM ECE342 SPRING 2007 Dear Students, I have prepared this concept review to aid in studying for your final exam. I hope it proves useful. I did not include concepts from HW1- 3 because unfortunately I did not have time. But these homeworks were relatively simple, and I believe the final exam will be weighted more heavily on the recent material, so you should be okay. Be sure to skim over HW2 and 3, though. This tutorial becomes more detailed the further you read. I tried my best to include all the concepts I thought were important in the last couple of chapters we covered in the course. I might have missed some concepts, so please check your notes. To study for this exam, I’d recommend working the practice exam, reworking the previous two exams, and reading this review. After you have done those things, then skim over your notes incase you or I missed some important topics. If you have free time after doing these things, skim over all your homework solutions. I wish you the best of luck for this exam. I hope that you found the class useful, or at least interesting. Best of luck with your future endeavors, Sincerely, Jonathan Rose. --------------------------------------------------------------------- ----------------------------------------- EXAM TOPICS FROM HW4, CH8 FEEDBACK AMPLIFIERS, LOOP GAIN, AND STABILITY BASICS Suggested HW4 Study Problems Problem 2: This is that long problem, where you calculate the feedback and basic amplifier blocks, the input and output impedance. You have a similar problem in the practice exam. Make sure you are familiar with this analysis!

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A . 1 + A Amount of feedback or desensitivity factor: 1+A. Closed Loop Gain: A f =

Stability Instability occurs when Af = . This occurs when loop gain L= -1 =1180. Phase margin and gain margin measure how close the feedback amplifier is to instability. Always, always, ALWAYS measure phase margin and gain margin by bode-plotting the loop gain. Phase margin is always measured at the unity gain frequency, t. Gain margin is always measured at the frequency where the phase is 180. Thus, A(s=j) =180. Study Fig. 8.36, p846 for measuring phase margin and gain margin. An amplifier is stable for pm>0 and gm>0. (These will both be true together.) Suggested HW5 Study Problems P2: Rework. P3: Rework. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW6, CH9 CMOS OP-AMPS Important Concepts Be sure you can analyze the Two-Stage CMOS Op-Amp circuit in Sec. 9.1.1. Try reworking Exam II problem 3. The two-stage CMOS op-amp (p872) and the folded cascade CMOS amplifier (sec. 9.2.1 p884) require the special trick of identifying a current mirror. Otherwise, to analyze any CMOS amplifier, just plug in the CMOS small signal model. Suggested HW6 Study Problems Rework problem 2 or problem 5. Rework Exam II problem 3. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW7, CH9 741 OP-AMP BIASING AND SMALL SIGNAL ANALYSIS 741 Op-Amp Conceptual Questions

Look at the 741 op-amp circuit schematic p894. Identify all stages of this amplifier.

What are the functions of each stage? o Stage 1: Differential amplifier. o Stage 2: High gain amplifier and frequency compensation (Cc creates the low frequency pole). o Stage 3: Class AB amplifier (has a voltage gain of 1, but can provide relatively high current to the load). What is the role of each transistor? o Bias: Q8,9,10,11,12,13,18,19. o Stage 1: Differential input: Q1,2,3,4 (Q3 and Q4 increase the input resistance). Current mirror: Q5,6. Q7 helps preserve stage 1 symmetry; it is balancing the loading effect of Q16. o Stage 2: Q16: increases input resistance to stage 2. Q16 is wired emitter follower, thus has a gain of 1. Q17: wired common emitter, thus has a high signal gain. o Stage 3: Q14,20: class AB amplifier. o Q23 brings the signal from stage 2 to stage 3. It has a voltage gain of 1, but provides a sink to the stage 3 bias current. o Short circuit protection: Q15,21,22,24. Can you calculate the reference bias current IREF? Looking at the left side of the 741 circuit, Q12 connects to the positive voltage Vcc=+15. Q11 connects to the negative voltage supply Vee=-15. Thus, across R5 we have (Vcc-Vee-0.7-0.7)=28.6 volts. (The 0.7 is the VBE of Q12 and Q11). Thus, IREF = 0.7333 mA.

Be sure you can calculate the input resistance and gain of the input stage as shown in Section 9.5.1 p905-7 (and also in Example 9.3 p908). Be sure you can calculate the gain of the second stage. See Sec. 9.5.2., p910-912.

Suggested HW7 Study Problems P1: Rework. P3: Rework if time allows, else reread your solution. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW8, CHAPTER 9 OP-AMP DYNAMIC PERFORMANCE AND D/A CONVERTERS Op-Amp Dynamic Performance 1. Be able to calculate Slew Rate of any given circuit. (See Exam II, P3.) For a circuit with a capacitor, I = C*dv/dt, where maximum dv/dt = slew rate. D-to-A Converters Digital to analog converters employ binary switches to adjust an output voltage. Most D/A converters sum up a current signal, and then convert this back to a voltage using an op-amp. Figure below (from p. 925) Notice how the resistors are set up so that each switch carries a binary-weighted current. Notice that the op-amp input forms a virtual ground so that each switch carries current I = Vref / Resistance.

Figure below (p926) The resistors in this figure accomplish the exact same function as in the figure above, except this ladder network requires only two resistor values: R and 2R (thus is easier to fabricate on a chip). This was the same circuit as on Exam II. The resistors are set up so that the node voltage halves at each node from left to right, as shown. This is the single most important fact to remember about this type of circuit, b/c remembering this will allow you to use standard Node Voltage analysis and avoid memorizing formulas.

Vref/2

Vref/4

Vref/2N-1

D/A Converter Formulas b b b D = 1 + 2 + ... + n (memorize this one). 1 2 2 2 2n io = ? (No need to memorize. Derive looking at ckt and using Node-Voltage. Notice that the formula will be slightly different for the two circuits shown above.) vo = ? (Derive looking at ckt and using Node-Voltage.) Know how to calculate quantization and converter error (see Exam II). A-to-D Converters 1. The Dual-Slope A/D Converter (p930-31) a. This circuit was not on any homework, so an exam could only ask the most basic questions about this circuit. b. Read how the circuit works, if time allows. Formulas and Fig. 9.44 will be provided if this circuit appears on the exam. 2. Parallel or Flash A/D converter (p932). a. Understand this converter fully. You should be able to draw the converter from memory:

b. Be able to pick the voltage references VR1, VR2 Suggested HW8 Problems to study P4: Rework. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW9 CH12 FILTERS

Filter response can be described by this figure (below). This figure will be provided on the formula sheet. This figure is designed to describe a low-pass filter. A high-pass filter can be described by the same figure, except flipped vertically.

Analyzing an unknown filter: Say youre given an unknown filter circuit:

To analyze, write the transfer function (TF) by solving the circuit T(s) = Vo/Vi. (Recall capacitor impedance Zc = 1/sC.) From this TF, you can find: a. A0 = T(s=0) (Low freq or DC gain) b. A= T(s=) (High frequency gain) c. Pole(s) location: Look at the denominator of T(s). Poles appear as polynomials in the denominator, of the form (s+p) or (s/p +1) (both forms are equivalent). d. t = Unity Gain Frequency. This results in solving |T(s=jt)| = 1. e. Type of filter (high pass, low pass, bandpass, notch, etc). For a single order filter, it will either be a high pass or low pass. Use A0 and A . (E.g. A0 >0, A = 0 Low pass.) For higher order filters, look at the pole/zero locations and sketch the bode amplitude according to Exam II Prob. 5. Match your sketch with the bode plots shown in Fig. 12.16, which will be provided in the formula sheet.

Filters in General Q: What does the order of the filter determine?

A: (See Fig. 12.19). Higher order filters have a more idealized transfer function (see Fig. 12.2 for an idealized TF), but require increasing circuit complexity. Poles are also called filter modes. Given a filter transfer function, you can recognize the filter order by the degree of the denominator. E.g.: A filter with (1+s)(10+s) in the denominator is a 2nd order filter. Zeros at infinity = degree{denominator}-degree{numerator}. If the denominator is not higher order than the numerator, then there are no zeros at infinity. 2 2 Pole quality factor Q=?: Rearrange denominator into a quadratic s + (0 / Q) s + 0 to determine Q. o If Q>0.5, the poles are complex conjugate. Otherwise, they are real. o If Q=1/2 = 0.707, the filter is said to exhibit maximally flat response. This means that, at the pole p, the response is less smooth and forms more of a sharp angle (see p1092). o If Q>1/2, the filter exhibits overshoot near the pole (see fig. 12.16, row b. Notice how the high-pass filter response peaks before leveling off).

Suggested HW9 Study Problems P1: Reread your solution. Rework if time allows. P2: Rework. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW10 CH12 ACTIVE FILTERS Butterworth Filter Know how to place the poles equally spaced around the complex plane circle (see Fig. 12.10). Formulas (12.11)-(12.15) will be provided. Know how to use (12.15) to calculate the filter order required (read paragraph right below (12.15)). Chebyshev Filter Formulas (12.18)-(12.24) will be provided. Butterworth vs. Chebyshev Q: What are the functional differences between a butterworth and Chebyshev of the same order? A: A Chebyshev filter exhibits ripple in the passband, but has a slightly steeper stopband slope (esp. near p). A butterworth exhibits no passband ripple, but has a slightly shallower stopband slope. Biquad. Filters Biquadratic filters are neat because, using three op-amps, they can be designed to realize all standard filter types: High Pass (HP), LP, BP, and Notch. Be able to use Table 12.2 to design a specified filter (table will be provided). If the info you need isnt in Table 12.2, use the filter transfer function Formula 12.68 (will be provided) to design poles and zeros and LF gain and HF gain as needed. Suggested HW10 Study Problems

Filters such as Butterwoth, Chebyshev, and Biquads (HKN and Tow-Thomas) are all designed using given formulas. This is very much a cookbook process. If you feel confident with the formulas, you do not need to rework any HW10 problems. Problem 1: Rework (optional).

-------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW11 CH12 & 13 SWITCHED CAPACITOR FILTERS AND LINEAR OSCILLATORS Switched Capacitors Switched capacitors are an IC Fabrication trick to replace large resistors. Thus, they perform the function of a resistor in a filter using a capacitor and a switches:

Replacing R1 by the switched filter, R1 = TC/C1.

Linear Oscillators

Given an oscillator circuit, how do you find the oscillation freq 0 and the gain criteria? o If the gain block and feedback blocks are easy to identify, A block

block use the Barkhausen criterion: The loop gain should be unity (L=A=10.) Thus

solve for A and according to the work in Sec. 13.2.1, The Wien-Bridge Oscillator. Notice that oscillators require positive feedback, thus the block is identified as the circuit portion feeding into the positive terminal of the op-amp. o If the gain and feedback blocks are not easy to identify,

Solve the circuit. Write a KCL equation at one of the nodes (cap. impedance = 1/sC, inductor impedance = sL). Solve this circuit according to the method in 13.3.1, LCTuned Oscillators. Once writing the KCL equation, you should be able to factor out the node voltage at this node you chose (as shown in eq. 13.18). Setting the rest of the expression equal to zero, you can then solve imaginary part = 0 to get the oscillation frequency 0 (as shown in eq. 13.20) and real part = 0 to get the gain criteria (as shown in eq. 13.21 and 13.22). Suggested HW11 Study Problems P2: Rework. The circuit was solved in section 13.2.1, but you should be able to do this on your own. Very important: P13.21 or follow the bookwork of section 13.3.1 to solve the given oscillator circuit. See HW solutions if you had trouble with P13.21. P4: Rework if you got part of this problem wrong on the HW, otherwise reread your solution. Equations will be provided on formula sheet. -------------------------------------------------------------------------------------------------------------EXAM TOPICS FROM HW12 CH13&14 NONLINEAR OSCILLATORS AND POWER AMPLIFIERS The field of nonlinear oscillators is broad: basically any oscillator that utilizes components operating in nonlinear regions. In this class, the only class of nonlinear oscillators we studied was the astable multivibrator. One building block to an astable multivibrators is the bistable circuit, which forms a a hysteresis loop in the input-output characteristic. E.g.: A bistable circuit:

In this circuit, the op-amp is saturated, and thus forms a comparator. L , if v+ > v vO = + L , if v+ < v Notice how the input voltage vI is compared to a reference voltage v+. The reference voltage v+ is not constant, but depends on the output vO (by the resistor voltage divider ratio). Since vO can take on two voltages (L+ or L-), there are two threshold voltages to which vI is compared to. If the output is high (vO = L+), then VTH applies, if the output is low (vO = L-), then VTL applies. Thus, input-output characteristic forms a hysteresis loop (above, right).

The other building block to an astable multivibrator is some type of RC timer circuit.

All astable multivibrators have two building blocks: 1. decision logic which forms a hysteresis loop, and 2. some type of timer involving a time constant (e.g. an op-amp integrator). Comparison: Linear Oscillator vs. Astable Multivibrator Criteria Linear Osc. Astable Multiv. Output Sinusoidal only Nonsinusoidal such as triangular, square, sawtooth, Waveform growing/decaying exponential, etc. Building 1. Forward gain linear 1. Decision logic which outputs two discrete Blocks amplifier. states (eg. a saturated op-amp outputs L+ and 2. Feedback consisting of L-) and forms a hysteresis loop. two or more storage 2. Timer: Storage element with a time constant elements (inductors or (eg. RC op-amp integrator).

Identifying Features (also see building blocks) Criteria for Oscillation. Circuit analysis

capacitors). Two storage elements.

Hysteresis loop: an op-amp with positive feedback (feedback connected to the positive input terminal), thus will saturate.

Loop gain = 1 (Barkhausen criterion) All op-amps operate in the linear region, thus input terminals are at the same voltage.

Uses (for interest, not on exam)

Logic outputs two states, neither of which are stable. The op-amp used for hysteresis is saturated, thus input terminals are generally not at the same voltage, except when the op-amp is switching high to low or low to high. Other op-amps in the circuit, such as the one used for a timer or integrator, operate in the linear region. Sinusoid audio tone generators Electronic testing. Generate clock signal for digital for modems, touch-tone circuits & computers. phones, radio transmitters for generating RF, determining quality of audio components.

Identify: Linear Oscillator or Astable Multivibrator? A useful skill is being able to identify whether an oscillator is linear or an astable multiv. This will help you in the circuit analysis, because you should know whether an op-amp is operating in the linear or saturated regime. See the table above for help in identifying circuits.

Astable multiv: a and c, linear osc.: b and d. c)

d)

Power Amplifiers

Calculating Efficiency Formulas for Class B amplifier power consumption will be provided. You should be familiar with how these formulas are derived. Read Sec. 14.3.3, p1236. If you have trouble seeing how some of the formulas are derived (e.g. Formula 14.13) see the Discussion 12 notes. load (output ) _ power = . Memorize this formula. input _ power P = VI , where V and I are RMS quantities. Recall that RMS voltage is related to peak voltage ( V ) by V = V 2 . You shouldnt graduate ECE without knowing this by heart. Heat Dissipation No formulas will be provided. Its easy. (See HW12 P5). Recall that the limiting parameter for any transistor is the maximum junction temperature. Thus, all maximum power calculations depend on not exceeding Tjmax. Suggested HW12 Problems P2: Rework. P4: Book problem 14.14. Rework. P5: Book prob. 14.30. Rework. --------------------------------------------------------------------------------------------------------------

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