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10.1
EE 109 Unit 10 – MIPS
Instruction Set
10.2
MIPS INSTRUCTION OVERVIEW
10.3
Instruction Set Architecture (ISA)
• Defines the _________________ of the processor and memory
system
• Instruction set is the ____________ the HW can understand and
the SW is composed with
• 2 approaches
– _____ = ___________ instruction set computer
• Large, rich vocabulary
• More work per instruction but slower HW
– _____ = ___________ instruction set computer
• Small, basic, but sufficient vocabulary
• Less work per instruction but faster HW
10.4
MIPS Processor and Bus Interface
• The MIPS processor can execute software instructions that will
cause it to:
– Load (Read) and Store (Write) data to and from memory or I/O
devices
– Perform arithmetic and logic operations (add, sub, and,
etc.)
– Make decisions to move around in the code (loops, ifs, call a
function, etc.)
MIPS Processor
Addr (32-bits)
Data (32-bits)
Control
Memory
instruc
data
0
ALUADD, SUB, AND, OR
op.
in1
in2
out
PC
$0-$31(32-bits each)
(32-bits ALU)
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10.5
Which Instructions
• In this class we'll focus on assembly to do the following
tasks (shown with the corresponding MIPS assembly
mnemonics)
– Load variables (data) from memory (or I/O) [LW,LH,LB]
– Perform arithmetic, logical, and shift instructions in the CPU
[ADD,SUB,AND,OR,SLL,SRL,SRA]
– Store variables (data) back to memory after computation is
complete [SW, SH, SB]
– Compare data [SLT]
– "Branch" to other code (to implement if and loops)
[BEQ,BNE,J]
– Call subroutines/functions [JAL, JR]
10.6
MIPS Instruction Set
• __________-style
• ______________ internal / __________ external data size–
Registers and ALU are 32-bits wide
– Memory bus is logically 32-bits wide (though may be physically
wider)
• Registers– ______ General Purpose Registers (GPR’s)
• For integer and address values
• A few are used for specific tasks/values
• Fixed size instructions – All instructions encoded as a single
______-bit word
– Three operand instruction format (dest, src1, src2)
– Load/store architecture (all data operands must be in
registers and thus loaded from and stored to memory explicitly)
10.7
MIPS GPR’sAssembler Name Reg. Number Description
$zero $0 Constant 0 value
$at $1 Assembler temporary
$v0-$v1 $2-$3 Procedure return values or expression
evaluation
$a0-$a3 $4-$7 Arguments/parameters
$t0-$t7 $8-$15 Temporaries
$s0-$s7 $16-$23 Saved Temporaries
$t8-$t9 $24-$25 Temporaries
$k0-$k1 $26-$27 Reserved for OS kernel
$gp $28 Global Pointer (Global and static
variables/data)
$sp $29 Stack Pointer
$fp $30 Frame Pointer
$ra $31 Return address for current procedure
Avoid using the yellow (highlighted) registers for anything
other than its stated use
10.8
MIPS Programmer-Visible Registers
• General Purpose Registers (GPR’s)– Hold data operands or
addresses (pointers) to data stored in memory
• Special Purpose Registers– ___: ____________ ___(32-bits)
• Holds the address of the next instruction to be fetched from
memory & executed
– HI: Hi-Half Reg. (32-bits)• For MUL, holds 32 MSB’s of
result. For DIV, holds 32-bit remainder
– LO: Lo-Half Reg. (32-bits)• For MUL, holds 32 LSB’s of
result. For DIV, holds 32-bit quotient MIPS Core
PC:
$0 - $31
32-bits
GPR’s
Special Purpose Registers
HI:
LO:
Recall multiplying two 32-bit numbers yields a 64-bit result
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10.9
IMPORTANT R-TYPE INSTRUCTIONS
Performing Arithmetic, Logic, and Shift Operations
10.10
R-Type Arithmetic/Logic InstructionsC operator Assembly
Notes
+ ADD $d, $s, $t d=destination, s = src1, t = src2
- SUB $d, $s, $t Order: $s – $t. SUBU for unsigned
* MUL $d, $s, $t If multiply won’t overflow 32-bit result
& AND $d, $s, $t
| OR $d, $s, $t
^ XO$ $d, $s, $t
~( | ) NOR $d, $s, $t Can be used for bitwise-NOT (~)
> (signed) SRA $d, $s, shamtSRAV $d, $s, $t
Shifts $s right by shamt or $t bits replicating sign bit to
maintain sign
>> (unsigned) SRL $d, $s, shamtSRLV $d, $s, $t
Shifts $s left by shamt or $t bits shifting in 0’s
, = SLT $d, $s, $tSLTU $d, $s, $t
Comparison. Order: $s – $t. Sets $d=1 if $s < $t, $d=0
otherwise
* MULT $s, $t MULTU $s, $t
Result in HI/LO. Use mfhi and mfloinstruction to move
results
/ DIV $s, $tDIVU $s, $t
$[s] / $[t]. Remainder in HI, quotient in LO
10.11
R-Type Instructions
C Code MIPS Assembly
F = X + Y – Z;
G = F | Z;
LOAD* $4, X # Get X from mem.
LOAD _____ # Get Y from mem.
LOAD _____ # Get Z from mem.
ADD _______ # Tmp = X+Y
SUB _______ # Tmp = Tmp - Z
STORE _______ # Store to F in memOR _______ # Tmp2 = F | Z
STORE $8, G # Store to G in mem* LOAD/STORE are not actual
instructions. We will learn the actual syntax soon.
• To perform arithmetic or logic operations in many processors
(MIPS included) a copy of the operand MUST be loaded into a
register first
• Consider the following operations– F = X + Y – Z– G = F |
Z
• Complete the assembly codeto perform these operations
– Remember to load/store youroperands to/from registers
MIPS Processor
Addr (32-bits)
Data (32-bits)
Control
Mem
ory
Load00400000
ALUADD, SUB, AND, OR
op.
in1
in2
out
PC
$0-$31(32-bits each)
(32-bits ALU)
Load
…
Store
X (e.g. 12)
Y (e.g. 7)
Z (e.g. 3)
F
G
$4
$5
$6
$7
$8
00400004
10010000
10010004
10.12
R-Type Instructions
• Format
– rs, rt, rd are 5-bit fields for register numbers
– shamt = shift amount and is used for shift instructions
indicating # of places to shift bits
– opcode and func identify actual operation (e.g. ADD, SUB)
• Example:
– ADD $5, $24, $17
opcode rs (src1)
6-bits 5-bits
rt (src2)
5-bits
rd (dest)
5-bits
shamt
5-bits
function
6-bits
000000
opcode rs rt rd
00000
shamt
100000
func
Arith. Inst. $24 $17 $5 unused ADD
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10.13
Logical Operations
• Should already be familiar with (sick of) these! ☺☺☺☺
• Logic operations are usually performed on a pair of bits
AND – Output is true if both inputs are true
OR – Output is true if any input is true
XOR – Output is true if exactly oneinput is true
X1 X2 AND
0 0 0
0 1 0
1 0 0
1 1 1
X1 X2 OR
0 0 0
0 1 1
1 0 1
1 1 1
X1 X2 XOR
0 0 0
0 1 1
1 0 1
1 1 0
X1 NOT
0 1
1 0
NOT – Output is inverse of input
0 OR x = x1 OR x = 1x OR x = x
0 AND x = 01 AND x = xx AND x = x
0 XOR x = x1 XOR x = NOT xx XOR x = 0
10.14
Logical Operations
• Logic operations on numbers means performing the operation on
each pair of bits
Initial Conditions: $1 = 0xF0, $2 = 0x3C
AND $2,$1,$2
R[2] = 0x30
0xF0AND 0x3C
0x30
1111 0000AND 0011 1100
0011 0000
OR $2,$1,$2
R[2] = 0xFC
0xF0OR 0x3C
0xFC
1111 0000OR 0011 1100
1111 1100
XOR $2,$1,$2
R[2] = 0xCC
0xF0XOR 0x3C
0xCC
1111 0000XOR 0011 1100
1100 1100
1
2
3
Tip: Unless you're very good w/ hex, convert to binary then
perform these operations!
10.15
Logical Operations
• Logic operations on numbers means performing the operation on
each pair of bits
Initial Conditions: $1= 0xF0, $2 = 0x3C
NOR $2,$1,$2
R[2] = 0x03
0xF0NOR 0x3C
0x03
1111 0000NOR 0011 1100
0000 0011
4
NOR $2,$1,$1
R[2] = 0x0F
0xF0NOR 0xF0
0x0F
1111 0000NOR 1111 0000
0000 1111
Bitwise NOT operation can be performed by NOR’ing
register with itself
10.16
Shift Operations• Shifts data bits either left or right
– Bits shifted out and dropped on one side
– Usually (but not always) 0’s are shifted in on the other
side
• In addition to just moving bits around, shifting is a fast way
to multiply or divide a number by ____________(see next slides)
• 2 kinds of shifts
– Logical shifts (used for __________________ numbers)
– Arithmetic shifts (used for _________________ numbers)
0 0 0 0 0 0 1 1
Right Shift by 2 bits:
Original Data
Shifted by 2 bits
0 0 0 0 1 1 0 0
0 0 0 0 1 0 1 0 0 0
Left Shift by 2 bits:
Original Data
Shifted by 2 bits
0 0 0 0 1 0 1 0
0 00’s shifted in… 0’s shifted in…
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10.17
Logical Shift
• 0’s shifted in
• Only use for operations on unsigned data– Right shift by
n-bits = Dividing by 2n
– Left shift by n-bits = Multiplying by 2n
Logical Right Shift by 2 bits:
... _____________
Logical Left Shift by 3 bits:
0’s shifted in… 0’s shifted in…
0 ... 0 1 1 0 0 = +12
= +3 = +96
0 x 0 0 0 0 0 0 0 C
0 x 0 0 0 0 0 0 0 3 0 x 0 0 0 0 0 0 6 0
10.18
Arithmetic Shift
• Use for operations on signed data• Arithmetic Right Shift –
replicate MSB
– Right shift by n-bits = Dividing by 2n
• Arithmetic Left Shift – shifts in 0’s– Left shift by n-bits =
Multiplying by 2n
_ _ 1 ... 1 1 1
Arithmetic Right Shift by 2 bits:
1 ... 1 0 0 0 0
Arithmetic Left Shift by 2 bits:
MSB replicated and shifted in… 0’s shifted in…
1 1 ... 1 1 0 0 = -4
= -1 = -16
Notice if we shifted in 0’s (like a logical right shift) our
result would
be a positive number and the division wouldn’t work
0 x F F F F F F F C
0 x _ _ _ _ _ _ _ _Notice there is no difference between
an arithmetic and logical left shift. We always shift in
0’s.
0 x _ _ _ _ _ _ _ _ _
10.19
Logical Shift vs. Arithmetic Shift
• Logical Shift– Use for unsigned or non-
numeric data
– Will always shift in ______ whether it be a left or right
shift
• Arithmetic Shift– Use for signed data
– Left shift will shift in ____
– Right shift will ____________ (__________ the sign bit) rather
than shift in 0’s
• If negative number…stays negative by shifting in _____
• If positive…stays positive by shifting in ______
Right shift
Left shift
Right shift
Left shift
__
__
___
10.20
MIPS Logical Shift Instructions
• SRL instruction – Shift Right Logical• SLL instruction – Shift
Left Logical• Format:
– SxL rd, rt, shamt (shamt = shift amount and is a constant;
e.g. x
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10.21
MIPS Arithmetic Shift Instruction
• SRA instruction – Shift Right Arithmetic• No arithmetic left
shift (use SLL for arithmetic left shift)• Format:
– SRA rd, rt, shamt (shamt = shift amount and is a constant;
e.g. x >> 7)– SRAV rd, rt, rs (rs is the shift amount and is
variable; e.g. x >> y)
• Notes:– shamt limited to a 5-bit value (0-31)– SRAV shifts
data in rt by number of places specified in rs
• Examples– SRA $5, $12, 7– SRAV $5, $12, $20
000000 00000
opcode rs
01100
rt
00101
rd
00111
shamt
000011
func
Arith. Inst. unused $12 $5 7 SRA
000000 10100 01100 00101 00000 000111
Arith. Inst. $20 $12 $5 unused SRAV
10.22
Immediate Operands
• Most ALU instructions also have an immediate form to be used
when one operand is a constant value
• Syntax: ADDI Rs, Rt, imm
– Because immediates are limited to 16-bits, they must be
extended to a full 32-bits when used the by the processor
– ___________ instructions always sign-extend to a full 32-bits
even for unsigned instructions (addiu)
– ___________ instructions always zero-extend to a full
32-bits
• Examples:
– ADDI $4, $5, -1 // R[4] = R[5] + 0xFFFFFFFF
– ORI $10, $14, -4 // R[10] = R[14] | 0x0000FFFC
Arithmetic Logical
ADDI ANDI
SLTI ORI
XORI
Note: SUBI is unnecessary since we can use ADDI with a negative
immediate value
10.23
Set If Less-Than
• SLT $rd, $rs, $rt
– Compares $rs value with $rt value and stores Boolean (1 =
true, 0 = false) value
into $rd
– C code equivalent: _________________
– $rd can only be 0x0000001 or 0x00000000 after execution
– Assumes signed integer comparison
• SLTI $rd, $rs, immediate
– Same as above but now 2nd source is a constant
• SLTU $rd, $rs, $rt
– Same as SLT but interprets values as unsigned
SLT $4, $1, $2$4 = 0x0000000_
Initial Conditions:
$1= 0xffffffff, $2 = 0x00000000$3 = 0x000000ff
SLT $4, $3, $3$4 = 0x0000000_
SLT $4, $3, $1$4 = 0x0000000_
SLTI $4, $2, 35$4 = 0x0000000_
SLTU $4, $1, $2$4 = 0x0000000_
10.24
DATA TRANSFER AND MEMORY
ACCESS INSTRUCTIONS
Loading (Reading) and Storing (Writing) Data From and To
Memory
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10.25
Physical Memory Organization
• Physical view of memory as large 2-D array of bytes (8K rows
by 1KB columns) per chip (and several chips)
• Address is broken into fields of bits that are used to
identify where in the array the desired 32-bit word is
– Processor always accesses memory chunks the size of the data
bus, selecting only the desired bytes as specified by the
instruction
...
…
Physical View of Memory
...
Proc.
32
32
A
D
Rank/Bank Row Col
Sample Address Breakdown
...
...
XX
0x00000404
00000 0000000000001 00000001 000x0404 =
0x000000
0x000400
0x000800
Assume each unit is a word
10.26
MIPS Supported Data Sizes
Integer
• 3 Sizes Defined
– Byte (B)
• 8-bits
– Halfword (H)
• 16-bits = 2 bytes
– Word (W)
• 32-bits = 4 bytes
Floating Point
• 3 Sizes Defined
– Single (S)
• 32-bits = 4 bytes
– Double (D)
• 64-bits = 8 bytes
• (For a 32-bit data bus, a double would be accessed
from memory in 2 reads)
10.27
MIPS Memory Organization• We can logically picture
memory in the units (sizes) that we actually access them
• Most processors are __________________________
– Every byte (8-bits) has a unique address
– 32-bit address bus => 4 GB address space
• However, 32-bit logical data bus allows us to access _______
of data at a time
• Logical view of memory arranged in rows of 4-bytes
– Still with separate addresses for each byte
5A 0x000000
13
F8
…
0x000001
0x000002
Logical Byte-Oriented View of Mem.
Proc. Mem.
32
32
A
D
5A137C
2933
… 0x000008
0x000004
0x000000
Logical Word-Oriented View
F8
AD8E
int x,y=5;z=8;x = y+z;
Recall variables live in memory & need to
be loaded into the processor to be used
10.28
Memory & Data Size
Byte operations only access the byte at the specified
address
NN+1N+2N+3
(Assume start address = N)
Halfword operations access the 2-bytes starting at the specified
address
NN+1N+2N+3
Word operations access the 4-bytes starting at the specified
address
NN+1N+2N+3
• Little-endian memory can be thought of as right justified
• Always provide the LS-Byte address of the desired data
• Size is explicitly defined by the instruction used
• Memory Access Rules
– Halfword or Word access must start on an address that is a
multiple of that data size (i.e. half = multiple of 2, word =
multiple of 4)
Byte
31 0
Half
15
Word
31 0
LB
LH
LW
Registers: Memory
Used to load a 1-byte var. (char)
Used to load a 4-byte variable (int)
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10.29
Memory Read Instructions (Signed)
LB (Load Byte)Provide address of
desired byte
LH (Load Half)Provide address of
starting byte
LW (Load Word)Provide address of
starting byte
Sign Extend
31 0
Byte
7
GPR
Sign Extend
31 0
Half
15
Word
31 0
If address = 0x02Reg. = 0x_____________
If address = 0x00Reg. = 0x_____________
If address = 0x00Reg. = 0x____________
5A 13 7C
… 000004
000000F8
5A 13 7C
… 000004
000000F8
5A 13 7C
… 000004
000000F8
Memory
10.30
Memory Read Instructions (Unsigned)
LBU (Load Byte)Provide address of
desired byte
LHU (Load Half)Provide address of
starting byte
LW (Load Word)Provide address of
starting byte
Zero Extend
31 0
Byte
7
GPR
Zero Extend
31 0
Half
15
Word
31 0
If address = 0x01Reg. = 0x__________
If address = 0x00Reg. = 0x___________
If address = 0x00Reg. = 0x____________
Memory
5A 13 7C
… 000004
000000F8
5A 13 7C
… 000004
000000F8
5A 13 7C
… 000004
000000F8
10.31
Memory Write Instructions
SB (Store Byte)Provide address of
desired byte
SH (Store Half)Provide address of
starting byte
SW (Store Word)Provide address of
starting byte
if address = 0x02
if address = 0x02
if address = 0x00
Memory
31 0
Byte
7
GPR
31 0
Half
15
Word
31 0
Reg. = 0x12345678
Reg. = 0x12345678
Reg. = 0x12345678
… 000004
000000
… 000004
000000
… 000004
000000
10.32
MIPS Memory Alignment Limitations
• Bytes can start at any address• Halfwords must start on an
even address
• Words must start on an address that is a multiple of 4
• Examples:– Word @ A18C –
– Halfword @ FFE6 –
– Word @ A18E –
– Halfword @ FFE5 –
F87C
…
00A18C
Addr
00FFE4C1 4B29EA
49CF
5A13
BD52
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10.33
Load Format (LW,LH,LB)
• Syntax: LW $rt, offset($rs)
– $rt = Destination register
– offset($rs) = Address of desired data
– Operation: $rt = Mem[ offset + $rs ]
– offset limited to 16-bit signed number
• Examples
– LW $2, 0x40($3) // $2 = ________________
– LBU $2, -1($4) // $2 = ________________
– LH $2, 0xFFFC($4) // $2 = ________________
5A12C5B7
0x002048
134982FE
F8BE97CD
0x002044
0x002040
00002000$3
0000204C$4
old val.$2
MemoryAddress
Registers
10.34
More LOAD Examples
• Examples
– LB $2,0x45($3) // $2 = _____________
– LH $2,-6($4) // $2 = _____________
– LHU $2, -2($4) // $2 = _____________
5A12C5B7
0x002048
134982FE
F8BE97CD
0x002044
0x002040
00002000
0000204C
old val.
$3
$4
$2
MemoryAddress
Registers
10.35
Store Format (SW,SH,SB)
• SW $rt, offset($rs)
– $rt = Source register
– offset($rs) = Address to store data
– Operation: Mem[ offset + $rs ] = $rt
– offset limited to 16-bit signed number
• Examples
– SW $2, 0x40($3)
– SB $2, -5($4)
– SH $2, 0xFFFE($4)
00002000
0000204C
123489AB
$3
$4
$2
Memory AddressRegisters
0x002048_ _ _ _ _ _ _ _
0x002044
0x002040
_ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _
10.36
Loading an Immediate
• If immediate (constant) ___________________
– Use ______ or _________ instruction with _____ register
– Examples
• ADDI $2, $0, 1 // $2 = 0 + 1 = 1 (Loads const. 1 into $2)
• ORI $2, $0, 0xF110 // $2 = 0 | 0xF110 = 0xF110 (Loads
0xF110)
• If immediate more than 16-bits
– Immediates limited to 16-bits so we must load constant with a
2 instruction sequence using the special
___________________________ instruction
– To load $2 with 0x12345678
• _______________________
• _______________________
$2
$2
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10.37
I-Type Instructions
• I-Type (Immediate) Format
– rs, rt are 5-bit fields for register numbers
– I = Immediate is a 16-bit constant
– opcode identifies actual operation
• Example:
– ADDI $5, $24, 1
– LW $5, -8($3)
opcode rs (src1)
6-bits 5-bits
rt (src/dst)
5-bits
immediate
16-bits
001000 11000
opcode rs
00101
rt
ADDI $24 $5
immediate
1
010111 00011 00101
LW $3 $5 -8LW is explained in the next sectionbut is an example
of an instruction
using the I-type format
Fill me in…
10.38
Translating to Machine Code• 32-bit Fixed Size Instructions
broken into 3 types (R-, I-, and J-)
based on __________…
• ___________
– Arithmetic/Logic instructions
– 3 register operands or shift amount
• ___________
– Use for data transfer, branches, etc.
– 2 registers +16-bit const.
• _________
– 26-bit jump address
– We'll cover this later
opcode rs (src1)
6-bits 5-bits
rt (src2)
5-bits
rd (dest)
5-bits
shamt
5-bits
function
6-bits
opcode rs (src1)
6-bits 5-bits
rt (src/dst)
5-bits
immediate
16-bits
opcode__-Type Jump address
26-bits6-bits
__-Type
__-Type
add $5,$7,$8 000000 ______ ______ ______ ______ 100000
lw $18, -4($3) 100011 ______ ______ _____ _____ _____ _____
j 0x0400018 000010 0000 0100 0000 0000 0000 0001 10
Each type uses portions of the instruction to "code" certain
aspects ofthe instruction. But they all start with an opcode that
helps determine
which type will be used.
10.39
COMPILING HIGH-LEVEL CODE
"Be the Compiler"
10.40
Tips for Translating to Assembly
• We will now translate C code to assembly
• A few things to remember:
– Data variables live in memory
– Data must be brought into registers before being processed
– You must have an address/pointer in a register to load/store
data to/from memory
• Generally, you will need 4 steps to translate C to
assembly:
– ________________ in a register (LUI + ORI)
– _______ data from memory to a register (___________)
– ___________ data (ADD, SUB, AND, OR, etc.)
– ________ data back to memory (____________)
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10.41
Translating HLL to Assembly
• HLL variables are simply locations in memory
– A variable name really translates to an address in assemblyC
operator Assembly Notes
int x,y,z;…x = y + z;
LUI $8, 0x1000ORI $8, $8, 0x0004
Assume x @ 0x10000004& y @ 0x10000008& z @
0x1000000C
char a[100];…a[1]--;
Assume array ‘a’ starts @ 0x1000000C
10.42
Translating HLL to Assembly
C operator Assembly Notes
int dat[4],x;…x = dat[0];x += dat[1];
LUI $8, 0x1000ORI $8, $8, 0x0010LW $9, 0($8)
Assume dat @ 0x10000010& x @ 0x10000020
unsigned int y;short z;y = y / 4;z = z
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10.45
Our Simulator - MARS
Download at:
http://courses.missouristate.edu/KenVollmar/MARS/
10.46
Assembler Syntax
• In MARS and most assemblers each line of the assembly program
may be one of three
possible options
– Comment
– Instruction / Pseudo-instruction
– _________________________
10.47
Comments
• In MARS an entire line can be marked as a comment by starting
it with a pound (#) character:
• Example:
# This line will be ignored by the assembler
LW $2,8($3)
ADDI $2,$2,1
...
10.48
Instructions
• In MARS each instruction is written on a separate line and has
the following syntax:(Label:) Instruc. Op. Operands Comment
• Example:
START: ADD $2,$3,$4 # R[2]=R[3] + R[4]
• Notes:
– Label is optional and is a text identifier for the address
where the instruction is placed in memory. (These are normally used
to identify the target of a branch or jump instruction.)
– In MARS, a comment can be inserted after an instruction by
using a ‘#’ sign
– A label can be on a line by itself in which case it refers to
the address of the first instruction listed after it
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10.49
Labels and Instructions
• The optional label in front of an instruction evaluates to the
____________ where the instruction or data starts in memory and can
be used in other instructions
.text
START: LW $4,8($10)
L1: ADDI $4,$4,-1
BNE $4,$0,L1
J START
LW
ADDI
BNE
J
0x400000 = START
0x400004 = L1
0x400008
0x40000C
Assembly Source File
…and replaces the labels with their corresponding address
Assembler finds what address each instruction
starts at…
Note: The BNE instruc. causes the program to branch (jump) to
the
instruction at the specified address if the two operands are Not
Equal. The J(ump) instruction causes program execution to jump to
the specified label (address).
.text
LW $4,8($10)
ADDI $4,$4,-1
BNE $4,$0,0x400004
J 0x400000
10.50
Assembler Directives
• Similar to pre-processor statements (#include, #define, etc.)
and global variable declarations in
C/C++
– Text and data segments
– Reserving & initializing global variables and
constants
– Compiler and linker status
• Direct the assembler in how to assemble the actual
instructions and how to initialize memory when the
program is loaded
10.51
An Example
• This is output from an actual MIPS gcc/g++
compiler
• Actual instructions are at the bottom (addiu, srl, etc.)
• Directives are the things starting with .
• Labels are names ending with :
• Let's learn about some of the directives
x:
.word 5
.globl nums
.section .bss
.align 2
.type nums, @object
.size nums, 40
nums:
.space 40
.text
.align 2
.globl _Z6calleei
$LFB2:
.ent _Z6calleei
_Z6calleei:
.frame $sp,0,$31
.mask 0x00000000,0
.fmask 0x00000000,0
addiu $2,$4,3
srl $3,$2,31
addu $2,$2,$3
10.52
Text and Static Data Segments
• .text directive indicates the following instructions should
be
placed in the program area of
memory
• .data directive indicates the following data declarations
will
be placed in the data memory
segment
Unused
0x0040_0000
Text Segment
Static Data Segment
Dynamic Data Segment
Stack
I/O Space
0x1000_0000
0x8000_0000
0xFFFF_FFFC
0x1000_8000
0x7FFF_FFFC
0x0000_0000
-
10.53
Static Data Directives
• Fills memory with specified data when program is loaded
• Format:
(Label:) .type_id val_0,val_1,…,val_n
• type_id = {.byte, .half, .word, .float, .double}
• Each value in the comma separated list will be stored using
the indicated size
– Example: myval: .word 1, 2, 0x0003
• Each value 1, 2, 3 is stored as a word (i.e. 32-bits)
• Label “myval” evaluates to the start address of the first word
(i.e. of the value 1)
10.54
More Static Data Directives
• Can be used to initialize ASCII strings
• Format:
(Label:) .ascii “string”
(Label:) .asciiz “string”
• .asciiz adds a null-termination character (0) at the end of
the string while .ascii does not
– Example: myval: .asciiz “Hello world\n”
• C-strings are just character arrays terminated with a null
character ('\0' ASCII = 00 decimal)
• Each character stored as a byte (including '\n' = Line
Feed)
• Label “myval” evaluates to the start address of the first byte
of the string
10.55
Reserving Memory
• Reserves space in memory but leaves the contents unchanged
• Format:
(Label:) .space num_bytes
.data
dat1: .word 0x12345678
array: .space 4
dat2: .word 0xFEDCBA98
00 00 00 00
FE DC BA 98
0x1000000C
00 00 00 00
0x10000008 = dat2
0x10000004 = array
12 34 56 78 0x10000000 = dat1
Skipped
10.56
Alignment Directive
• Used to skip to the next, correctly-aligned address for the
given data size
• Format:
• 0 = byte-, 1 = half-, 2 = word-, 3 = double-alignment
.align 0,1,2, or 3
.data
dat1: .byte 1, 2, 3
.align 1
dat2: .half 0x4567
.align 2
dat3: .word 0x89ABCDEF
00 00 00 00
89 AB CD EF
0x1000000C
00 00 45 67
0x10000008 = dat3
0x10000004 = dat2
00 03 02 01 0x10000000 = dat1Skipped
Skipped
Note: The number after .align is not how many bytes to skip, it
indicates what type of data will come
next and thus the size to be aligned
-
10.57
.data example Examples
• C1 evaluates to ________________________
• MSG evaluates to ________________ (Note: \n = Line Feed char.
= 0x0A)
• DAT evaluates to _________________
• VAR evaluates to _________________
.data
C1: .byte 0xFE,0x05
MSG: .asciiz “SC\n”
DAT: .half 1,2
.align 2
VAR: .word 0x12345678 0x10010000
0x10010004
0x10010008
0x1001000C
10.58
C/C++ and Directives
• Directives are used to initialize or reserve space for global
variables in C
short int count = 7;
char message[16];
int table[8] = {0,1,2,3,4,5,6,7};
void main()
{
...
}
.data
count:
message:
.align ______
table: .word ________________
.text
.globl main
main: ...
C/C++ style global declarations Assembly equivalent
10.59
Summary & Notes
• Assembler Directives:– Tell the assembler how to build the
program memory
image• Where instructions and data should be placed in memory
when
the program is loaded
• How to initialize certain global variables
• Recall, a compiler/assembler simply outputs a memory IMAGE of
the program. It must then be loaded into memory by the OS to be
executed.
• Key: Directives are NOT instructions!– They are used by the
assembler to create the memory
image and then removed
– The MIPS processor never sees these directives!
10.60
Directives in the Software Flow
1110 0010 0101 10010110 1011 0000 11000100 1101 0111 11111010
1100 0010 10110001 0110 0011 1000
MOVE.W X,D0CMPI.W #0,D0BLE SKIPADD Y,D0SUB Z,D0
SKIP MUL …
High Level Language
Description
Assembly (.asm/.s files)
Executable Binary Image
int n = 0xC259;void main(){if (x > 0)x = x + y - z;
a = b*x;
.datan: .word 0xC259
.textSLT $4,$2,$0BNE SKIP…
SKIP: MUL …
1110 0010 0101 10010110 1011 0000 11000100 1101 0111 11111010
1100 0010 10110001 0110 0011 1000
.c/.cpp files1110 0010 0101 10010110 1011 0000 11000100 1101
0111 11111010 1100 0010 10110001 0110 0011 1000
Object/Machine Code(.o files)
Compiler
Assembler
LinkerLoader /
OS
Program Executing
Assembler Directives are used to create the
object code (executable) image…
…the processor NEVER sees/executes these
directives
PC
SLT
BNE
-
10.61
Pseudo-instructions
• “Macros” translated by the assembler to instructions actually
supported by the HW
• Simplifies writing code in assembly
• Example – LI (Load-immediate) pseudo-instruction translated by
assembler to 2
instruction sequence (LUI & ORI)
...
lui $2, 0x1234
ori $2, $2, 0x5678
...
...
li $2, 0x12345678
...
With pseudo-instruction After assembler…
10.62
Pseudo-instructions
Pseudo-instruction Actual Assembly
NOT Rd,Rs NOR Rd,Rs,$0
NEG Rd,Rs SUB Rd,$0,Rs
LI Rt, immed. # Load Immediate LUI Rt, {immediate[31:16],
16’b0}
ORI Rt, {16’b0, immediate[15:0]}
LA Rt, label # Load Address LUI Rt, {immediate[31:16],
16’b0}
ORI Rt, {16’b0, immediate[15:0]}
BLT Rs,Rt,Label SLT $1,Rs,Rt
BNE $1,$0,Label
Note: Pseudoinstructions are assembler-dependent. See MARS Help
for more details.
10.63
Support for Pseudo-instructions
• Pseudo-instructions often expand to several instructions and
there is a need for usage of a
temporary register
• Assembler reserves register $1
– In the assembler, $1 = $at (assembler temp.)
• You can use $1 but it will be overwritten when you use certain
pseudo-instructions
10.64
Coding Exercise with MARS
• int x = 7, y = 5, z = 3; z = x * z + (x – y++)
• # #DEFINE MASK 0xe0;# PORTD &= ~(MASK)
# PORTD |= ((x
-
10.65
INSTRUCTION SET ARCHITECTURE
What are the common features of all processor instruction
sets?
10.66
Components of an ISA
1. ________ and Address Size– 8-, 16-, 32-, 64-bit
2. Which instructions does the processor support– SUBtract
instruc. vs. NEGate + ADD instrucs.
3. ________________________ of instructions– How is the
operation and operands represented with 1’s
and 0’s
4. __________ accessible to the instructions– Faster than
accessing data from memory
5. Addressing Modes– How instructions can specify location of
data operands
10.67
Historic Progression of Data Size & Registers
Processor Year Trans. Count
Data Size GPRs
8088 1979 29K 8 8
80286 1982 134K 16 8
80386/486 ’85/’89 275K/1.18M
32 8
Pentium 1993 3.1M 32 >8
Pentium 4 2000 42M 32 >= 128
Core 2 Duo 2006 291M 64 >= 128
6-core Core i7 2011 2.27B 64 >= 128
MIPS 1999 var. 32 32
10.68
General Instruction Format Issues
• Instructions must specify three things:
– ______________________________________
– Source operands
• Usually 2 source operands (e.g. X+Y)
– ______________________________________
• Example: ADD $8, $9, $10 ($8 = $9 + $10 where $ =
Register)
• Binary (machine-code) representation broken into fields of
bits for each part
000000 00000
Arith. Unused
OpCode
100000
Add
FunctionShift Amount
01001 01010
$9 $10
Src. 1 Src. 2 Dest.
01000
$8
-
10.69
Historical Instruction Formats
• Different instruction sets specify these differently
– 3 operand instruction set (MIPS, PPC, ARM)
• Similar to example on previous page
• Format: ADD DST, SRC1, SRC2 (DST = SRC1 + SRC2)
– 2 operand instructions (Intel / Motorola 68K)
• Second operand doubles as source and destination
• Format: ADD SRC1, S2/D (S2/D = SRC1 + S2/D)
– 1 operand instructions (Old Intel FP, Low-End Embedded)
• Implicit operand to every instruction usually known as the
Accumulator (or ACC) register
• Format: ADD SRC1 (ACC = ACC + SRC1)
10.70
Historical Instruction Format Examples
Single-Operand Two-Operand Three-OperandLOAD X
ADD Y
SUB Z
STORE F
LOAD A
ADD B
STORE G
MOVE F,X
ADD F,Y
SUB F,Z
MOVE G,A
ADD G,B
ADD F,X,Y
SUB F,F,Z
ADD G,A,B
(+) Smaller size to encode each instruction
(-) Higher instruction count to load and store ACC value
Compromise of two extremes (+) More natural program style
(+) Smaller instruction count
(-) Larger size to encode each instruction
• Consider the pros and cons of each format when performing the
set of operations– F = X + Y – Z– G = A + B
• Simple embedded computers often use single operand format –
Smaller data size (8-bit or 16-bit machines) means limited instruc.
size
• Modern, high performance processors use 2- and 3-operand
formats
10.71
MIPS Instruction Format
• _______________ operand format
– Most ALU instructions use 3 registers as their operands
– All operations are performed on entire 32-bits (no size
distinction)
– Example: ADD $t0, $t1, $t2
• ______________ architecture
– Load (read) data values from memory into a register
– Perform operations on registers
– Store (write) data values back to memory
– Different load/store instructions for different operand sizes
(i.e. byte, half, word)
Proc.
1.) Load operands to proc. registers
Mem.
Proc.
2.) Proc. Performs operation using register values
Mem.
Proc.
3.) Store results back to memory
Mem.
Load/Store Architecture
