EE-527: MicroFabrication527: MicroFabrication · 2017-10-03 · Photomask Design Layer SetupPhotomask Design Layer Setup • Example for the EE-527 M4 mask set: Mask Layer Layout

EE-527: MicroFabricationEE 527: MicroFabrication

Photomask Design

R. B. Darling / EE-527 / Winter 2013

Photomask Physical Construction ConsiderationsPhotomask Physical Construction Considerations

• CostR l i• Resolution

• Critical dimension accuracy• Wear / lifespan• Wear / lifespan• Illumination wavelength• Plate-to-plate tolerances for multi-mask setsp• Printing method• Thickness of the plate• Flatness• Temperature stability (thermal expansion coefficient)


• Mask polarity

Photomask Geometrical Design Considerations - 1Photomask Geometrical Design Considerations 1

• Wafer sizeDi i• Die size

• Die array on wafer• Device minimum feature size• Device minimum feature size• Layout grid size• Manufacturing grid sizeg g• Floor planning

– Active device core and standard cell arrays– Interconnect channels– Bus ring for power distribution– Pad frame and wire bonding scheme


– Thermal allowances & ESD/EOS protection

Photomask Geometrical Design Considerations - 2Photomask Geometrical Design Considerations 2

• Physical layout design rulesAli k• Alignment markers– Layer-to-layer and cumulative– Visual, coarse, fine, vernier– Marker placement

• Proximity and density effectsh i k d bl• Process shrinks and bloats

• Corner compensation• Process test patterns• Process test patterns• Diagnostic devices and probe pads• Dicing and packaging fiducial marks


Dicing and packaging fiducial marks

Photomask MaterialsPhotomask Materials• Substrates:

– Soda lime glass: poor transmission, >8.9 ppm/C, n = 1.515B ili t l (P ) 350 2000 3 25 /C 1 474– Borosilicate glass (Pyrex): 350 – 2000 nm, 3.25 ppm/C, n = 1.474

– Quartz (fused silica, SiO2): 220 – 2000 nm, 0.55 ppm/C, n = 1.458– Sapphire (Al2O3): 190 – 5000 nm, 5.3 ppm/C, n = 1.780

• Blocking layer: generally need an optical density (OD) > 4 0• Blocking layer: generally need an optical density (OD) > 4.0– Fe2O3 (least expensive)– Cr (best finish and uniformity)

• Standard mask plate thicknesses for the Oriel aligners:Standard mask plate thicknesses for the Oriel aligners: – 4-inch square mask plate: 0.062 inches– 5-inch square mask plate: 0.093 inches

• Pellicles: used only for projection systemsPellicles: used only for projection systems• Master versus daughter plates, polarity reversals, mirror reversals• Transparency films:

– Overhead xerox transparencies using toner: forget it – they don’t work!


Overhead xerox transparencies using toner: forget it they don t work!– Professional phototransparencies: need emulsion coatings for OD > 3.0

Photomask FabricationPhotomask Fabrication

• Photoplotter– Least expensive: ~$250/plateLeast expensive: $250/plate– Aperture wheel (Gerber style) with vectored flashes– Used most commonly in the PCB industry– Resolution down to ~25 microns = 1 milResolution down to ~25 microns 1 mil

• Direct-write laser– Intermediate cost: ~$350 to $650/plate

Vector pattern generation– Vector pattern generation– Resolution down to ~2.5 microns

• Direct-write e-beamM i $2500/ l ( l l) b i h– Most expensive: ~$2500/plate (entry level) + beam time charge

– The Etec MEBES system was the original, MEBES-IV is current– Raster scan with vectored subfields; field stitching requirements

R l i d 20


– Resolution down to ~20 nm

Example: EE-527 Mask Set M3 (5-mask set)Example: EE 527 Mask Set M3 (5 mask set)


(3-inch wafer)

Example: EE-527 Mask Set M4 (6-mask set)Example: EE 527 Mask Set M4 (6 mask set)


(100 mm wafer)

Photomask Design FundamentalsPhotomask Design Fundamentals• Always laid out on a grid:

– usually 1 nm for ICs, ll 1 f PCB– usually 1 m for PCBs;

– sometimes 1 mil for PCBs (English units)! • Always created in a layer-based hierarchy• Fundamental shapes:

– Boxes (rectangles)– Polygons: orthogonal, 45-degree, all-angle– Wires (lines of fixed width): orthogonal, 45-degree, all-angle– Curved lines must be synthesized from straight line segments!

• Standard output file formats in use: – CIF: Caltech Intermediate Format (not used much any more)– GDS-II: Graphical Database System – II (IC industry standard)– DXF: Drawing Exchange Format (AutoCAD)


g g ( )– NOTE: Visio, PowerPoint, Corel Draw, etc. are not suitable formats…

Photomask LayersPhotomask Layers

• Drawn layersC t i th ti h i l l t i f ti– Contain the native physical layout information:

• Physical process features: metals, vias, poly, contacts, n+, p+, etc.• Device and area identifications: resistors, capacitors, diodes, etc.

• Utility layers– Contain constructions used to assist in the layout:

• grid points, origins, rulers, labels, not-exists, keep-ins, keep-outsg p , g , , , , p , p

• Derived layers– Are computed from other layers using image morphology

operations: AND OR NOT GROW SHRINKoperations: AND, OR, NOT, GROW, SHRINK– Used for creating and adjusting layers for photomask fabrication– Used for design validation tools: design rule checks, circuit and

i i i i i h kR. B. Darling / EE-527 / Winter 2013

parasitic extraction, connectivity checks, etc.

Photomask Design Layer SetupPhotomask Design Layer Setup• Example for the EE-527 M3 mask set:

Mask Number

Layer Name

Layout Color

Process Type

Polarity Alignment

1 Contact etch dark field1 Contact etch dark field

2 Metal1 deposit + liftoff

dark fieldliftoff

3 Via etch dark field

4 Metal2 deposit + dark field4 Metal2 deposit + liftoff

dark field

5 Overglass etch dark field


Photomask Design Layer SetupPhotomask Design Layer Setup• Example for the EE-527 M4 mask set: Mask Layer Layout Process Polarity AlignmentMask Number

Layer Name

Layout Color

Process Type

Polarity Alignment

1 Align etch dark field

2 PDiff etch + diffuse

dark field

3 NDiff t h + d k fi ld3 NDiff etch + diffuse

dark field

4 Active etch dark field

5 Contact etch dark field


6 Metal1 deposit + liftoff

dark field

Mask PolarityMask Polarity• Bright field: drawn features are opaque – easy to align

– Make the alignment cross hairs are smaller than the wafer targets. • Dark field: drawn features are transparent – requires building in

windows for alignment– Make the alignment cross hairs are larger than the wafer targets.

Bright field mask cross hairs Dark field mask cross hairs

R. B. Darling / EE-527 / Winter 2013Alignment target on wafer

MisalignmentMisalignment

• Different views for bright field versus dark field: – In both cases, the mask (in yellow) is shifted up and to the right:

Bright field mask cross hairs Dark field mask cross hairs

R. B. Darling / EE-527 / Winter 2013Alignment target on wafer

Wafer Alignment Mark Targets and Cross HairsWafer Alignment Mark Targets and Cross Hairs• Coarse: 50 m targets with 100 m cross hairs• Fine: 10 m targets with 20 m cross hairs• Usually adequate for contact alignment to within ±1 µm.


Verniers to Measure Alignment AccuracyVerniers to Measure Alignment Accuracy

Pitch of vernier ticks is increased by 5 µm (coarse) and 2 µm (fine) from mating ticks on the prior mask. By finding the pair of mating ticks which matches best, the alignment error can be determined to ±0.5 µm.


EE-527 M4 Mask Set: Visual Alignment KeysEE 527 M4 Mask Set: Visual Alignment KeysNorth

NEmarkermarker

The NE marker guarantees that the mask and wafer are not accidentally rotated by 90

West East

accidentally rotated by 90 degrees.

Visual alignment keys are usually the largest open feature in a dark-field mask and very useful for making sure the wafer is roughly aligned to the mask before


Southaligned to the mask before using the microscope for the finer adjustments.

Process DiagnosticsProcess Diagnostics• Each mask set should provide test structures by which to troubleshoot

problems and monitor the fabrication process. • Process diagnostics:• Process diagnostics:

– photoresist tuning: prebake / exposure / development– doping levels: sheet resistance

metal conductivity: sheet resistance and tempco– metal conductivity: sheet resistance and tempco– MOS oxide: field-effect, threshold voltage, trapping: MOS capacitors– interlevel dielectric breakdown strength and capacitance: MIM capacitors

via reliability and resistance: via chains– via reliability and resistance: via chains– contact reliability and resistance: contact chains

• Device diagnostics: t t t i t di d b i it– test transistors, diodes, or sub-circuits

• variable gate widths• variable gate lengths• ring oscillator


ring oscillator• pn-junction diode I-V and leakage• Schottky diode I-V and leakage

Process Diagnostic: Photoresist Line/Space PatternsProcess Diagnostic: Photoresist Line/Space Patterns

Proper prebake, exposure, and p p , p ,development should produce a 50:50 line and space pattern.

This pattern is usually easy to tune with an opticaltune with an optical microscope and avoids the need for using an SEM.


Process Diagnostic: 4-Point Resistivity (Substrate)Process Diagnostic: 4 Point Resistivity (Substrate)• 100 m dia. contacts, 1000 m and 500 m spacings:

Diagnostic Probe Pads :

800 m x 800 m square,

1250 m pitch, p ,

approx. = 0.050 in pitch,

designed for use with a standard 4-point probe headhead.

The photolithographically defined contacts provide a much higher accuracy 4-point probe measurementpoint probe measurement than most commercial 4-point probe heads!


Process Diagnostic: 4-Point Resistivity (Diffusions)Process Diagnostic: 4 Point Resistivity (Diffusions)• Test bars of different doped regions, 200 µm wide.

Diagnostic Probe Pads :

1000 m x 1000 m square,

2000 m pitch.

It is designed for use with a standard 5-point pogo pin test head:

4-wire Kelvin resistance measurement with a separate substrate ground connection.

Bar contacts are 40 µm square, 1 x 2 array

Substrate contacts are 50 µm round


50 µm round.

Process Diagnostic: Metal Sheet ResistanceProcess Diagnostic: Metal Sheet Resistance• 2751 squares in M1; same pattern also for M2:


Process Diagnostic: Interlevel Dielectric CapacitorsProcess Diagnostic: Interlevel Dielectric Capacitors• radius = 1175 m, overlap area = 4.3374 mm2:


Process Diagnostic: M1-Via-M2 ChainsProcess Diagnostic: M1 Via M2 Chains• 1080 (30 x 36) vias (20 m sq.) in series, 2 instances:

R. B. Darling / EE-527 / Winter 2013This is also a stringent test of via yield!

Process Diagnostic: Interconnect ResistancesProcess Diagnostic: Interconnect ResistancesUpper three test structures provide a 4-wire Kelvin resistance measurement ofresistance measurement of 2 contacts (20 µm sq. ea.) plus three different lengths of n-type diffusion.

Th th i tThese three resistance measurements can be used to extract the resistance of each contact and the sheet resistance of the n-type ypdiffusion.

The lower structure provides a measurement of the sheet resistance ofthe sheet resistance of Metal1 using 3690 squares.


Process Diagnostics: Example SOS-CMOS DevelopmentProcess Diagnostics: Example SOS CMOS Development

• Developed at Stanford University over 1997-1998• High voltage process for charge pumps HV actuators and photodiodes• High voltage process for charge pumps , HV actuators, and photodiodes• 20.0 x 7.6 mm die; about half of the die is process diagnostics


Bonding PadsBonding Pads• Note: Bonding pads do not scale with Moore’s Law!

– A bond wire is still the same diameter as it has always been. • Size is dictated by the bonding technology:

– 100 m sq. is large and generous, and allows at least 2 tries with either gold ball or aluminum wedge bonders.

– 50 m sq. is about the smallest practical for commercial ICs. – 200 m sq. is used in the EE-527 masks.

• Probe pads may also be used: – Size depends upon the probe station. – 50 m is good for general research. – 25 m is reasonable with high end probes.

• Pogo pin pads: (huge!) – 200 to 1000 µm for wafer contact points. – Not common, but useful for R&D.


– Good for very fast, low cost wafer testing.

Bonding Pad ConstructionBonding Pad Construction• Generally want as much metal as possible underneath a bond pad.

– Use all available metal layers. U i l l i b l l– Use single large vias between metal layers.

– This may violate some design rules (e.g. exact via size). • Make vias generously smaller than the metal pads to hem the edges.

R. B. Darling / EE-527 / Winter 2013A hemmed edge helps keep the metal from lifting during bond wire attachment.

EE-527 M3 Mask Set Die Layout and Pad FrameEE 527 M3 Mask Set Die Layout and Pad Frame4.00 mm sq. die

2.40 mm sq. core area

32-pad frame (8 x 8 quad)

200 m sq. pads

300 m pad pitch

di i fid i l k ddicing fiducial marks on edges

50 m dicing streets

alignment validation markers

l ilogos in corners


Pad Frame: Example Active Cilia Array ChipPad Frame: Example Active Cilia Array Chip• Developed at Stanford University over 1996-1997• Standford Quick-MOS process + 5 thermal bimorph MEMS layers


Design RulesDesign Rules

• Design rules are geometrical rules that can be applied to the layers of a physical layout to insure manufacturabilitythe layers of a physical layout to insure manufacturability of the design and function of the devices.

• Design rule dimensions: g– Absolute: e.g. microns or mils– Scalable: e.g. lambdas which change with the technology node

• Each design rule is applied to either:• Each design rule is applied to either: – Within a single layer, or– Between two layers.

• Exception cases can be prescribed: – intersections

coincidences


– coincidences– acute angles

Automatic Design Rule CheckingAutomatic Design Rule Checking

• Software suites for IC and PCB layout include subprograms for checking design rules either in a batchsubprograms for checking design rules, either in a batch mode or interactively.

• These are known as DRC tools, and they report back any y p yviolations of a rule within the specified test region.

• Examples: C d Vi t / A DRC– Cadence Virtuoso / Assura DRC

– Mentor Graphics Layout DRC– Tanner L-Edit DRC– Cadence OrCAD PCB Editor– Altium Designer PCB Editor


Design Rule TypesDesign Rule Types• DRC rules: can be checked automatically through layers

– Minimum Width– Exact Width– Spacing

Surround– Surround– Overlap– Extension– Density– Not Exist

• Other design rules:Other design rules: – Off grid objects– Pad frame allowances and restrictions

/ d i ll d i iR. B. Darling / EE-527 / Winter 2013

– ESD/EOS device allowances and restrictions

Example: Minimum Width RuleExample: Minimum Width Rule

• Rule 2.1: Metal1 minimum width = 5.0 m

5 0 m minimum5.0 m, minimum


Example: Exact Width RuleExample: Exact Width Rule

• Rule 3.1: Via exact width = 5.0 m

5.0 m, exactly


Example: Spacing RuleExample: Spacing Rule

• Rule 2.2: Metal1 to Metal1 spacing = 5.0 mR l 4 2 M l2 M l2 i 5 0• Rule 4.2: Metal2 to Metal2 spacing = 5.0 m

• Rule 4.3: Metal2 to Metal1 spacing = 5.0 m– Exceptions: coincident or intersectionExceptions: coincident or intersection

5.0 m, minimum5.0 m, minimum

5.0 m, minimum5.0 m, minimum

5.0 m, minimum


Example: Surround RuleExample: Surround Rule

• Rule 3.3: Via surrounded by Metal1 by 5.0 m

5.0 m, minimum


Mask Alignment ErrorsMask Alignment Errors• The average alignment error between the target and the crosshair is

Δxalign. This is a function of the aligner and the operator. E ith f t li t i l th f th l• Even with perfect alignment in one place on the wafer, other places may run out and be misaligned if the mask features do not register properly to the existing features across the entire wafer. Th k t k t i Δ d thi i ti l t th• The mask-to-mask run out is Δxrunout and this is proportional to the distance between the two points being examined: Δxrunout = k·L.

– For step-and-repeat systems, L is the die or reticle size. F t t li L i th i f th f– For contact aligners, L is the size of the wafer.

• The greatest contributor to Δxrunout is thermal expansion mismatches between the mask plate and the wafer:

k (C C )( )– k = (CTEwafer – CTEmask)(Texposure1 – Texposure2)– CTE = coefficient of thermal expansion: ΔL/L = CTE·ΔT [ppm/C].

• The temperature of an exposure system must be very closely controlled id hi T i l i l i hi i


to avoid this. Typical optical steppers operate within environments that are controlled to better than ±0.2C.

Critical Dimension ErrorsCritical Dimension Errors

• A critical dimension (CD) is a specified distance between two points on a mask which is used to guarantee mask-to-mask registration.on a mask which is used to guarantee mask to mask registration.

• The simplest CD is the distance between the two primary alignment marks on opposite sides of the mask.

• Specifying a CD will add cost to a mask set but all professional• Specifying a CD will add cost to a mask set, but all professional quality masks will have these, and the will place an upper bound on the mask-to-mask registration errors, ΔxCD.

• Note that exposing through a mask at a temperature different from• Note that exposing through a mask at a temperature different from what it was manufactured will change the CD value.

• CD values are always specified at a given temperature, usually 25C. O l t i d d d i l t ll b t• Overlap, extension and surround design rules must generally be greater than or equal to the sum of the alignment errors to insure electrical integrity (no shorts or opens): Δ > Δ + Δ + Δ


• Δxrule > Δxalign + Δxrunout + ΔxCD.

Using Mask Sets Effectively for R&DUsing Mask Sets Effectively for R&D• Mask sets are generally more effective when

professionally produced, but this adds more cost. • The investment in design and layout time should be offset

by a mask set which covers as much ground as possible. A h• Approaches: – Splits: Use different subsets of the same mask set to support

several slightly different, but largely common process flows. – Options: Add a few additional masks for optional process steps to

increase the overall versatility of the mask set. – Cells: Fabricate standard cells that are already tested and

interconnect them differently using only the last metal mask. – Multiproject: (MPW) Include several different project die within

the same mask set if the process flow can support them


simultaneously.

EE-527 M3 Mask Set: Fuse DieEE 527 M3 Mask Set: Fuse Die


EE-527 M3 Mask Set: MSM DieEE 527 M3 Mask Set: MSM Die


EE-527 M3 Mask Set: Inductor DieEE 527 M3 Mask Set: Inductor Die


EE-527 M3 Mask Set: Circular Capacitor DieEE 527 M3 Mask Set: Circular Capacitor Die


EE-527 M3 Mask Set: Square Capacitor DieEE 527 M3 Mask Set: Square Capacitor Die


EE-527 M3 Mask Set: Circular Diode DieEE 527 M3 Mask Set: Circular Diode Die


EE-527 M3 Mask Set: Square Diode DieEE 527 M3 Mask Set: Square Diode Die


EE-527 M4 Mask Set: Hall Effect / Van der PauwEE 527 M4 Mask Set: Hall Effect / Van der Pauw


EE-527 M4 Mask Set: Hall Effect / Van der PauwEE 527 M4 Mask Set: Hall Effect / Van der Pauw


EE-527 M4 Mask Set: Lateral pin DiodeEE 527 M4 Mask Set: Lateral pin Diode

n+ e terior 100 m sq are


n+ exterior: 100 µm squarep+ interior: 160 µm square

EE-527 M4 Mask Set: npn BJTEE 527 M4 Mask Set: npn BJT

C (sub)

E BE B

AE = 40 µm x 40 µm


AE 40 µm x 40 µm

EE-527 M4 Mask Set: MOS C-V Test CapacitorsEE 527 M4 Mask Set: MOS C V Test Capacitors


EE-527 M4 Mask Set: p-channel MOSFETEE 527 M4 Mask Set: p channel MOSFETG B

W = 10 µmL = 10 µm

D S


EE-527 M4 Mask Set: Large Area PhotodiodeEE 527 M4 Mask Set: Large Area Photodiode


EE-527 M4 Mask Set: Quad PhotodiodeEE 527 M4 Mask Set: Quad Photodiode


EE-527 M4 Mask Set: 10-Element Photodiode ArrayEE 527 M4 Mask Set: 10 Element Photodiode Array


Documents

EE-527: MicroFabrication527: MicroFabrication · 2017-10-03 · Photomask Design Layer SetupPhotomask Design Layer Setup • Example for the EE-527 M4 mask set: Mask Layer Layout