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Programmable logic

Devices (PLD)

Mantık Devreleri

Yard.Doç.Dr. Mutlu BOZTEPE

Programmable logic Devices

� Programmable Arrays� OR Array

� AND Array

� Classifications of Simple Programmable LogicDevices (SPLD)� Programmable Read-Only Memory (PROM)

� Programmable Logic Array (PLA)

� Programmable Array Logic (PAL)

� Generic Array Logic (GAL)

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OR Array

Figure 3--65 An example of a basic programmable OR array.

AND Array

Figure 3--66 An example of a basic programmable AND array.

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Programmable Read-Only Memory(PROM)

Figure 3--67 Block diagram of a PROM (programmable read-only memory).

Connectedas a decoder!

• The PROM is used primarly as an addressable memory and not as a logic

device because of limitations imposed by fixed AND gates.

Programmable Logic Array (PLA))

Figure 3--68 Block diagram of a PLA (programmable logic array).

• The PLA was developed to overcome some of the limitations of PROM. The

PLA is also called an FPLA (Field programmable logic array) because the user

in the field, not the manufacturer, programs it.

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Programmable Array Logic (PAL)

Figure 3--69 Block diagram of a PAL (programmable array logic).

• It was developed to overcome certain disadvantages of PLA, such as longer

delays due to the additional fusible links that result from using two

programmable arrays and more dificult complexity. The PAL is most common

one-time programmable (OTP) logic device and is implemented with bipolar

technology (TTL or ECL)

Generic Array Logic (GAL)

Figure 3--70 Block diagram of a GAL (generic array logic).

• The two main differences between GAL and PAL devices are:

• The GAL is reprogrammable

•The GAL has programmable output configurations.

• The GAL programmable again and again because it uses E2CMOS (electrically

erasable CMOS) technology instead of bipolar technology and fusible links.

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SPLD’s summary

PALs

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PAL Operation

Figure 4--44 Basic structure of a PAL.

Example

X=AB+AB’+A’B’

Figure 4--45 PAL implementation of a sum-of-products expression.

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Figure 4--46 Simplified diagram of a programmed PAL.

Example

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PAL Block Diagram

Tristate control

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PAL Output configuration Logic

Standart PAL numbering

PAL10L8

Programmablearray logic

Ten inputs Active low output

L: active-LOW

H: active-HIGH

P: programmable

polarity

Eight outputs

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PAL10L8

GALs

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SPLD’s summary

Generic Array Logic (GAL)

Figure 3--70 Block diagram of a GAL (generic array logic).

• The two main differences between GAL and PAL devices are:

• The GAL is reprogrammable

•The GAL has programmable output configurations.

• The GAL programmable again and again because it uses E2CMOS (electrically

erasable CMOS) technology instead of bipolar technology and fusible links.

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GAL Operation

PAL

The cells can be electrically erasedand reprogrammed.

A typical E2CMOS cell can retain itsprogrammed statefor 20 years ormore…

Example

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Example

GAL Block Diagram

OLMC: Output Logic Macrocells (Programmableoutput types!! Combinational

or registered)

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GAL22V10 OLMC configurations

� Active-LOW combinational mode

� Active-HIGH combinational mode

� Active-LOW registered mode

� Active-HIGH registered mode

GAL22V10 OLMC Configurations

S1=1 S0=0 Active-LOW combinational mode

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GAL22V10 OLMC Configurations

S1=1 S0=1 Active-HIGH combinational mode

GAL22V10 OLMC Configurations

S1=0 S0=0 Active-LOW registered mode

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GAL22V10 OLMC Configurations

S1=0 S0=1 Active-HIGH registered mode

GAL22V10 OLMC

Configurations

Output orInputselection:

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Example S0=? S1=?X=ABCD+A’BCD’+AB’CD’+A’BC’D+AB’CD+ABC’D

Standart GAL numbering

GAL16V8

Generic arraylogic

Sixteeninputs

Variable outputconfiguration

(remember OLMC)

Eight outputs

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PLD programming

GAL22V1012 inputs

10 input/outputs (I/O)

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GAL22V10

Array

Diagram

12 inputs

10 input/outputs (I/O)

GAL22V10 Array Diagram

cell numbers in OLMC blockfor programming S0 and S1

These 12 special cells (5808 through 5827) are not

shown in the array diagram

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GAL22V10

22 input lines132 product term lines

5808 E2PROM intersections

Each product term line consist of 44 AND gate inputs

Example: Implementing an SOP function

X=ABCDEF+AB’CD’EF’+A’BC’DE’F+A’BCDEF’+AB’C’D’E’F+A’B’C’DEF+A’B’C’D’E’F’

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GAL 16V8

GAL16V8 is

designed to be

programmed in

one of three

available modes

to emulate most

of the existing

PAL’s; thus, it

may replace the

PAL for which it

is programmed.

GAL16V8 OLMC configurations

� PAL Emulation� Simple mode

� Combinational output

� Combinational output with feedback to AND array

� Dedicated input

� Complex mode� Combinational output

� Combinational input/output (I/O)

� Registered mode� In chap.9

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GAL16V8 Simple mode

XOR determines

active state of

the output

GAL16V8 Complex mode

•XOR determines active state of the output

•The I/O’s are limited to 6 in this mode

•Notice that there are only 7 inputs to the OR gate!! Because 8th input is

used for tristate control

•This means OLMC can produce up to seven product terms in SOP

expression