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EE462L, Spring 2014

Implementation of Unipolar PWM Modulation for H-Bridge Inverter

(pre-fall 2009 - but discrete components provide a better sense of how this circuit operates)

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ABBAload VVVV

Switching rules

H-Bridge Inverter Basics – Creating AC from DC

Vdc

Load

A+ B+

A– B–

Va Vb

Either A+ or A– is closed, but never at the same time

Either B+ or B– is closed, but never at the same time

Can use identical isolated firing signals for A+, A–, with inverting and non-inverting drivers to turn on, turn off simultaneously

The A+, A– firing signal is a scaled version of Va

The B+, B– firing signal is a scaled version of Vb

The difference in the two firing signals is a scaled version of Vab

Same idea for B+, B–

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Vcont > Vtri , close switch A+, open switch A– , so voltage Va = Vdc Vcont < Vtri , open switch A+, close switch A– , so voltage Va = 0 –Vcont > Vtri , close switch B+, open switch B– , so voltage Vb = Vdc –Vcont < Vtri , open switch B+, close switch B– , so voltage Vb = 0

Vcont Vtri −Vcont

Implementation of Unipolar PWM

Vcont is usually a sinewave, but it can also be a music signal.

Vtri is a triangle wave whose frequency is at least 30 times greater

than Vcont.

The implementation rules are:

Vcont is the input signal we want to amplify at the output of the inverter.

Ratio ma = peak of control signal divided by peak of triangle wave

Ratio mf = frequency of triangle wave divided by frequency of control signal

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Vdc

−Vdc

Vload

Progressivelywider pulses at the center

(peak of sinusoid)

Progressively narrower pulses

at the edges

Unipolar Pulse-Width Modulation (PWM)

Implementation of Unipolar PWM Modulation for H-Bridge Inverter

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The four firing circuits do not have the same ground reference. Thus, the firing circuits require isolation.

Vdc (source of power delivered to load)

Load

A+ B+

A–

B–

Local ground reference for A+ firing circuit

Local ground reference for B+ firing circuit

Local ground reference for B− firing circuit

Local ground reference for A− firing circuit

S

S

S

S

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This year’s circuit

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8 5 Comp

1 4

270kΩ

VtriVcont

–Vcont

270kΩ

1kΩ

1.5kΩ

1.5kΩ

V(A+,A–)

–12Vfrom DC-DC chip

+12Vfrom DC-DC chip

Common (0V) from DC-DC chip

+12V

–12V

Comparator Gives V(A+,A–) wrt. Common (0V)

Vcont > Vtri

Vcont < Vtri

+24V

0V

Vcont > Vtri

Vcont < Vtri

Use V(A+,A–) wrt. –12V

Output of the Comparator Chip

Since the comparator compares signals that can be either positive or negative, the comparator must be powered by ±V supply

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8 5 Comp

1 4

270kΩ

VtriVcont

–Vcont

270kΩ

1kΩ

1.5kΩ

1.5kΩ

V(B+,B–)

–12Vfrom DC-DC chip

+12Vfrom DC-DC chip

Common (0V) from DC-DC chip

+12V

–12V

Comparator Gives V(B+,B–) wrt. Common (0V)

–Vcont > Vtri

– Vcont < Vtri

+24V

0V

– Vcont > Vtri

– Vcont < Vtri

Use V(B+,B–) wrt. –12V

Output of the Comparator Chip

Since the comparator compares signals that can be either positive or negative, the comparator must be powered by ±V supply

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This year’s circuit

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Wall wart Op amps

Notes for the above converter chip – keep the input and output sections isolated from each other. When energizing your circuit, check the +12V and −12V outputs to make sure they are OK. Low voltages indicate a short circuit in your wiring, which can burn out the chip in a few minutes.

Input Output

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Triangle wave generator

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Dual Op Amp

Dual Comparator

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Figure 9. Output of triangle-wave generator (with respect to protoboard common)

Indicates DC offset

Figure 10. Rise and fall times of the triangle wave

Equal rise and fall times

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Figure 11. Output of high-pass filter

DC offset minimized

Save screen snapshot #1

0V

+4V

−4V

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Figure 12. Output control voltages V(A+,A–) and V(B+,B–), with respect to protoboard –12V reference, with Vcont = 0 (i.e., the ma = 0 case)

Save screen snapshot #2

For ma = 0, use a

multimeter to check the following DC voltages with respect to –12V ref:

V(A+,A–) ≈ 11.8Vdc

V(B+,B–) ≈ 11.8Vdc

0V

+24V

0V

+24V

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Figure 14. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is negative)

Figure 13. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is positive)

Save screen snapshot #3

0V

+24V

0V

+24V

0V

+24V

0V

+24V

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Figure 15. Idealized Vload, with ma just into the overmodulation region

split

split Save screen snapshot #4

0V

+24V

−24V

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Figure 17. Idealized Vload observed in the scope averaging mode, with ma just into

the overmodulation region

Figure 16. Idealized Vload observed in the scope averaging mode, with ma in the

linear region

Save screen snapshot #5

0V

+24V

−24V

0V

+24V

−24V

Flat toping indicates the onset of overmodulation

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Figure 18. Idealized Vload observed in the scope averaging mode, with ma almost into

the saturation (i.e., square wave) region

0V

+24V

−24V

Approaching a square wave

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Figure 19. FFT of idealized Vload in the linear region with ma ≈ 1.0, where the

frequency span and center frequency are set to 100kHz and 50kHz, respectively

2ftri cluster (46kHz) 4ftri cluster

(92kHz) 60Hz

component