12 Embedded Processing & DSP Resource Guide 2013

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Take a look at the growth of the Internet, smartphone handsets, tablet computers, M2M, or just about any device that connects to the Internet and there are two common traits: 1. growth ranges from “up” to “really up!”; and 2. it’s the need for data exchange that is driving demand. Increasingly, this data moves wirelessly over Wi-Fi when inside a building, and over cellular when outside or trav-eling around. Wireless operators are frantically looking for ways to handle increased demand without investing in expensive wholesale buildout of their networks. One way to add more bandwidth is by intelligently handling device data requirements through DPI, compression, local routing, RF spectrum optimization, and heterogeneous cellular networks that self-organize.

According to documentation from AirHop Communica-tions, a provider of intelligent Radio Access Network (RAN) software for multi, small, and macro cell net-works: “network operators are turning to small cell base stations to increase capacity and complement existing mac-rocell networks.” The resulting ‘HetNet’ (heterogeneous net-work) requires self-organizing network (SON) technology spe-cifically designed for small cell networks to actively optimize system capacity and power, and manage inter-cell interference when so many cell sites are situated close by each other.

Analysts predict a ratio of 10:1 in favor of small cells vs tradi-tional macro cell base stations. TI claims to have captured some 50 percent of the designs for small cells, and aims to win over 70 percent of the total market. With devices like their new KeyStone TCI6612 and TCI6614, it’s understand-able why the company is so enthusiastic.

AirHop has partnered with Texas Instruments, making their eSON software available on TI’s KeyStone multi-core TMS320C66x/ARM Cortex-A8 based SOCs for small cell base stations. There are two devices – the TMS320

TCI6612 and TMS320 TCI6614 – that provide wireline to RF solutions for 3G, 4G, and LTE radio nets. The density and array of features in these devices is simply astounding, showcasing a balance of on-chip DSP, RISC CPU, packet processing, and hierarchical crossbar fabric engines. Most impressive is how optimized the chips are for making deci-sions, moving data, and autonomously handling the task at hand: making RAN SON small cells work efficiently.

Functional Block PartyTI’s small cell family consists of three devices (Figure 1), including the TCI6636 designed for up to 256 users. The system organization of the 6614 shown in Figure 2 shows a highly integrated SOC broken in several major functional blocks, all interconnected by the TeraNet fabric crossbar supporting up to 2 Tbits/s data. TeraNet is hierarchical and low latency, moving the most important data so that on-chip accelerator resources avoid starvation. As well,

power consumption is lower in idle states.

The devices are organized as: processor resources; multi-core shared memory; external memory and low-speed I/O; high speed I/O; Layer 1 and 2 Bit Rate Coprocessor (BCP)/network coprocessors. All of the onboard functional blocks, connected by the TeraNet fabric, are under the con-trol of a packet-based manager called Multicore Navigator. Navigator handles “fire and forget” communications, job management and data transfers to assure dynamic

Small Cells Connecting a Big World Require Huge IntegrationWhile Texas Instruments no longer calls itself a “DSP company”, it still leverages DSP expertise and IP to create dense, feature-packed KeyStone SOCs targeting small cell base stations.

By Chris A. Ciufo, Senior Editor

Figure 1: TI’s KeyStone small cell portfolio includes the TMS320 TCI6612/14 discussed here, plus the TCI6636 designed for high capacity small cells and “green power macro cells”. The ‘12 and ‘14 use ARM Cortex-A8 cores, while the ‘36 uses an industry-leading Cortex-A15.

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14 Embedded Processing & DSP Resource Guide 2013

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resource scheduling, load balancing, and hardware-based task prioritization. Between Navigator and TeraNet, data is designed to f low into and out of the SOC as quickly as possible with minimal latency or bottlenecks.

According to TI’s Tom Flannigan, Director of Technology Strategy, MultiCore processors: “For 2G, 2.5G, 3G and 4G standards a lot is done in hardware, not software.” That means that packet processing is done in hardware in a network pro-cessor-like way; however, unlike the often proprietary nature of NPUs, standard Eclipse-based tools are used to program the TI devices, along with the popular and expansive ecosystem available for C66x and ARM core devices.

We’ll discuss a few of the chips’ subsystems below.

KeyStone Processors - DSP and ARM Married Once AgainPerhaps no company has so successfully married DSP with ARM cores as TI, as exemplified in their handset OMAP ASSPs and SOCs. They’re again hitched together in the 6612/14 where the C66x boasts “four times the pro-cessing power of previous generations of DSPs”. The ARM Cortex-A8 (and A15 in the TCI6636) handles control plane processing with 32 KB of L1 SRAM for each C66x core. As well, there are two C66x cores in the ‘12, and four in the

‘14, with each core supported by its own 1 MB L2 memory giving a total of 4.8 GHz of DSP processing and up to 153.6 16-bit GMACs per second. And these are f loating point cores folks, churning out a whopping 76.8 GFLOPs. They also handle fixed point math, and TI claims a 5x increase over standalone fixed point solutions.

L3 SRAM memory is shared between the cores for data and for ARM program stores. The L3 multicore shared memory is under the control of a dedicated controller (MSMC) to prevent memory contention, data starvation, and arbi-trates accesses between L2, L3 and the three (in the ‘12) or five (in the ‘14) cores. The MSMC also performs another high-performance function in that it keeps memory data off of the TeraNet fabric, allowing atomic movement between the cores and freeing up the fabric for moving packet data between the rest of the peripherals. TI claims the MSMC has L3 latency that’s “nearly identical” to the local L2 memories.

Lastly, there’s a 64-bit, 1,600 MHz bus external memory interface for off-board DDR3 memory under the MSMC’s control. Because advanced 3G and 4G small cells handle loads of data, latency is kept low with this interface. The EMIF can also control 16-bit external NAND and NOR flash.

Garden Variety PeripheralsBefore we get to the really fun peripherals, it’s important to mention the more common interfaces, without which the chip wouldn’t make a very cooperative system player. Here again, TI shows off the company’s expertise in building high density SOCs. On the low-speed side, there’s I2C, SPI and twin UARTs. There’s also a 32-pin GPIO port with programmable interrupts fired from key events. On the high-speed side are four serial RapidIO lanes at 5 Gbits/s, PCI Express (two lanes, GEN1 and GEN2), and the obligatory Gigabit Ethernet ports (two). Since getting data between the Ethernet backbone and the air interface is the IC’s primary function, additional on-chip accelerators speed network data handling functions.

There are two Ethernet media access controllers to pipeline data between the PHY and the DSP cores. This is partly handled by a data I/O module that continuously polls all 32 addresses “in order to enumerate all PHY devices in the system”. A packet processor can classify Layer 2 to Layer 4 data at up to 1.5 Gbits/s, while an embedded security accelerator works at 1 Gbits/s (wire speed) performing IPSec, SRTP, and 3GPP air interface security protocols.

TI also includes HyperLink and AIF2 ports. The former is the proprietary 12.5 Gbaud/lane inter-processor backbone used to connect multiple SOCs together. The low protocol/high rate link between TI KeyStone devices allows scalable small cell solutions with MultiCore Navigator software

Figure 2: Block diagram of the TCI6612 and TCI6614. The ‘12 has two C66x cores whereas the ‘14 has four.

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16 Embedded Processing & DSP Resource Guide 2013

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dispatching tasks to multiple devices which appear as local resources in a multiprocessing fashion.

The AIF2 interface is a peripheral module used for trans-ferring baseband IQ data between baseband DSPs and a

high-speed serial interface. On the ‘12 and ‘14, the AIF2 second-generation SERDES-based antenna interface is capable of up to 6.144 Gbits/s per link, and there are six links available. AIF2 supports OBSAI RP3 and CPRI pro-tocols for the following RF standards: WCDMA/FDD, LTE (FDD and TDD), WiMax, TD-SCDMA, and GSM/Edge. AIF2 connects externally to either RF units or other baseband devices. The AIF2 interface is so important that it has its own 433 page manual, separate from the rest of the chip.

Not So Garden Variety PeripheralsWhile the “garden variety” peripherals are impressive, even more so are the accelerators and co-processors TI packs into the twin devices. Designed for bit rate pro-cessing that avoids disturbing the DSP cores, they are

lumped together into the bit rate coprocessor (BCP) block shown in Figure 2 as “Layer 1” and “Layer 2”. The BCP’s top-level functions are shown in Figure 3 which includes a CRC engine, turbo interference cancellation for MIMO equalization - a critical function of small cell base stations - and various mod/demodulators and interleaver/deinterleavers.

Collectively, the configurable accelerators and co-processors maximize f low-through system performance while also reducing base station complexity through single chip operation. For example, there’s no need to implement in off-board FPGAs FFT or DFT transforms, Viterbi decoders, or LTE decode logic. Some typical performance numbers are shown in Figure 4.

SummaryAs on-the-go Internet traffic increases through data transfers, there’s an acute need for small cell base stations. These offload macro cells by cost effectively adding users, bridging wireless standards, and increasing coverage. Seizing the market with high-inte-gration, high intelligence peripherals, Texas Instruments’ TMS320TCI6612/14 SOCs offer barn-burning performance without con-suming much power. Taking advantage of all on-board resources, TI quotes small cell base station power levels at 26mW per Mbits/s of data transferred. That’s a tidy way to connect a big world’s huge demand for wireless data, one cell site at a time.

Chris A. Ciufo is senior editor for embed-ded content at Extension Media, which includes the EECatalog print and digital publications and website, Embedded

Intel® Solutions, and other related blogs and embed-ded channels. He has 29 years of embedded technology experience split between the semiconductor industry (AMD, Sharp Mi-croelectronics) and the defense industry (VISTA Controls and Dy4 Systems), and in content creation. He co-founded and ran COTS Jour-nal, created and ran Military Embedded Systems, and most recently oversaw the Embedded franchise at UBM Electronics. He’s considered the foremost expert on critically applying COTS to the military and aero-space industries, and is a sought-after speaker at tech conferences. He has degrees in electrical engineering, and in materials science, emphasiz-ing solid state physics. He can be reached at cciufo@extensionmedia.com.

Figure 3: The on-board bit-rate coprocessor (BCP) is designed to move and process data through the chips without burdening the DSP cores. As such, the BCP includes Layer 1 and Layer 2 processing engines tied together via the TeraNet fabric.

Figure 4: On-board coprocessors and accelerators, coupled with the TCI6612/14’s flow-through architecture, returns impressive performance numbers for typical small cell operations. TI’s goal was to build an SOC needing no external FPGA or ASIC.