Architecture of tms320 f2812

Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.

Digital Signal Controller TMS320F2812

Chapter 1 : Architecture


C281x Block Diagram

32x32 bit32x32 bitMultiplierMultiplier


SectoredSectoredFlashFlash

SectoredSectoredFlashFlash

A(18-0)A(18-0)

D(15-0)D(15-0)

Program BusProgram Bus

Data BusData Bus

RAMRAMRAMRAMBootBootROMROM

BootBootROMROM

2222

32-bit32-bitAuxiliaryAuxiliaryRegistersRegisters


3332 bit 32 bit

Timers Timers

3332 bit 32 bit

Timers Timers RealtimeRealtimeJTAGJTAG

RealtimeRealtimeJTAGJTAG

CPUCPU

Register BusRegister Bus

R-M-WR-M-WAtomicAtomicALUALU


PIE PIE Interrupt Interrupt ManagerManager

3232

3232

3232

EventEventManager AManager A

EventEventManager AManager A

EventEventManager BManager B

EventEventManager BManager B

12-bit ADC12-bit ADC12-bit ADC12-bit ADC

WatchdogWatchdogWatchdogWatchdog

McBSPMcBSPMcBSPMcBSP

CAN2.0BCAN2.0BCAN2.0BCAN2.0B

SCI-ASCI-ASCI-ASCI-A

SCI-BSCI-BSCI-BSCI-B

SPISPISPISPI

GPIOGPIOGPIOGPIO


C28x CPU

32-bit fixed-point DSP 32 x 32 bit fixed-point MAC Dual 16 x 16 single-cycle fixed-point

MAC (DMAC) 32-/64-bit saturation 64/32 and 32/32 modulus division Fast interrupt service time Single cycle read-modify-write

instructions Unique real-time debugging

capabilities Upward code compatibility

Data BusData Bus



3332 bit 32 bit

Timers Timers

3332 bit 32 bit

Timers Timers RealtimeRealtime

JTAGJTAG

RealtimeRealtimeJTAGJTAG CPUCPU

Register BusRegister Bus



Program BusProgram Bus

MCU/DSP balancing code density & execution time. Supports 32-bit instructions for

improved execution time; Supports 16-bit instructions for

improved code efficiency

PIE PIE Interrupt Interrupt ManagerManager32x32 bit32x32 bit

MultiplierMultiplier



XT (32) or T/TLXT (32) or T/TL

MULTIPLIER MULTIPLIER 32 x 32 or 32 x 32 or

Dual 16 x 16Dual 16 x 16

P (32) or PH/PLP (32) or PH/PL

AH (16)AH (16)

C28x Multiplier and ALU / Shifters

Data Bus

Data Bus

Program Bus

ALU (32)ALU (32)

3232

3232

3232

3232

3232

AL (16)AL (16)

3232

3232

••

16/3216/32

8/168/16

Shift R/L (0-16)Shift R/L (0-16)

ACC (32)ACC (32)

AH.MSB AH.LSBAH.MSB AH.LSB AL.MSB AL.LSBAL.MSB AL.LSB

3232


3232


3232

1616 8/16/328/16/32


C28x Pointer, DP and Memory

XAR0XAR0XAR1XAR1

XAR2XAR2XAR3XAR3XAR4XAR4XAR5XAR5

XAR6XAR6XAR7XAR7

ARAUARAU

MUXMUX

Data MemoryData Memory

MUXMUX

DP (16)DP (16)

Data Bus

Program Bus

6 LSB6 LSBfrom IR IR

XARn 32-bitsARn 16-bits

22223232


C28x Internal Bus Structure

Data-write Address Bus (32)Data-write Address Bus (32)

Program Address Bus (22)Program Address Bus (22)

ExecutionExecution


Real-TimeReal-TimeEmulationEmulation

&&TestTest

EngineEngine

Program-read Data Bus (32)Program-read Data Bus (32)

JTAG JTAG

ProgramProgram

DecoderDecoder

PCPC

XAR0XAR0toto

XAR7XAR7

SPSP

DPDP @X@X

ARAUARAU MPY32x32MPY32x32

XTXTPP

ACCACC

ALUALU

RegistersRegisters DebugDebug

Register Bus / Result BusRegister Bus / Result Bus

Data/Program-write Data Bus (32)Data/Program-write Data Bus (32)

Data-read Address Bus (32)Data-read Address Bus (32)

Data-read Data Bus (32)Data-read Data Bus (32)

Memory

Data (4G * 16)

Program(4M* 16)

StandardPeripherals

ExternalInterfaces


C28x Atomic Read/Modify/Write

Registers ALU / MPY

LOAD

STORE

WRITE

READ

CPU Mem

Atomic Instructions Benefits:

Simpler programming

Smaller, faster code

Uninterruptible (Atomic)

More efficient compiler

AND *XAR2,#1234h

2 words / 1 cycles

Atomic Read/Modify/Write

MOV AL,*XAR2AND AL,#1234hMOV *XAR2,AL

DINT EINT

6 words / 6 cycles6 words / 6 cycles

Standard Load/Store


FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

C28x Pipeline

Protected Pipeline

Order of results are as written in source code

Programmer need not worry about the pipeline

8-stage pipelineFF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

FF1 1 F F2 2 DD1 1 DD2 2 RR1 1 RR2 2 XX

AABBCC

DDEEFFGG

WW

WW

WW

WW

WW

WW

WW

WW

E & G Accesssame address

RR1 1 RR2 2 XX WW

DD2 2 R R1 1 RR2 2 X WX W

F1: Instruction AddressF2: Instruction ContentD1: Decode InstructionD2: Resolve Operand AddrR1: Operand AddressR2: Get OperandX: CPU doing “real” workW: store content to memory

HH


TMS320F2812 Memory MapMO SARAM (1K)MO SARAM (1K)

M1 SARAM (1K)M1 SARAM (1K)

LO SARAM (4K)LO SARAM (4K)

L1 SARAM (4K)L1 SARAM (4K)

HO SARAM (8K)HO SARAM (8K)

Boot ROM (4K)Boot ROM (4K)MP/MC=0MP/MC=0

BROM vector (32)BROM vector (32)MP/MC=0 ENPIE=0MP/MC=0 ENPIE=0

OTP (1K)OTP (1K)

FLASH (128K)FLASH (128K)

reserved

reserved

reservedPF 0 (2K)PF 0 (2K)

reserved

reservedPF 1 (4K)PF 1 (4K)reservedPF 2 (4K)PF 2 (4K)

reservedPIE vectorPIE vector(256)(256)ENPIE=1ENPIE=1

XINT Zone 0 (8K)XINT Zone 1 (8K)

XINT Zone 2 (0.5M)XINT Zone 6 (0.5M)

XINT Zone 7 (16K)MP/MC=1

XINT Vector-RAM (32)MP/MC=1 ENPIE=0

reserved

reserved

reserved

Data | ProgramData | Program

0x00 00000x00 0000

0x00 04000x00 0400

0x00 08000x00 08000x00 0D000x00 0D00

0x00 10000x00 10000x00 60000x00 60000x00 70000x00 70000x00 80000x00 8000

0x00 90000x00 9000

0x00 A0000x00 A0000x3D 78000x3D 7800

0x3D 80000x3D 8000

0x3F 80000x3F 8000

0x3F A0000x3F A0000x3F F0000x3F F000

0x3F FFC00x3F FFC0

0x3F C0000x3F C000

0x18 00000x18 0000

0x10 00000x10 00000x08 00000x08 0000

0x00 40000x00 40000x00 20000x00 2000

Data | ProgramData | Program

128-Bit Password128-Bit Password

CSM: LO, L1CSM: LO, L1OTP, FLASHOTP, FLASH

reserved0x3D 7C000x3D 7C00


Code Security Module• Prevents reverse engineering and protects valuable intellectual

property

• 128-bit user defined password is stored in Flash• 128-bits = 2128 = 3.4 x 1038 possible passwords• To try 1 password every 2 cycles at 150 MHz, it would take at

least 1.4 x 1023 years to try all possible combinations!

LO SARAM (4K)LO SARAM (4K)

L1 SARAM (4K)L1 SARAM (4K)

OTP (1K)OTP (1K)

FLASH (128K)FLASH (128K)

reserved

0x00 80000x00 8000

0x00 90000x00 9000

0x00 A0000x00 A0000x3D 78000x3D 7800

0x3D 80000x3D 8000

128-Bit Password128-Bit Password

reserved0x3D 7C000x3D 7C00


C28x Fast Interrupt Response Manager 96 dedicated PIE vectors No software decision

making required Direct access to RAM

vectors Auto flags update Concurrent auto context

save

28x CPU Interrupt logic

28xCPUINTMINTMIFRIFR IERIER

96 96 P

erip

hera

l Int

erru

pts

12x

8 =

96

12 interrupts12 interrupts

INT1 to INT1 to

INT12INT12

PIERegister

Map

PIE module For 96 interrupts

T ST0AH AL

PH PLAR1 (L) AR0 (L)DP ST1DBSTAT IERPC(msw) PC(lsw)

Auto Context Save


C28x / C24x Modes

C24x Mode 1 1 1 1

C28x Mode 1 1 0 0

Test Mode (default) 0 0 0 0

Reserved 0 0 1 1

OBJMODE AMODEMode Bits Compiler

OptionMode Type

C24x source-compatible mode: Allows you to run C24x source code which has been reassembled using the

C28x code generation tools (need new vectors) C28x mode:

Can take advantage of all the C28x native features

--v28

-v28 -m20

-v27


Reset – BootloaderReset

OBJMODE=0 AMODE=0ENPIE=0 VMAP=1

Boot determined by Boot determined by state of GPIO pinsstate of GPIO pins

Reset vector fetched from boot ROM0x3F FFC0

XMPNMC=0(microcomputer mode)

ExecutionEntry PointH0 SARAM

Note:Details of the various boot options will be discussed in the Reset and Interrupts module

Bootloader sets

OBJMODE = 1AMODE = 0


Summary

• High performance 32-bit DSP• 32 x 32 bit or dual 16 x 16 bit MAC• Atomic read-modify-write instructions• 8-stage fully protected pipeline• Fast interrupt response manager• 128Kw on-chip flash memory• Code security module (CSM)• Two event managers• 12-bit ADC module• 56 shared GPIO pins• Watchdog timer• Communications peripherals

Education

Architecture of tms320 f2812