Efficient addressing scheme for sequentiallyaccessed serial highways

D S Fenna, B.Sc, Ph.D., M. Inst. M.C.,

Indexing terms: Digital control, Digital instrumentation

Abstract: It is now common practice in industrial applications of digital electronics for plant interface unitsto be geographically distributed and connected to a central point by a time-division multiplexed serial link.As in all such links, some means must be provided for each interface unit to send or accept data only in itsallotted time, and the paper describes an arrangement which minimises the time consumed by this addressingfunction without sacrificing reliability in noisy environments. It entails the central station sending one bit ofaddress information in each unit's time slot, in such a way that the current rc-bit address is formed by the nmost recently received address bits. Each unit can verify this process. The method is suitable for applications,in which many remote units are scanned sequentially to exchange data with a central station; for example, indatalogging.

1 Introduction

When a digital datalogging or control system is installed in a largeplant, the electrical connections between the plant and thecomputer (or logger) consititute a very significant part of theinstalled cost of the system. In order to reduce these costs, it isnow normal practice to use small interface units located closeto the plant transducers, and these communicate with thecomputer via a parallel-connected data highway. The computercontrols the highway system so that each interface unit sendsor receives data only in its allocated time slot, Fig. 1. As afurther step in minimising cost, this highway usually consistsof a single conductor pair, and all signals are in time-•multiplexed serial form.

D— —a

transducers

multiplexer

controller

Fig. 1 Typical industrial data-highway system

The continuing fall in the cost of digital electronicscomponents has led to similar techniques being used insystems which do not involve a computer, and installations

Paper 2087E, first received 16th October 1981 and in revised form14th May 1982The author is with the Department of Electrical, Instrumentation &Control Engineering, Teesside Polytechnic, Middlesborough, ClevelandTSl 3BA, England

with large numbers of indicator lights or digital displays oncontrol desks or mimic diagrams can now benefit from usingmultiplexed highways instead of individual wiring. Aninexpensive 2-wire circuit can gather data for a thousand ormore indicators. In these applications, it is necessary tocontrol the highway system so that the interface units arescanned sequentially, so a controller must be provided whichsends signals over the highway to all units, and each unituses this information in conjunction with its individuallyassigned address to identify its own time slot. It is thearrangement of these addressing signals which is examined inthis paper.

2 Terminology

A variety of terms are used to denote the various componentsof a serial data stream; the following are used here.

The period during which every unit on the system transmitsor receives its data (in turn) is a 'scan'. If the scanningsequence is controlled by a signal which occurs only once perscan (see Section 3), this is a 'synchronising (sync.) signal'.

The basic data to be transmitted from or to one interfaceunit ('unit') is a 'data byte', and to this may be addedadditional bits for addressing and bit-synchronisation to forma 'word'. All words would normally be the same size.

The system capacity is N units, and each scan comprisesonly N words and possibly a sync, signal. Symbol n denotesthe smallest integer, such that 2n >N, i.e. the smallest numberof address bits required to assign a unique address to each unit.

3 Synchronisation levels

It is not possible to construct two or more electronicoscillators having exactly the same frequency at all times, sopart of the highway specification must allow for differences inoscillator frequencies in each unit to be corrected oraccommodated. This is bit synchronisation.

The sequence of bits on a serial highway contains data toand from various destinations and the significance of any givenbit depends on its position within the sequence. It is thereforenecessary in a distributed system for each unit to recognise thestart of a word and the start of a scan. If bit synchronisation isoperating correctly, then it should only be necessary to forceword and scan synchronisation once, when the system ispowered up. In practice, however, it is normal to forcesynchronisation at regular intervals, in case one unit is upsetby a local disturbance, or the whole system is corrupted byimpulsive noise etc. This requires extra information to betransmitted over the highway, and so the interval at which this

IEEPROC, Vol. 129, Pt. E, No. 6, NOVEMBER 1982 0143-7062/82/060235 + 04 $01.50/0 235

is done is a matter for compromise, taking into account suchfactors as the likelihood of corruption, the consequence oferrors, and the net data-transmission speed (scans per second).Methods for bit and word synchronisation are well known andare therefore not discussed here [1 ] .

4 Scan synchronisation

The usual arrangements for ensuring scan synchronisation fallinto one of three clases:

(i) A particular data word is reserved for synchronisation; itis never sent as data, only by the controller. Each I/O unitcounts words from this sync signal.

(ii) An extra bit is added to each word, which is set to 1 forthe first word in each scan and to 0 for the other words.

(iii) A sync signal is sent by electrically separate means,such as a pulse of a different voltage. Again, each I/O unitcounts words from this.

These are illustrated in Fig. 2.

I synch , data 1 | D2 | D3 | | data N| synch |D1~_TLn_rLrn i~ _~ _~ _ ~_ ~_ r _~ _~_ ~ j _ _"_• ~ j i . rLn_ro c :

(i)

dataN data 1 I D2 I D3 I i I data N I data 1

rj P_"> 1 1 iiruiL L c u r u i L . " U T U J . " | _TTLTL"_Z Z< T~u<ssrvsynch bit '

(ii)dataNlsldatai I D2 | D3 | DA i |data N-1idata N "s"Dl

ZLG p u r_Ti r_ T . _ " . T L ~_-_-L~i I J~_~U~_ U G p u "~usynch pulse ' "-•

(iii)Fig. 2 Three types of scan-synchronisation scheme

Alternatively, the complete address of the next unit may besent in every word. The system then has random-accesscapability and there is a very high degree of redundancy ifsequential access is used. Some of the redundant informationcan be used for checking the received address, but it is stillvery inefficient.

A serious drawback to method (i) is that it imposes arestriction on the 'user' data which can be transmitted by thesystem.

The use of a separate electrical signal, as in (iii), is inessence changing a binary system to ternary, a facility whichcould be better utilised to increase the capacity or noiseimmunity of the system.

With all these methods, synchronisation occurs only onceper scan, and hence any corruption in transmission of thesynchronising signal cannot easily be detected and will causeerrors throughout the next scan. The method now to bedescribed overcomes many of these disadvantages; it is anextension of method (ii).

5 New method

The new method uses the principle of so-called m-sequences,also known as pseudorandom binary sequences. These aresequences of bits which can easily be generated using an «-bitshift register and exclusive-OR gates, and have the propertythat the binary number created by taking blocks of n adjacentbits takes on all possible values of 1 to N = 2" — 1, see Fig.3, then repeats after N bits.

This can be utilised in multiplexer addressing as follows.The controller transmits one address bit during each word, andthese are stored by every unit in an «-bit shift register. Theseaddress bits are generated in the controller as an m-sequence.Each unit compares the shift register contents with its ownfixed address and becomes active when they agree, Fig. 4.

These shift register contents comprise the blocks of n bitsillustrated in Fig. 3, so each unit will be active for just oneword in every N.

The operation of the system is illustrated in Fig. 5. Eachword contains bit and word synchronising bits (generated bythe controller according to the bit/word synchronising schemein use), and data bits generated by the particular transmitterunit relevant to that word.

There is now an additional bit in each word, generated bythe controller. At the appropriate time in each word, everyunit shifts a register so that the content of these registers atany time is equal to the last n address bits received. Theseaddress bits are generated in the controller by a shift registerclocked at the same rate of once per word, so the effect of thehighway link is to produce in every remote unit a copy of thecontroller's register contents.

This latter shift register could be connected in a variety offeedback arrangements to operate as a counter, and the countsequence would appear in each remote unit as an addressingsequence. One possibility is the Johnson (twisted ring) config-uration, but this produces only 2n states in an w-bit register.

sequence repeats

__J ! ! !_-.1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0

Fig. 3 Occurrence ofmultibit numbers in an m-sequence

controller

address bit_TDM gate

highway

address bitstrobe

SIshift reg

comparatofc

plantsignals

remote unit

address links-

Fig. 4 General arrangement of new scheme

highwaywaveformJi

1word data bits and address bits

-time

Fig. 5 Operation of addressing scheme for n = 3, N = 7x initial or erroneous states

236 IEEPROC, Vol. 129, Pt. E, No. 6, NOVEMBER 1982

The m-sequence arrangement is near optimal, in that it issimple to construct and has 2n — 1 different states; with asmall modification all 2n states can be included [2].

It can be seen from Fig. 5 that the initial state of the shiftregister in each remote unit affects only the first n words,since there is no feedback. If synchronisation is lost, or thereare transmission errors resulting in the register taking up somearbitrary erroneous state, these errors will be shifted out asthe first n correct address bits are received and synchronisationwill then be restored.This method has the advantages that:

(a) The time used by the addressing scheme is only one bitper word, for any size of system.

(b) If any unit is out of step, it will be corrected within nwords (after word synchronisation is restored).

(c) Received address bits can be predicted, and hence easilyverified, by every unit.

(d) An address bit which is corrupted in transmission willaffect only the next n words.

Note that the remote units are not activated in numericalorder of addresses. The order of accessing is not usuallyimportant, but if it were, the actual order may be deter-mined from the m-sequence as in Fig. 5, and addresses assignedaccordingly.

6 Error detection

As stated above, the address registers in the remote unitscontain a copy of that in the controller. It is therefore possiblefor each remote unit to predict the next address bit, if it isfitted with the same feedback configuration as the controller.

This feedback signal predicts the next bit from the control-ler and, if they do not agree, it must be assumed that the

current contents of the address register are wrong, see Fig.6a. This information can be used to inhibit the activation ofthe unit, until n correct address bits have been received.

In practice the signal connected to the input of the slaveregister would normally be the full multiplexed highwaysignal, since its value is ignored except at the times of theregister clock pulse, so this could not be used for comparisonpurposes. However, the addition of an extra stage as in Fig.6b removes this problem; it also allows the two registers tobe clocked at different times.

7 Generation of sequences

The generation of w-sequences using one ex-or gate asdepicted in Fig. 3 is outlined in many texts on digital datatransmission systems. Sequences of different length can beobtained by ex-or'ing the outputs from various stages, as listedin Table 1.

Table 1: Connections for m-sequence generator

n23456789

101112

N37

153163

127255512

102320474095

Feedback stages1,22.33,43,55,66,74,5,6.85,97.109,116,8, 11, 12

M

i•

IH

Data for longer sequences available in Reference 4

clock II

master master

elk

H

TDM gate

TDM highway

clko

slave slave

Fig. 6 Error detection arrangement

a Principle, b Practice

IEEPROC, Vol. 129, Pt. E, No. 6, NOVEMBER 1982 237

It is important to note that the sequence will not start ifthe register contains all zeros. This condition can be correctedby detecting the all-zero state; either explicity, using anw-input NOR gate, or implicity by using a watchdog arrange-ment on the output [3].

The problem can be alleviated completely by using themodification suggested by Smith and Ward [2], so that thereis no invalid state, but this requires an extra integrated circuitin the error-checking logic of every remote unit, whichincreases the system cost unnecessarily.

8 Conclusions

A method has been described by which sequentially accessedhighway systems may be synchronised. Its usefulness lies in itsbeing a compromise between the two schemes widelyused at present, since it does not require so much time as

signalling a full address with every word, but it does providethe ability to resynchronise after only n words rather thanonce per scan. It has also the great advantage that the addressinformation received by field units can be verified, so theiroperation may be suspended if there are errors in the trans-mission of address information.

These benefits are achieved with no significant increase inhardware cost.

9 References

1 BYLANSKI, P. and INGRAM, D.G.W.: 'Digital transmissionsystems' (Peter Perigrinus, 1976)

2 SMITH, D.T., and WARD, J.C.: 'A pseudo-random pulse-traingenerator', Electron. Eng., 1977, 48, pp. 21-23

3 HORTON, D.: 'Simple self-starter for PRBS generators', ElectronProd.Des., 1981, 2, (7), p. 29

4 LANCASTER, D.: 'CMOS Cookbook'

Contents of Software & MicrosystemsThe contents are given below of the October 1982 issue of Software & Microsystems.

Some experiences of implementing theAda concurrency facilities on adistributed multiprocessor computersystem. G.C. Shoja, F. Halsall andProf. R.L. Grimsdale

A technique for interrupt distribution ina multiprocessor system. A. Cantoni

Design and performance of a simple nucleusfor real-time control applications. H.W. Thomas

University microsProjects at University College London

Conference reportHuman factors in computer systems

238 IEEPROC, Vol. 129, Pt. E, No. 6, NOVEMBER 1982