Efficient Test Pattern Generation Scheme Chip BIST · 2019. 8. 1. · 554 B. K. S. V. L. VARAPRASADet al. using external patterns to test. Evenmoreappeal- ingis a techniquewherethe

VLSI DESIGN2001, Vol. 12, No. 4, pp. 551-562Reprints available directly from the publisherPhotocopying permitted by license only

(C) 2001 OPA (Overseas Publishers Association) N.V.Published by license under

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An Efficient Test Pattern GenerationScheme for an On Chip BISTB. K. S. V. L. VARAPRASADa’*, L. M. PATNAIKc’t,

H. S. JAMADAGNI’i’* and V. K. AGRAWALb’

aMicro Electronics Design Facility, bControl Systems Group, ISRO Satellite Centre, Bangalore, India 560 017,"CMicroprocessor Applications Laboratory, Department of Computer Science and Automation,

aCentre for Electronics Design and Technology, Indian Institute of Science, Bangalore, India 560 012

(Received 15 August 1999; In finalform 11 September 2000)

Testing and power consumption are becoming two critical issues in VLSI design due tothe growing complexity of VLSI circuits and remarkable success and growth of lowpower applications (viz. portable consumer electronics and space applications). On chipBuilt In Self Test (BIST) is a cost-effective test methodology for highly complex VLSIdevices like Systems On Chip. This paper deals with cost-effective Test Pattern Gene-ration (TPG) schemes in BIST. We present a novel methodology based on the use ofa suitable Linear Feedback Shift Register (LFSR) which cycles through the requiredsequences (test vectors) aiming at a desired fault coverage causing minimum circuittoggling and hence low power consumption while testing. The proposed technique usescircuit simulation data for modeling. We show how to identify the LFSR using graphtheory techniques and compute its feedback coefficients (i.e., its characteristicpolynomial) for realization of a Test Pattern Generator.

Keywords: Design For Testability (DFT); Built In Self Test (BIST); Test Pattern Generator (TPG);Linear Feedback Shift Register (LFSR)

1. INTRODUCTION

Performance, area, power and testing are some ofthe most important attributes of complex VLSIsystems. With the current reduction in device sizes,it is becoming possible to fit increasingly larger

devices onto a single chip or wafer. As chip densityincreases, the probability of defects occurring in a

chip increases as well. The quality, reliability andcost of the product are directly proportional to thedegree of testing of the product. Over the time, thefocus on testing of Integrated Circuits (ICs) has

* Fax: 91 -80-5266099, e-mail: [email protected] author. Fax: 91 -80-3341683, e-mail: [email protected]: 91 -80-3341808, e-mail: [email protected]: 91 -80-5082321, e-mail: [email protected]

551

552 B. K. S. V. L. VARAPRASAD et al.

shifted from the final fabricated ICs to the designstage. In this context, many Design For Testability(DFT) techniques have been developed to easetesting of circuits [1]. The testability of a circuitcan be increased with DFT. Testing of the circuitinvolves the generation of test patterns for thecircuit, application of these test patterns to thecircuit and analysis of the output response ofthe circuit. To get the maximum fault coverage ofthe circuit, one of the simplest approaches is toapply the exhaustive test patterns to the circuit.Many test pattern generation methods like, Ran-dom Pattern Testing, Pseudorandom Testing andPseudo-Exhaustive Testing have been developed[2, 3] aiming to reduce the pattern length withoutcompromising the fault coverage. Built In SelfTest (BIST) is a suitable test methodology forhighly complex VLSI devices like systems on a

chip. Minimization of circuit area and delay hasbeen the main objective in VLSI design for manyyears. However, low power consumption hasrecently emerged as another important designobjective. Often circuit designers try to reducethe power consumption of a circuit at the cost ofincreasing the area and delay of the circuit. Powerdissipation in CMOS circuits is dominated by thedynamic component [4] which is incurred when-ever signals in the circuit undergo a logictransition. One of the several important factorsaffect-ing power consumption is the choice ofcircuit technique for logic drivers, latches and flip-flops. A good understanding of how the powerconsumption occurs in the circuits is essential todesign more efficient circuits which consume lesspower. One method reported [5] suggests to switchoff the power to the test area to reduce the powerduring normal operation of the circuit. Howeverthis does not look into the power consumption ofthe test area during testing. In this paper, a methodis proposed by which the power consumptionduring testing is minimized.The paper is organized as follows. Section 2

describes the power consumption in CMOScircuits. Section 3 describes problems faced intesting and methods to reduce them. Section 4gives a description of the methods used to generate

test patterns. Section 5 gives the simulation resultson three circuits to study the behavior of the faultcoverage, transitions in the logic of the internalnodes and capacitance switching in the circuit forvarious LFSR sequences. Based on the simulationresults, a method to compute the characteristicpolynomial which gives maximum fault coveragewith minimum transitions and capacitance switch-ing is explained in Section 6. Section 7 summarizesthe salient features suggested in this paper toreduce the power consumption in the BIST imple-mentation while testing.

2. POWER CONSUMPTIONIN CMOS CIRCUITS

The power consumption of digital CMOS circuitsis normally divided into three parts, short circuitpower Psc, static power Ps and dynamic powerPd [4].

2.1. Short-circuit Power Consumption

When a static CMOS gate is switched by an inputsignal with a non-zero rise or fall time, bothn-channel and p-channel transistors conductsimultaneously for a short time. During this time,there will be a "short-circuit current", flowingdirectly between Vdd and ground.

2.2. Static Power Consumption

Static power consumption in CMOS circuits iscaused by leakage currents of transistors and pn-junctions.

2.3. Dynamic Power Consumption

Dynamic power consumption is related to a nodecapacitor which is charged and discharged. Theaverage dynamic power dissipation in the circuitis given by,

2n

Pavg fclk(Vdd) Cload(g) T(g) (1)g=l

TEST PATTERN GENERATOR 553

where folk is the clock frequency, Vdd is the supplyvoltage, Cload(g is the load capacitance of gate g,and T(g) is the average number of transitions atgate g per clock cycle.The total power consumption P of the circuit is

given by,

P Psc + Ps + Pd (2)

Dynamic power consumption normally dominatesstatic power consumption and short circuit powerconsumption. It may range from 80% to 85% ofthe total circuit power consumption. Once theoperating frequency of the circuit fclk is fixed,the parameter which can be optimized to reducethe average dynamic power consumption is

Cload(g)’T(g). In this paper a method to reducethis switching factor for reduction of the dynamicpower dissipation in the circuit during testing isproposed.

3. TESTING

Testing falls into a number of categories dependingupon the intended goal. The diagnostic test is usedduring the debugging of a chip or board and tries toidentify and locate the fault in a failing chip orboard. The functional test (also called go/no go test)determines whether or not a manufactured compo-nent is functional. This problem is simpler than thediagnostics test since the analysis and debugging isnot involved in this test. Since this test is to beexecuted on every manufactured die and has adirect impact on the cost (viz., test equipment cost,testing time), it should be as simple and swift aspossible. The parametric test checks on a numberof nondiscrete parameters, such as noise margin,propagation delays and maximum clock frequen-cies, under a variety ofworking conditions, such astemperature and supply voltage.

patterns to its inputs. For an N-input circuit,this requires the application of 2N patterns. In a

sequential circuit, the output of the circuit dependsnot only on the inputs applied, but also on thevalue of the state of the internal registers of thecircuit. An exhaustive test of this finite statemachine requires the application of 2N+M testpatterns, where M and N are the number ofregisters/flip-flops and inputs of the circuit respec-tively. As N and M increase, the test lengthexpands exponentially. To reduce the test patternlength an alternate approach is required.By eliminating redundancy and providing a

reduced fault coverage, it is possible to test mostcombinational logic blocks with a limited set ofinput vectors. To test a given fault in a sequentialcircuit, the circuit must first be brought to thedesired state/initial state before applying the inputexcitation. One approach adopted in scan test, is toconvert the sequential circuit into a combinationalone by breaking the feedback loop during the test.

Testability of the circuit, depends on the con-trollability and observability of the internal nodesof the circuit [6]. Combinational circuits fall underthe class of easily observable and controllablecircuits, since any node can be controlled and ob-served in a single cycle. Design For Testability(DFT) [1] is the design effort through which adesign can be made an easily testable design by en-

hancing the controllability and observability. DFTis used to reduce test generation costs, enhance thequality of the tests and hence reduce defect levels.The DFT strategy contains two components:

(1) Provide the necessary circuitry so that the testprocedure can be swift and comprehensive.

(2) Provide the necessary test patterns (excitationvectors) to be employed during the testprocedure. For reasons of cost, it is desirablethat the test sequence be as short as possiblewhile covering the majority of possible faults.

3.1. Some of the Intricaciesof the Test Problem

The functionality of a combinational circuit can beverified by exhaustively applying all possible input

3.2. Built-in-self-test(BIST)

An attractive approach to testability is having thecircuit itself generate the test patterns instead of


using external patterns to test. Even more appeal-ing is a technique where the circuit itself decides ifthe obtained results are correct. Depending uponthe nature of a circuit, this might require theaddition of extra circuitry for the generation andanalysis of the patterns.BIST [7] schemes provide advantages such as

at-speed testing, easy reuse of the built-in teststructure for diagnosis and repair. One salientfeature of BIST that makes it stand out in designand test of VLSI is using a divide-and-conquerapproach in which every block has its ownembedded BIST structure and is controlled by a

chip-wide BIST controller. An ideal BIST schemeachieves not only very high fault coverage withminimum area overhead, low or zero performancedegradation and minimum test time but also haslow power consumption while testing.

4. TEST PATTERN GENERATION(TPG) SCHEMES

There are many ways to generate and apply stimulifor the Circuit Under Test. Most widely usedstimuli are the exhaustive, pseudo-exhaustive andrandom [2,3] approaches. In the exhaustive ap-proach, the test length is 2N, where N is thenumber of inputs to the circuit. The exhaustivenature of the test means that all detectable faultswill be detected, given the space of the availableinput signals. An N-bit counter is a good exampleof an exhaustive pattern generator. However as Nincreases the testing time increases exponentially.Normally in a system with N input variables, everyfunction may depend only on a subset ofM inputs.Then the test pattern set which contains 2M vectorsgives the same degree of confidence in a system asif it is tested with all 2TM vectors since each func-tion in the circuit is tested exhaustively [3]. Asmentioned earlier, the testing time can be reducedby shrinking the test pattern sequence. Many testgeneration algorithms and methods like PODEM,FAN and TOPS have been developed [1]. Analternate approach is to use random patterns to

get maximum fault coverage with minimum testtime.

Various types of test generation procedures forsynchronous sequential circuits described at thegate level have been developed. Some of these aredeterministic branch and bound techniques [1] andare successful in achieving high fault coveragewith high computational complexity and others arebased on genetic optimization procedures [8]. Atest generation scheme MIX reported in [9] com-bines several test generation approaches to derivetest sequences exhibiting very high fault coverageat relatively low CPU times. Using any of theabove methods, an effective set of ’k’ test vectors(patterns) can be identified. These ’k’ patterns canbe applied to the CUT in the following ways.

The ’k’ patterns can be stored in a lookup table(ROM) and addressed by a counter.By designing a logic circuit for the ’k’ patternsusing counter design techniques.By designing a suitable Cellular Automata.By choosing a suitable LFSR which can cyclethrough the minimum patterns in which all ’k’patterns are included.

The efficiency of the method is evaluated interms of fault coverage, test application time,power consumption, area overhead, performancepenalty/degradation and computational time toarrive at a particular solution.

5. SIMULATION STUDIESOF AN LFSR AS A TPG

Autonomous circuits such as Linear FeedbackShift Registers (LFSR) [1] are used as low-cost-testpattern generators for circuits testable by pseudo-random patterns. An LFSR with different feed-back coefficients (characteristic polynomials)started with different initial seeds may yieldsignificantly different pattern lengths. When thesepatterns are used as test sequence, it yields dif-ferent fault coverage. To study the relationshipamong the features such as the fault coverage,


transitions and capacitance switching in a circuitusing all possible sequences of an LFSR, faultsimulation and circuit simulation have beencarried out on three different circuits (viz., rippleadder, Booth multiplier and comparator). Thecircuits were synthesized using ASIC Synthesizerof Compass tools. The gate level net list has beensimulated using QSIM of Compass tools to cal-culate the number of transitions of each net.Fault simulation has been done using Verifault-XL Cadence tool for the same gate level net list.We considered all the possible characteristicpolynomials of an 8-stage LFSR and all possibleinitial seeds for each characteristic polynomial inthe simulation studies. The summary of simulationresults is shown in Tables I, II and III. The resultsshown in these Tables are chosen on the basis ofthe following criteria:

Maximum fault coverage achieved in a circuitwith minimum number of patterns.The results corresponding to the number ofpatterns where the percentage difference be-tween fault coverage is maximum.The results corresponding to the number ofpatterns where the percentage difference be-tween number of transitions is maximum.

5.1. Simulation Results of a Ripple Adder

An 8-input ripple adder circuit was simulated anda summary of the simulation results is shown inTable I. The simulation results indicate that a faultcoverage of 97.3% can be achieved by usingpatterns of length 5 to 255. It may be observedthat, as the pattern length reduces, the number oftransitions also reduces. Moreover, for the same

TABLE Simulation results for an adder

No. ofpatterns

Minimum fault Maximum fault Minimum Maximumcoverage coverage Minimum Maximum capacitance capacitance(%) (%) transitions transitions (pF) (pF)

2591012141585127255

49.79676972.4079.3091.5979.3097.3097.3097.30

79.30 52 68 4.53 6.3297.30 61 132 5.63 12.7097.30 70 240 6.78 23.0697.30 74 262 7.I3 25.2197.30 102 284 9.94 27.6397.30 118 312 11.56 30.0597.30 138 341 13.71 33.0897.30 1082 1471 108.73 145.7497.30 1810 1864 180.77 185.4197.30 3623 3660 361.83 364.65

TABLE II Simulation results for a multiplier

No. ofpatterns

Minimum fault Maximum fault Minimum Maximumcoverage coverage Minimum Maximum capacitance capacitance

(%) (%) transitions transitions (pF) (pF)

2591012141585127255

45.79 76.09 99 135 10.0749.79 94.59 102 272 10.7777 98.69 157 432 19.7583 99.09 231 469 28.4383.5 99.09 265 543 33.7586.40 99.09 258 606 30.8089.69 99.59 354 658 45.7199.09 99.59 2469 3111 315.6499.30 99.59 3878 4095 496.2899.59 99.59 7875 8051 1006.94

16.1933.2453.9359.3968.3876.9582.91

394.09519.491025.50

556

No. ofpatterns

Minimum faultcoverage(%)

B. K. S. V. L. VARAPRASAD et al.

TABLE III Simulation results for a comparator

Maximum faultcoverage Minimum Maximum(%) transitions transitions

Minimum Maximumcapacitance capacitance

(pF) (pF)

2591012141585127255

58.26O58.258.258.860.661.288.897.6100

73.5 34 3588.2 33 10197.1 33 17097.6 38 18597.6 43 211100 56 234100 75 240100 810 1052100 1314 1459100 2739 2777

pattern length, depending on the pattern sequenceproduced by the LFSR, the fault coverage and thenumber of transitions vary. For example, with apattern length of 5, depending on the pattern seq-uence, the number of transitions varies between 61to 132 while the fault coverage varies between 67%to 97.3%. It is observed that a pattern length of255 also yields the same fault coverage. However,the number of transitions varies between 3623 to3660 for the pattern length of 255. This behaviorof fault coverage and number of transitions withrespect to the pattern length is reflected in Figure 1.

5.2. Simulation Results of a Booth Multiplier

Simulation were carried out on an 8-input Boothmultiplier circuit. The results shown in Table II,

90 :..:

300070 .’"e0

2500

10o0

Number of patterns

30

20

10

Minimum fault coverage Maximum fault coverageMinimum transitions Maximum transitions

FIGURE Fault coverage and number of transitions for anadder.

4.11 4.203.90 11.633.90 20.O44.53 22.295.05 25.306.65 28.288.81 28.82

96.79 125.12156.05 175.11327.37 331.66

indicate that a fault coverage of 99.59% we canachieve using patterns of various lengths between15 and 255. It may be observed that, the numberof transitions also reduces with reduction of thepattern length. The fault coverage and the num-ber of transitions vary depending on the patternsequence produced by the LFSR. For instance,consider a pattern length of 15. Depending on thepattern sequence, the number of transitions variesbetween 354 to 658 while the fault coverage variesbetween 86.69% to 99.59%. It may further benoted that a pattern length of 255 also yields thesame fault coverage with the number of transi-tions varying between 7875 to 8051. Figure 2illustrates, this behavior of fault coverage andnumber of transitions with respect to the patternlength.

patterns

fault coverage

transitions

FIGURE 2 Fault coverage and number of transitions for amultiplier.


5.3. Simulation Results of a Comparator

Table III presents the simulation results obtainedon an 8-input comparator circuit. The simulationresults indicate that a fault coverage of 100% can beobtained by using patterns of length 14 to 255. Inthis example also, the number oftransitions reduceswith the pattern length. Moreover, for the samepattern length, depending on the pattern sequenceproduced by the LFSR, the fault coverage and thenumber of transitions vary. For example, with a

pattern length of 14, depending on the sequence, thenumber of transitions varies between 56 to 234 andthe fault coverage varies between 60.6% to 100%.Note that a pattern length of 255 also yields thesame fault coverage, but the number of transitionsvaries between 2739 to 2777. This behavior of faultcoverage and number of transitions with respectto the pattern length is reflected in Figure 3.

5.4. Summary of Simulation Studies

A summary of these three simulation studies ispresented in Table IV. These studies indicate that amethod must be adopted to select the test patternsequence such that the application of this testpattern sequence to the CUT gives the maximumfault coverage, while minimizing the number ofpatterns and number of transitions. Minimumnumber of transitions has the obvious advantageof reduced power consumption during testing ofthe circuit. For example, the number of transitionsin the adder circuit for a fault coverage of 97.3%can be reduced from 3623 to 132, with a reducedtest length from 255 to 5, by suitably selecting thecharacteristic polynomial of an LFSR.

6. PROPOSED METHODOLOGY

5040

30

10

Number of pattern==

1500

1000

500

Minimum fault coverageMinimum transitions

Maximum fault coverageMaximum

FIGURE 3 Fault coverage and number of transitions for acomparator.

Configuration of an LFSR for use as an efficientTPG in an On Chip BIST is a difficult problem.We must obtain a solution, such that the LFSRcycles through a minimum number of states inwhich all the required test patterns are included,ensuring high fault coverage consuming minimumpower during testing. A method based on learningand genetic optimization process has been ex-

plained in [10]. In this approach, the authors haveconsidered test length and fault coverage as theparameters of interest but have not aimed at powerminimisation during testing. Considering minimi-zation of power consumption during testing asthe primary objective we propose a methodologyshown in Figure 4.

Testing of an n-input combinational circuitrequires an n-stage LFSR, which is used as a

TABLE IV A summary of the simulation results

Circuit

Minimum Maximum Minimum Maximumpattern pattern number of number oflength length transitions transitions

Faultcoverage(%)

Powersaving(%)

AdderComparatorMultiplier

51415

255 61 3660255 56 2777255 354 8051

97.3100.099.5

98.397.995.6


Tag the identified path forexclusion from this process

Start

Generate test vectors for a CUT using any ATPGtechnique

Construct an LFSR state transition graph

Mark the test vectors generated by the ATPG

in the LFSR state transition graph

Assign the number of logic transitions in the CUTas arc weight of the LFSR state transition graph

Identify a minimum arc weight path in the LFSRcovering the marked states. (a path not tagged)*

Write LFSR state transition equations, from theidentified path

Find the characteristic polynomial using theabove equations

No

Yes

Initially no path is tagged for exclusion.

Realise the LFSR as TPG

FIGURE 4 Method to configure an LSFR as TPG.

TPG. Normally, the LFSR behavior can berepresented in a directed graph. The vertices ofthe graph are the different output patterns gen-erated by the LFSR. An edge connects two prob-able sequences of the output patterns.

Consider a 3-stage LFSR whose behavior isshown in the following graph (See Fig. 5).For a characteristic polynomial /x/x2/x3

and an initial seed of "010", the 3-stage LFSRcycles through the paths {all,al2}. Similarlydepending on its characteristic polynomial andits initial seeds, the LFSR can cycle through the

100

al

110

a3

alO111

a9

FIGURE 5 LFSR graph.

001

a2

011


paths {a3, a4, a5}, {a6, a8, a7}, {al,a8, a2, a3},{al, a8, a7, a12, a5, a3}, {al, al0, a9, a7, a12, a5, a3}and {a2, a3, a4, al 1, a6, al0, a9}.

6.1. Steps to Identify a Path in an LFSRGraph

(1) A set of ’k’ test vectors are derived for theCUT using any Automatic Test Pattern Gen-eration (ATPG) technique.

(2) Construct a state transition graph (arcweighted directed graph) for an n-stage LFSRas explained above, wherein the vertices (statesof an LFSR) are the test vectors.

(3) Mark the ’k’ test vectors, obtained in Step 1, inthe above graph.

(4) Compute the total number of signal transitionsfrom logic "0" to "1" in CUT, while the inputtest vector of the CUT is changed from Si to

Sj, by simulation of the CUT.(5) Represent the number of transitions, obtained

in Step 4, as arc weights in the graph.(6) In the above graph, find the path which has

minimum arc weight which includes all themarked ’k’ test vectors. The minimum arc

weight path can be obtained using the alge-braic method proposed in [11].

In this method, the n-stage LFSR graph,’G’, is represented by its adjacency matrix A,A [ai3] and ai3 if arc (Si, Sj) exists in G

aij 0 if arc (Si, Sj) does not exists in G.

A modified variable adjacency matrix, B, isformed from matrix A in which the elementis set to Sj if there is an arc from vertex Si tovertex Sj and zero otherwise. Let Pi be the pathmatrix, representing all possible paths with Tarcs. All elementary paths in the graph G, canbe obtained by successive multiplication of Bby Pi.

i.e.,

Pi+l B * Pi (3)

The adjacency matrix A represents the pathswith single arc. Hence P1 A.

It may be noted, that in the iterative multi-plication process, the leading diagonal ele-ments of path matrix Pi are set to zero, beforemultiplication, to avoid self loops. The numberof matrix multiplications in Eq. (3) to obtain a

path which includes all the selected ’k’ vectors,varies from k- to 2n- 1.

(7) Find the characteristic polynomial of theLFSR, which cycles through the states repre-sented by the path obtained in Step 6.

6.2. Method to Compute the Coefficientsof the Characteristic Polynomial

A set of equations is formed using all the requi-red states sequence of the LFSR. Let $1, S2,S3,...,Sk be the various states of the selectedsequence produced by LFSR. Let si3 be the jthelement of the Sith state. The relation betweentwo successive states produced by an n-stageLFSR can be expressed in terms of the matrixoperation [12]

Si C Si+l (4)

where

cl 0c2 0

Cn-1 0 0Cn 0 0

0 00 0

00 0

the LFSR transition matrix and S (SilSi2,..., Sin), < < 2n.The values of the first column vector in the

matrix C, viz., (cl, c2,..., Cn- 1, Cn) are the feed-back coefficients of the LFSR and are also thecoefficients of the characteristic polynomial. InEq. (4), Si represents the current state and Si+represents the next state of an n-stage LFSR.


From the matrix operation (4), we have a set ofequations

SllCl -]- S12C2 at- -]- SlnCn $21

S21Cl -J- S22C2 -[- -[- S2nCn $31

SklCl q- Skit2 -t- -I- SknCn Sll

Now the problem reduces to solving theseequations to find out the values of cl, c2,..., Cn.Although the above set of equations appear to bea set of linear equations, the addition is a modulo2 operation. Hence, the conventional techniqueswhich are used to evaluate linear system ofequations can not be used directly. We can solvethese equations by modulo 2 addition of pairsof equations in the set. However, using thisapproach need not always lead to a solution ofthe system of equations. Hence, we propose amethod of substitution to evaluate these coeffi-cients. In this method we assign "0" as the valuefor one of the coefficients. The equations arerewritten with the given values and should bechecked for consistency as defined below.

DEFINITION A system of equations is said to beconsistent if there exist a vector C- (cl c2... %) tosatisfy

n

Z Sij * i k; VSij, i, k [0, 1] (6)i,j=l

under modulo 2 addition.

If the resulting set of equations are consistentthen we take the coefficient to the assigned value as"0", otherwise make the value of the coefficient as"1". Proceed further in the similar manner for thenext coefficient evaluation. In this way all thecoefficients can be evaluated. To explain the aboveprocess, we take an example of an 8-stage LFSRwhose pattern sequences and steps to achieve thesolution for coefficients of a characteristic poly-nomial is explained below.

6.3. Example to Compute the Coefficientsof the Characteristic Polynomial

Consider an LFSR of 8 stages that has to cyclethrough the following twelve sequences.

0 0 0 0 00 0 0 0 0

0 0 0 00 0 0 0

0 0 0 00 0 0

0 0 0 00 0 0 0

0 0 00 0 0 0

0 0 0 00 0 0 0

From Eq. (4), these sequences result in thefollowing system of equations.

c3 +c5

C2cl +c3

This system of equations can be solved for thecoefficients ca, C2,..., Cn, by assigning values either"0" or "1" to the unknown coefficients andchecking the resultant system for consistency.While choosing the values, "0" is given prioritysince the feedback connection can be avoidedwhile realizing the LFSR. Simplification of theabove equations is done by modulo 2 operations.For the above example, the unknown coefficient

vector (c c2 c3 c4 c5 c6 c7 c8). By fixing C "0",we have the following system of equations aftersimplification of the above set of equations.


c3

C4

C2 nt-C5C2 -+-C3

c3 +c4C2 --l-C4 -qt--c5

C2 nt-C3 -+-C5C3

C3

C2

q-c4

+c4

c2 nt-c4

+ca+c6

+c7 0

+c6 +c8+c7

+c8 0-+-C6 0

+c6 +c7nt-C7 -+-C 0

+c6 +c8+c6 +c7 0

q-C7 -t-C 0

The resultant set of equations satisfies c =0since the above equations are consistent. Bysuccessive assignment of the values "0" or "1",to the rest of the coefficients we can get thesolution. It may be noted that assigning c4=0after fixing cl =c.=c3=0, we get the followingset of inconsistent equations.

characteristic polynomial (cl c2 C3 C4 C5 C6 C7 C8)(0 0 0 0 0 0 1) is obtained. The correspondingLFSR is shown in Figure 6.

This way one can find LFSR coefficients andrealize the circuit for required Test PatternGenerator. It may also be noted that some ofthe sequences generated by an LFSR can beobtained by more than one characteristic poly-nomial. Hence, our method of substitutions leadsto one of these characteristic polynomials. Forexample, a 3-stage LFSR cycles through the samesequence 110, 011, 101 for two different character-istic polynomials, namely, -[-ClX--{-C2x2, +C3X3.Though the theory is not mathematically provenhere, we have carried out several experiments usingthe proposed methodology. We have achieved theresult with few iterations.

7. CONCLUSIONS

c5 +caC6

C nt-C7C6 --C8

C7

(7.1)(7.2)

=0 (7.3)(7.4)(7.5)

-0 (7.6)=0 (7.7)

(7.8)-0 (7.9)

(7.10)=0 (7.11)-0 (7.12)

Equation (7.1) and Eq. (7.6) are contradict-ing each other. Hence, we assign c4 1. By ap-plying the above method, the coefficients of the

FIGURE 6 LFSR with characteristic polynomial nt-C4X4qC8X8.

This paper has discussed a suitable method toreduce the power consumption in the BIST im-plementation during testing. Since LFSRs arebeing used as TPG in the BIST implementationscheme as a cost effective TPG, we have con-ducted simulation study of LFSRs with differentconfigurations and initial values for different testsequences. Simulation study on three differentcircuits has revealed that maximum fault coveragecan be achieved with an LFSR sequence of mini-mum test length while keeping the power con-

sumption of the circuit at a low value. We haveshown how to choose a test sequence produced byLFSR to reduce the power consumption usinggraph theory techniques. Also we have shown howto find the characteristic polynomial for a giventest sequence. Even though the approach shownhere is convenient for small combinational circuits,large combinational circuits can be partitionedinto smaller sub blocks and can be tested in asimilar way. In case of sequential circuits, similarapproach can be adopted by introducing scanmethods. We are currently extending our ap-proach for testing sequential circuits.


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[3] Thyagaraju Damarla and Avinash Sathaye, "Applicationof One-dimensional Cellular Automata and LinearFeedback Shift Registers for Pseudo Exhaustive Test-ing", IEEE Trans. on CAD of ICs and Systems, 12(10),1580-1591, October, 1993.

[4] Jan M. Rabaey and Massoud Pedram, Low Power DesignMethodologies, Kulwer Academic Publishers, 1996.

[5] Paul S. Levy, "Designing in Power-down Test Circuits",IEEE Design and Test of Computers, pp. 31-35,September, 1991.

[6] Fujiwara, H., "Computational Complexity of Controll-ability/Observability Problems for CombinationalCircuits", IEEE Trans. on Computers, 39(6), 762-767,June, 1990.

[7] Agarwal, V. D., "A Tutorial on BIST", IEEE Design andTest of Computers, 10(1), 73-82, March, 1993.

[8] Rajesh, V. and Ajai Jain, "Automatic Test PatternGeneration for Sequential Circuits Using Genetic Algo-rithms", Proc. llth International Conference on VLSIDesign’98, pp. 270-273, January, 1998.

[9] Xijianglin, Irith Pomeranz and Sudhakar M. Reddy,"MIX: A Test Generation for Synchronous SequentialCircuits", Proc. llth International Conference on VLSIDesign’98, pp. 456-463, January, 1998.

[10] Irith Pomeranz and Sudhakar M. Reddy, "On Methods toMatch a Test Pattern Generator to a Circuit-Under-Test",IEEE Transactions on VLSI Systems, 6(3), 432-444,September, 1998.

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[12] Golomb, S. W., Shift Register Sequences, Aegean ParkPress, Laguna Hills, Calif., 1982.

Authors’ Biographies

Prof. L. M. Patnaik is a Professor with the IndianInstitute of Science, Bangalore, in the Departmentof Computer Science and Automation. His re-search interests have been in the areas of Paralleland Distributed Computing, Mobile Computing,Soft Computing, CAD of VLSI Circuits, andReal-Time Systems. In these areas, he has

published over 330 papers in refereed Interna-tional Journals and Conference Proceedings. He isFellow of the IEEE, and The Third WorldAcademy of Sciences. He has been awarded theIEEE Computer Society’s 1999 Technical Achieve-ment Award. He serves on the Editorial Boardsof almost a dozen International Journals. Hehas served in various capacities for over 60 IEEEsponsored Conference Committees. He can bereached at [email protected]. H. S. Jamadagni is the Chairman of Cen-tre for Electronic Design and Technology (CEDT)at the Indian Institute of Science, Bangalor. Hisarea of work is Computer Networks and Embed-ded Systems. He is working for a number ofindustry sponsored Research and Developmentprojects. He is involved in a national level educa-tion project. His email address is [email protected]. V. K. Agrawal is working in ISRO since 1976.Currently, he is a Group Director, ControlSystems Group, ISRO Satellite Centre. He hasworked on the design and development of On-board computer systems for satellite with state-of-art technology. His research interests includeParallel processing, Fault tolerant computing,VLSI design and microprocessor based design.B. K. S. V. L. Varaprasad received the B.E. degreein Computer Engineering from Andhra Univer-sity, India in 1987. In 1988, he joined ISROSatellite Centre and working for Testing of VLSIcircuits, design of ASIC’s for logic circuits andsoftware development. In 1997, he took admissionin Indian Institute of Science to do his research inthe area of VLSI testing. His research interests areDesign and Development of VLSI circuits withDFT, Computer Architecture and software devel-opment for EDA tools.

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