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EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 11
Chapter 5Chapter 5
Logic Built-In Self-Test Logic Built-In Self-Test
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 22
What is this chapter about?What is this chapter about?
Introduce the basic concepts of logic BIST BIST Design Rules
Test pattern generation and output response analysis techniques
Fault Coverage Enhancement
Various BIST timing control diagrams A Design Practice
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 33
IntroductionIntroduction
What are the problems in today’s semiconductor testing? Traditional test techniques become quite
expensive No longer provide sufficiently high fault coverage
Why do we need built-in self-test (BIST)? For mission-critical applications Detect un-modeled faults Provide remote diagnosis
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 44
BIST Techniques CategoriesBIST Techniques Categories
Online BIST Concurrent online BIST Non Concurrent online BIST
Offline BIST Functional offline BIST Structural offline BIST
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 55
A General Form of Logic BISTA General Form of Logic BIST
Non-concurrent
BIST
Offline Online
ConcurrentFunctional Structural
[Abramovici 1994]
Logic BIST Techniques
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 66
AA Typical Logic BIST SystemTypical Logic BIST System
Structural off-line BIST
Logic BIST
Controller
Test Pattern Generator (TPG)
Output Response Analyzer (ORA)
Circuit Under Test (CUT)
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 77
BIST Design RulesBIST Design Rules
Logic BIST requires much more stringent design restrictions when compared to conventional scan. Therefore, when designing a logic BIST system, it is essential that the circuit under test meet all scan design rulesand BIST specific design rules, called BIST design rules.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 88
Typical X-bounding MethodsTypical X-bounding Methods
Methods for blocking an unknown (X) source
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 99
X-bounding Methods X-bounding Methods Depending on the nature of each unknown (X) source, several X-bounding methods can be appropriate for use.
Common problems: (1) Increase the area of the design. (2) Impact timing.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1010
Typical Unknown SourcesTypical Unknown Sources
Analog Blocks Adding bypass logic. Adding control-only scan point
Memories and Non-Scan Storage Elements Bypass logic Initialization
Combinational Feedback Loops Scan points
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1111
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
Asynchronous Set/Reset Signals using the existing scan enable (SE) signal to
protect each shift operation and adding a set/reset clock point (SRCK) on each set/reset signal to test the set/reset circuitry.
Set/ResetCircuitry
RD Q
FunctionalLogic
CK
0
1
Scan-In
SE
SRCK
[Abdel-Hafez 2004]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1212
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
Asynchronous Set/Reset Signals
CK
SRCK
SE
Shift Window Capture Window
… C1
Shift Window
C2
…
Capture Window
…
Shift Window
Timing control diagram for testing data and set/reset faults
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1313
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
Tri-State Buses Re-synthesize each bus with multiplexers. One-hot decoder
A one-hot decoder for testing a tri-state bus with 2 drivers
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1414
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
False Paths 0-control point 1-control point
Critical Paths Adding an extra input pin to a selected
combinational gate on the critical path.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1515
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
Multiple-Cycle Paths 0-control point 1-control point Holding certain scan cell output states
Floating Ports PI or PO must have a proper connection to Power
(Vcc) or Ground (Vss). Floating inputs to any internal modules must be
avoided.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1616
Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)
Bi-directional I/O Ports Fix the direction of each bi-directional I/O port to
either input or output mode.
BIST_mode
EN
D IO
Z
SE
Forcing a bi-directional port to output mode
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1717
Re-TimingRe-Timing
Races and hazards caused by clock skews may occur between the TPG and the (scan chain) inputs of the CUT as well as between the (scan chain)outputs of the CUT and the ORA. To avoid these potential problems and ease physical implementation, we recommend adding re-timing logic between the TPG and the CUT and between the CUT and the ORA.
D Q
CK D Q
CK O R A
CK3
D Q
CK D Q
CK T P G
CK1 CK2
CUT
Re-timing logic among the TPG, CUT, and ORA
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1818
Test Pattern GenerationTest Pattern Generation
Test pattern generators (TPGs) constructed from linear feedback shift registers (LFSRs)
TPG Exhaustive testing Pseudo-random testing Pseudo-exhaustive testing
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1919
Standard LFSRStandard LFSR
Si0 Si1Sin-2 Sin-1
hn-1 hn-2 h2 h1
Consists of n D flip-flops and a selected number of exclusive-OR (XOR) gates
An n-stage (external-XOR) standard LFSR
[Golomb 1982]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 2020
Modular LFSRModular LFSR Each XOR gate placed between two
adjacent D flip-flops
An n-stage (internal-XOR) modular LFSR
[Golomb 1982]Si0 Si1 Sin-2
h1 h2 hn-2 hn-1
Sin-1
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 2121
LFSR PropertiesLFSR Properties
The internal structure of the n-stage LFSR can be described by a characteristic polynomial of degree n,
f(x).
hi is either 1 or 0,depending on the feedback path
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 22
LFSR PropertiesLFSR Properties
22
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 2323
LFSR PropertiesLFSR Properties
Let Si represent the contents of the n-stage LFSR after shifts of the initial contents,S0,of the LFSR, and Si(x) be the polynomial representation of Si
thi
If T is the smallest positive integer such that f(x) divides ,then the integer T is called the period of the LFSR.
Tx1
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 24
LFSR PropertiesLFSR Properties
If T = 2n −1, then the n-stage LFSR generating the maximum-length sequence is called a maximum-length LFSR.
Define a primitive polynomial of degree n as a polynomial that divides 1+xT, but not 1+xi, for any integer i < T, where T = 2n−1 [Colomb 1982].
24
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 2525
4-stage standard and modular LFSRs4-stage standard and modular LFSRs
421 xxxf
• 4-stage Standard LFSR
• 4-stage Modular LFSR
41 xxxf
30 xs
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 26
4-stage standard and modular LFSRs4-stage standard and modular LFSRs
The first test sequence repeats after 6 patterns The second test sequence repeats after 15
patterns, the LFSRs have periods of 6 and 15, respectively.
This further implies that 1+x^6 can be divided by 1+x^2 +x^4, and 1+x^15 can be divided by
1+x+x^4.
26
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 27
4-stage standard and modular LFSRs4-stage standard and modular LFSRs
27
A primitive polynomial is irreducible. Because T = 15 = 2n −1,
the characteristic polynomial, f(x) = 1+x+x4, used to construct the previous Figure is a primitive polynomial; thus, the modular LFSR is a maximum-length LFSR.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 28
Finite field arithmeticFinite field arithmetic
Arithmetic in a finite field is different from standard integer arithmetic. There are a limited number of elements in the finite field; all operations performed in the finite field result in an element within that field.
28
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 29
Finite field arithmeticFinite field arithmetic
The finite field with pn elements is denoted GF(pn) and is also called the Galois Field, in honor of the founder of finite field theory, Évariste Galois.
A particular case is GF(2), where addition is exclusive OR (XOR) and multiplication is AND. Since the only invertible element is 1, division is the identity function
29
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 30
Finite field arithmeticFinite field arithmetic
For example, the following are equivalent representations of the same value in a characteristic 2 finite field:
Polynomial: x6 + x4 + x + 1
Binary: {01010011}
30
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 31
Finite field arithmeticFinite field arithmetic
In a finite field with characteristic 2, addition modulo 2, subtraction modulo 2, and XOR are identical. Thus,
Polynomial: (x6 + x4 + x + 1) + (x7 + x6 + x3 + x) = x7 + x4 + x3 + 1
Binary: {01010011} + {11001010} = {10011001}
31
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 32
Finite field arithmeticFinite field arithmetic Under regular addition of polynomials, the sum
would contain a term 2x6, but that this term becomes 0x6 and is dropped when the answer is reduced modulo 2.
Here is a table with both the normal algebraic sum and the characteristic 2 finite field sum of a few polynomials:
32
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 33
Finite field arithmetic (Multiplication)Finite field arithmetic (Multiplication)
(x6 + x4 + x + 1)(x7 + x6 + x3 + x) =
(x13 + x12 + x9 + x7) + (x11 + x10 + x7 + x5) + (x8 + x7 + x4 + x2) + (x7 + x6 + x3 + x) =
x13 + x12 + x9 + x11 + x10 + x5 + x8 + x4 + x2 + x6 + x3 + x =
x13 + x12 + x11 + x10 + x9 + x8 + x6 + x5 + x4 + x3 + x2 + x
33
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 34
Example: LFSR Example: LFSR
G(X) = X3 + X1 + 1 represents an LFSR with feedback taps 3 and 1
34
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 35
LFSRLFSR
For example, we may be asked to find all sets of maximal-length feedback taps for an LFSR with m=3 registers. We do this as follows: The length of the m-sequences will be N=23-1=7. We know that the solution lies in all the primitive factors of polynomial X7+1. We use modulo-2 linear algebra (probably with the aid of a computer algorithm) to find the prime factors to be
35
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 3636
Hybrid LFSRHybrid LFSR
Fully decomposable iff both b(x) and c(x) have no common terms and there exists an integer j such that
xcxbxa 1
1, jxbxxc j
xbxxbxf j1
Assume: f(x) is fully decomposable
A (hybrid) top-bottom LFSR [Wang 1988a] can be constructed:
xbxxxs jj 1
Indicate the XOR gate with one input Is connected to the feedback path, notbetween stages
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 3737
5-stage hybrid LFSRs 5-stage hybrid LFSRs
(a) 5-stage top-bottom LFSR
(b) 5-stage bottom-top LFSR
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 38
Hybrid LFSRsHybrid LFSRs
Assume that a standard or modular LFSR uses m XOR gates, where m is an odd number.
If its characteristic polynomial, f(x), is fully decomposable, then a hybrid LFSR can be realized with only (m+1)/2 XOR gates.
38
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 3939
Primitive polynomials list Primitive polynomials list Primitive polynomials of degree n up to 100
013424)( xxxxxxp Note: “24 4 3 1 0” means
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4040
Exhaustive TestingExhaustive Testing
Exhaustive Testing Applying exhaustive patterns to an n-input
combinational circuit under test (CUT)
Exhaustive pattern generator Binary counter Complete LFSR
n2
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4141
Binary counterBinary counter
Example binary counter as EPG
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4242
Exhaustive Testing performanceExhaustive Testing performance
Exhaustive Testing guarantees all detectable, combinational faults will be detected.
Test time maybe be prohibitively long if input number is larger than 20.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4343
Pseudo-Random TestingPseudo-Random Testing
Pseudo-random pattern generator Reduce test length but sacrifice the fault
coverage Difficult to determine the required test
length and fault coverage
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4444
Pseudo-Random TestingPseudo-Random Testing
Maximum-length LFSR RP-resistant problem
Weighted LFSR Cellular Automata
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4545
Weighted LFSRWeighted LFSR
Example weighted LFSR as PRPG
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4646
Cellular AutomataCellular Automata
Provide more random test patterns Provide high fault coverage in a random-
pattern resistant (RP-resistant) circuit Implementation advantage
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4747
Cellular AutomataCellular Automata
A general structure of an n-stage CA
‘0’
‘0’
Cell0
Cell1
Celln-2
Celln-1
Each rule determines the next state of a cell based on the state of the cell and its neighbors
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4848
Cellular AutomataCellular Automata
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4949
Example cellular automatonExample cellular automaton
A 4-stage CA Test sequence
X0 X1
‘0’
‘0’
X3X2
0 0 0 10 0 1 00 1 1 11 1 1 10 0 1 10 1 0 11 0 0 01 1 0 00 1 1 01 1 0 10 1 0 01 0 1 01 0 1 11 0 0 11 1 1 0
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5050
CA construction rulesCA construction rulesConstruction rules for cellular automata of length n up to 53
[Hortensius 1989]
*For n=7, Rule=152=001,101,010=1,101,010, where “0” denotes a rules 90 and “1” denotes a rule 150 cell, or vice versa
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 51
Cellular Automata ImplementationCellular Automata Implementation
51
‘0’
‘0’
Cell0
Cell1
Celln-2
Celln-1
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 52
2-D Cellular Automata Implementation2-D Cellular Automata Implementation
52
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 53
2-D Cellular Automata Implementation2-D Cellular Automata Implementation
53
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 54
LFSR ImplementationLFSR Implementation
54
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5555
Pseudo-Exhaustive Testing Pseudo-Exhaustive Testing
Reduce test time while retaining many advantages of exhaustive testing
Guarantee 100% single-stuck fault coverage
Verification test technique [McCluskey 1984] Segmentation test technique [McCluskey 1981]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5656
Verification TestingVerification Testing
Divide the CUT into m cones, backtracing from each output to determine the inputs that drive the output. Each cone will receive
exhaustive test patterns and are tested concurrently. [McCluskey 1984]
x1
y1
x2
y2
x3
y3
x4
y4
Pseudo-exhaustive pattern generatorsPEPGs
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5757
Syndrome Driver CounterSyndrome Driver Counter
Use SDC to generate test patterns. Check whether some inputs can share the same test signal. If n-p Inputs can share test inputs with other p inputs, then the circuit can be tested exhaustively with these
p inputs. [Savir 1980]
A 3-stage syndrome driver counter
X1 X2 X3
X4
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5858
Constant-Weight CounterConstant-Weight Counter
Use CWCs to generate test patterns. Constant-Weight counters are constructed using constant-weight code or M-out-of-N code. The constant-weight test set is a minimum-length test set for many circuits.
[McCluskey 1982]
A 3-stage constant-weight counterX1 X2 X3
X4
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5959
Combined LFSR/SRCombined LFSR/SRUse a combination of an LFSR and a shift register (SR) for patterngeneration. The method is most effective when w is much less than n.In general, this technique requires much more tests than other schemes when w is greater than n/2.
[Barzilai 1983 ] [Tang 1984]
A 4-stage combinedLFSR/SRX1 X2 X3 X4
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6060
Combined LFSR/PSCombined LFSR/PSA combined LFSR/PS approach using a combination of an LFSR and a linear phase shifter which includes a network of XOR gates to generate test pattern. Similar to combined LFSR/SR, this technique requires more tests than other schemes when w is greater than n/2.
[Vasanthavada 1985]
A 3-stage combined LFSR/PSX1 X2 X3
X4
X1 X2 X3
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6161
Condensed LFSRCondensed LFSR
)]1/([]1/[ knkknkw
Condensed LFSRs are constructed based on linear codes.Define g(x) and p(x) as the generator polynomial and primitive polynomial over GF(2), respectively. An (n, k) condensed LFSR
can be realized using
Where
[Wang 1986a]
)()...1()()()( 2 xpxxxxpxgxf kn
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6262
Example Condensed LFSR Example Condensed LFSR
A (4,3) condensed LFSR Test sequence
X1 X2 X3 X4
1100011000111010010110011111
Set
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6363
Cyclic LFSRCyclic LFSR
Use cyclic LFSRs to reduce the test length when w < n/2.
A cyclic code always exists when
1,12' bn b
find a generator polynomial g(x) of largest degree k’ (or smallest degree k), for generating an (n’,k’) = (n’,n’-k) cyclic code, that divides 1+x^^n’ and has a design distance d > w+1;
construct an (n’,k) cyclic LFSR using f(x) = h(x)p(x) = (1+x^^n’)p(x)/g(x), where h(x) = (1+x^^n’)/g(x); and
shorten this (n’,k) cyclic LFSR to an (n,k) cyclic LFSR by deleting the rightmost, middle, or leftmost n’-n stages from the (n’,k) cyclic LFSR.
To exhaustively test any (n,w) CUT
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6464
Example Cyclic LFSR Example Cyclic LFSR A (8,5) cyclic LFSR, picking the first 6 stages and the last two stages of the (15,5) cyclic LFSR.
An (n,k-s) shorted cyclic LFSR can be employed when
1 0 1 0 0 1 0 0
22 , bn b
1 0 1 0 1 0 1 0
[Wang 1987b]
[Wang 1988b]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6565
Compatible LFSR Compatible LFSR
(a) An (n,w) = (5,4) CUT (b) A 2-stage compatible LFSR
The combined LFSR of an l-stage LFSR and an l-to-n mapping logic,called l-stage compatible LFSR, can further reduce the test length, whenonly single stuck faults are considered.
Y1
Y2
X1
X2
X3
X4
X5
0 0
X1 X2 X3 X5X4
Example compatible LFSR as PEPG
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6666
Segmentation TestingSegmentation Testing
Used when Test length using previous techniques is too long
or Output depends on all inputs.
Divide the circuit into segments Hardware partitioning Sensitized partitioning
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6767
Delay Fault TestingDelay Fault Testing
Need patterns to test delay fault exhaustively
Test set could cause test invalidation when more than one inputs change.
122 nn
TESTTYPE
X1 X2 Xn-1Xn
hn-1 hn-2 h2 h1
0
1 [Bushnell 2000]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6868
Output Response AnalysisOutput Response Analysis
Output response compacted to a signature Then compared with golden signature Compaction Techniques: Ones count testing Transition count testing Signature analysis
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6969
Ones Count TestingOnes Count Testing
},,{ 1210 Lrrrr
Assume the CUT has one output and the output contains a stream of L bits. Let the fault-free output response be
Aliasing probability [Savir 1985]
Ones count testing will need a counter to count the number of 1s in the bit stream.
)12/()1),(()( LOC mLCmP
Example:
R0 ={0101100} , OC=4,
m= OCR = 3 and L = 7, POC(m )= 34/127 = 0.27
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7070
One Count TestingOne Count Testing
SignatureCUT
T
Counter
CLK
One counter as ORA
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7171
Transition Count TestingTransition Count TestingTransition count testing is similar to that for ones count testing, except the signature is defined as the number of 1-to-0 and 0-to-1 transitions.
Aliasing probability
[Hayes 1976]
)12/()1),1(2()( LTC mLCmP
In the previous example, where m= TCR0 = 4 and L = 7,P(TC(m)) = 29/127 = 0.23
R0 ={0101100} , OC=4,
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7272
Transition Count TestingTransition Count Testing
Transition counter as ORA
CUTT SignatureCounter
CLK
D Q
riri-1
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7373
Signature AnalysisSignature AnalysisSignature analysis is the most popular compaction technique used today, based on cyclic redundancy checking.
Two signature analysis schemes Serial signature analysis Parallel signature analysis
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7474
Serial Signature AnalysisSerial Signature Analysis
11210 ...)(
LL xmxmxmmxM
r0 rn-2 rn-1
h1 h2 hn-2 hn-1
M r1
An n-stage single-input signature register
Define L-bit output sequence M
Let the polynomial of the modular be f(x)
IFSignature is the
polynomial remainder, r(x))()()()( xrxfxqxM
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7575
ExampleExample
M
A 4-stage SISR
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7676
ExampleExample
M
A 4-stage SISR
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 77
SISRSISR
77
fault detection or aliasing problem of an SISR E or error polynomial E(x) of the fault-free
sequence M and a faulty sequence M’.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7979
Parallel Signature AnalysisParallel Signature AnalysisMultiple-input signature register (MISR)
An n-input MISR can be remodeled as a single-input SISR witheffective input sequence M(x) and effective error polynomial E(x)
M1 M2M0 Mn-2 Mn-1
h1 h2 hn-2 hn-1
r0 r1 rn-1rn-2
)()(...)()()( 11
22
10 xMxxMxxxMxMxM nn
nn
)()(...)()()( 11
22
10 xExxExxxExExE nn
nn
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8080
4-stage MISR4-stage MISR
A 4-stage MISR
M1M2M0 M3
M0
M1
M2
M3
1 0 0 1 00 1 0 1 0
1 1 0 0 0
1 0 0 1 1
1 0 0 1 1 0 1 1M
An equivalent M sequence
Aliasing probability
)12/()12()( )( mLnmLPSA nP
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8282
Logic BIST ArchitecturesLogic BIST Architectures
Four Types of BIST Architectures: No special structure to the CUT Make use of scan chains in the CUT Configure the scan chains for test pattern
generation and output response analysis Use concurrent checking circuitry of the
design
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8383
TypeType II - Centralized and Separate - Centralized and Separate Board-Level BIST (CSBL)Board-Level BIST (CSBL)
Two LFSRs and two multiplexers are added to the circuit.The first LFSR acts as a PRPG, the second serves as a SISR.The first multiplexer selects the inputs, another routes the PO to the SISR.
[Benowitz 1975]
CSBL Architecture
n
PIs CUT(C or S)
MUX SISRk 1
mMUX
n
1
k = [log2m]
PRPG
n
TEST
POs
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8484
Type I -Type I - Built-In Evaluation and Self- Built-In Evaluation and Self-Test (BEST)Test (BEST)
Use a PRPG and a MISR. Pseudo-random patterns are applied in parallel from the PRPG to the chip primary inputs (PIs) and a MISR is used to compact the chip output responses .
[Perkins 1980]
BEST ArchitecturePOs
CUT (C or S)
MISR
PRPG
PIs
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8585
Type II -Type II - LSSD On-Chip Self-Test LSSD On-Chip Self-Test (LOCST)(LOCST)
In addition to the internal scan chain, an external scan chain comprising all primary inputs and primary outputs is required. The External scan-chain input is connected to the scan-out point of the internal scan chain.
[Eichelberger 1983]
LOCST Architecture
Sin
CUT(C)
Si So
POsPIs
SRL
R2
SISRPRPG Sout
SRL
R1
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8686
Type II -Type II - Self-Testing Using MISR and Parallel Self-Testing Using MISR and Parallel SRSG (STUMPS)SRSG (STUMPS)
Contains a PRPG (SRSG) and a MISR. The scan chains areloaded in parallel from the PRPG. The system clocks are then pulsed and the test responses are scanned out to the MISR for compaction. New test patterns are scanned in at the same time when the test responses are being scanned out.
[Bardell 1982]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8787
STUMPS STUMPS
PRPG
MISR
CUT
(C or S)CUT
(C or S)
Linear Phase Compactor
MISR
Linear Phase Shifter
PRPG
STUMPS A STUMPS-based Architecture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8888
Type IIIType III - Built-In Logic Block Observer - Built-In Logic Block Observer (BILBO) (BILBO)
The architecture applies to circuits that can be partitioned intoindependent modules (logic blocks). Each module is assumed to have its own input and output registers (storage elements), or such registers are added to the circuit where necessary. The registers are redesigned so that for test purposes they act as PRPGs or MISRs.
[Konemann 1980]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8989
Built-In Logic Block Observer Built-In Logic Block Observer
Scan-In X0
0
1D Q
B1
B2
Y0 Y2Y1
D Q D Q
SCK X1Scan-Out/X2
A 3-stage BILBO
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9090
Type III -Type III - Concurrent Built-In Logic Block Concurrent Built-In Logic Block Observer (CBILBO)Observer (CBILBO)
A 3-stage concurrent BILBO (CBILBO)
Scan-In X0
B1
Y0 Y1 Y2
SCK X1
D Q0
1
1D2DSEL
D Q
0
1 1D2DSEL
Q Q
D Q
1D2DSEL
Q
B2 X2
Scan-Out
[Wang 1986c]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9191
Type III -Type III - Circular Self-Test Path (CSTP) Circular Self-Test Path (CSTP)
All primary inputs and primary outputs are reconfigured as externalscan cells. They are connected to the internal scan cells to form a circularpath. During self-test, all primary inputs (PIs) are connected as a shiftregister (SR), whereas all internal scan cells and primary outputs (POs) are reconfigured as a MISR.
[Krasniewsk 1989]
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9292
Circular Self-Test Path Circular Self-Test Path
(a) The CSTP architecture (b) Self-Test cell
CUT(C)
PIs
Sin 0
1
CIRCULATE
Sout MISRMISR
MISRSR
POs
TEST
0
1Xi-1
Yi XiD Q
CLK
CSTP architecture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9393
Type IV -Type IV - Concurrent Self-Verification (CSV) Concurrent Self-Verification (CSV)
CSV Architecture
Checking Circuitry
Functional Circuitry Duplicate Circuitry
m m
two-rail checker
PRPG
n
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9494
SummarySummary
Representative Logic BIST Architectures
B: board-level testingC: combinational circuitS: sequential circuit
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9595
Fault Coverage EnhancementFault Coverage Enhancement
Three approaches to enhance the fault coverage Test point insertion Mixed-mode BIST Hybrid BIST
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9696
Test Point InsertionTest Point Insertion
Two typical types of test points
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9797
Test Point Insertion ExampleTest Point Insertion ExampleAn example where one control point and one observation point are inserted to increase the detection probability of a 6-input AND-gate.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9898
Test Point PlacementTest Point Placement
Fault simulation guided techniques Testability measure guided techniques Timing-driven test point insertion techniques
Where to place the test points in the circuit to maximize thecoverage and minimize the number of test points required.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9999
Control Point ActivationControl Point Activation
Random activation Deterministic activation
During normal operation, all control points must be deactivated. During testing, there are different strategiesas to when and how the control points are activated.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 100100
Mixed-Mode BISTMixed-Mode BIST
Mixed-mode BIST is an alternative way to improve fault coverage without modifying the CUT.Pseudo-random patterns are generated to detect the RP-testable faults, and then some additional deterministic patterns are generated to detect the RP-resistant faults.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 101101
Mixed-Mode BIST Mixed-Mode BIST
ROM Compression. LFSR Reseeding. Embedding Deterministic Patterns.
Approaches for generating deterministic patterns on-chip:
LFSR
Bit-Flipping Function
Scan Chain
…
…
… … … LFSR
Seeds Poly. Id
Dec
odin
g
Log
ic
…
..
Reseeding with multiple-polynomial LFSR
Bit-flipping BIST
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 102102
Hybrid BISTHybrid BISTFor manufacturing fault coverage enhancement where a tester is present, deterministic data from the tester can be used to improve the fault coverage.
Top-up ATPG Store the compressed deterministic patterns
on the tester
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 103103
BIST Timing ControlBIST Timing Control
To test Multiple-clock-domain circuits To detect Intra-clock-domain faults and
inter-clock-domain faults Capture-clocking schemes
Single-capture Skewed-load Double-capture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 104104
One-Hot Single-CaptureOne-Hot Single-Capture A capture pulse is applied to one clock domain, while holding all other test clocks inactive, during each capture window.
Benefit: a single and slow global scan mode signalDrawback: long test time
CK1
CK2
GSE
Shift Window Capture Window
…C1
Shift Window
C2
…
Capture Window
…
Shift Window
… ……
d1 d2
One-hot single-capture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 105105
Staggered Single-CaptureStaggered Single-Capture
Benefits: short test time; a single and slow global scan mode signalDrawback: some structural fault coverage loss
CK1
CK2
Shift Window Capture Window Shift Window
…
…
…
…
C1
C2
GSE
d2 d3d1 Staggered single-capture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 106106
Skewed-LoadSkewed-Load
An at-speed delay test technique Address intra-clock-domain delay faults Three approaches
One-hot skewed-load Aligned skewed-load Staggered skewed-load
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 107107
One-Hot Skewed-LoadOne-Hot Skewed-Load Tests all clock domains one by one by applying a-shift-followed by-a-capture pulses to detect intra-clock-domain delay faults.
Drawbacks: (1) Cannot detect inter-clock-domain delay faults (2) Test time is long (3) Single and global scan enable (GSE) signal can no longer be used
CK1
SE1
Shift Window Capture Window Shift Window Capture Window Shift Window
… … …S1 C1
d1
CK2
SE2
…C2
……S2
d2
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 108108
Aligned Skewed-LoadAligned Skewed-Load
Solve the long test time problem Test all intra-clock-domain and inter-
clock-domain faults Need complex timing-control
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 109109
Aligned Skewed-LoadAligned Skewed-Load
S
CK1
CK2
CK3
SE1
SE2
SE3
Capture WindowC1
C2
C3
S1S3
CK1
CK2
CK3
SE1
SE2
SE3
S2S1 C
Capture aligned skewed-load Launch aligned skewed-load
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 110110
Staggered Skewed-LoadStaggered Skewed-Load When two test clocks cannot be aligned precisely, we can simply insert a proper delay to eliminate the clock skew. The two last shift pulses are used to create transitions and their output responses are caught by the next two capture.
Drawback: Need at-speed scan enable signal for each clock domain
CK1
SE1
Shift Window Capture Window Shift Window
… …S1 C1
d1
d3
CK2
SE2
…C2
…S2
d2
Staggered skewed-load
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 111111
Double CaptureDouble Capture
Solve the physical implementation difficulty using skewed-load
True at-speed test Double-capture benefits
Detect intra-clock-domain faults and inter-clock-domain structural faults or delay faults at-speed
Facilitate physical implementation Ease integration with ATPG
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 112112
One-Hot Double-CaptureOne-Hot Double-Capture Test all clock domains one by one by applying two consecutive capture pulses at their respective domains’ frequencies to test intra-clock-domain delay faults.
Benefit: true at-speed testing of intra-clock-domain delay faults
Drawbacks: (1) Cannot detect inter-clock-domain delay faults (2) Test time is long
One-Hot double-capture
Shift Window Capture Window Shift Window Capture Window Shift Window
CK1 … … …C1 C2
d1
CK2 …C4
……C3
d2
GSE
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 113113
Aligned Double-CaptureAligned Double-Capture
Aligned double-capture - I Aligned double-capture - II
C3
CK1
CK2
CK3
C2C1 C
GSE
C
CK1
CK2
CK3
Capture Window
C1 C4
C2
GSE
C3
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 114114
Staggered Double-Capture Staggered Double-Capture In the capture window, two capture pulses are generated for eachclock domain. The first two capture pulses are used to create transitions at the outputs of scan cells, and the output responses to the transitions are caught by the next two capture pulses, respectively.
Staggered double-capture
Shift Window Capture Window Shift Window
…
…
…
…
CK1
CK2
C1 C2
C3 C4
GSE
d2 d3 d4d1 d5
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 115115
Fault DetectionFault Detection Intra-clock-domain delay fault detection is relatively
easy. Testing inter-clock-domain delay faults is more
complex. A single capture yields the highest fault coverage of
inter-clock-domain delay faults.
GSE
CK1
CK2
Shift Window Capture Window Shift Window
…
…
…
…
C1
C2
d
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 116116
Fault Detection CapabilityFault Detection Capability
Note: A hybrid double-capture scheme using staggered double-capture and aligned double-capture seems to be the preferred scheme for true at-speed testing
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 117117
A Design PracticeA Design PracticeAn example of designing a logic BIST system for testing a scan-based design (core) comprising two clock domains using s38417 and s38584. The two clock domains are taken from the ISCAS-1989 benchmarkcircuits [Brglez 1989].
Design statistics
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 118118
Design flowDesign flow
BIST Rule Checking and Violation Repair Logic BIST System Design RTL BIST Synthesis Design Verification and Fault Coverage
Enhancement
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 119119
BIST Rule Checking and Violation RepairBIST Rule Checking and Violation Repair
The number of test clocks present in the design The number of set/reset clocks present in the design
All DFT rule violations of the scan design rules and BIST-specific designrules must be repaired. In addition, we should be aware of the followingdesign parameters:
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 120120
Logic BIST System DesignLogic BIST System Design
The type of logic BIST architecture to adopt The number of PRPG-MISR (or PEPG-MISR) pairs to use The length of each PRPG-MISR (or PEPG-MISR) pair The faults to be tested and BIST timing control diagrams to be
used The types of optional logic to be added
The second step is to design the logic BIST system at the RTL, including:
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 121121
Logic BIST ArchitectureLogic BIST Architecture
A logic BIST system for testing a design with 2 cores
We choose to implement a STUMPS-based architecture, since it is easy to integrate with scan/ATPG and is the industry widely used architecture.
MISR2
ClockDomain
CD1
TPG
Input Selector
ClockDomain
CD2
BIST-Ready Core
ORAMISR1
SpC1 SpC2
PIs/ SIs
POs/ SOsClockGatingBlock
TestController
SCK1SCK2
StartFinishResult
TCK1
TCK2 C
CCK1CCK2
PRPG1
PS1/SpE1
PRPG2
PS2/SpE2
PLL
Data/Control
Logic BIST Controller
CK1CK2
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 122122
TPG and ORATPG and ORA
Next, we need to determine the length of each PRPG-MISR pair. Using aseparate PRPG-MISR pair for each clock domain allows us to reduce the Length of each PRPG and MISR.
PRPG-MISR Choices
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 123123
Test ControllerTest Controller
The test controller plays a central role in coordinating the overall BIST operation. Often, external signals are controlled through an IEEE 1149.1 Boundary-Scan Standard based test access port (TAP) controller.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 124124
Test Controller (cont)Test Controller (cont)
In order to test structural faults in the BIST-ready core, we choose the Staggered single-capture approach.
TCK1
TCK2
Shift Window Capture Window Shift Window
…
…
…
…
C1
C2
GSE
Slow-speed timing control using staggered single-capture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 125125
Test Controller (cont)Test Controller (cont)
In order to test delay faults in the BIST-ready core, we choose the Staggered double-capture approach if CD1 and CD2 are asynchronous, or the aligned double-capture approach if they are synchronous.
Staggered double-capture
Shift Window Capture Window Shift Window
…
…
…
…
TCK1
TCK2
C1 C2
C3 C4
GSE
Shift Window Capture Window Shift Window
…
…
…
…
TCK1
TCK2
C1 C2
C3 C4
GSE
d
Aligned double-capture
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 126126
Clock Gating BlockClock Gating Block
In order to generate an ordered sequence of single-capture or double-capture clocks, clock suppression [Rajski 2003] [Wang 2004], daisy-chain clock-triggering, or token-ring clock-enabling [Wang 2005a] can be used.
TCK1
TCK2
GSE
…
…
C1 C2
C3 C4 d
Daisy-chain clock-triggering
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 127127
Clock Gating Block (cont)Clock Gating Block (cont)
SE2 Generator
SE2
2-Pulse Controller
TCK1
CK1
SE1 Generator
BIST mode
CK2 CK2
TCK2 2-Pulse
Controller
CK1
SE1
A daisy-chain clock-triggering circuit
CK1
CK1
CK1
TCK2 1 1 1 1 CK2
GSE Generator
BIST mode
GSE
0 0 1 1 TCK1 ‘0’
‘0’
A clock suppression circuit
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 128128
Re-Timing LogicRe-Timing Logic
we recommend adding two pipelining registers between each PRPG andthe BIST-ready core, and two additional pipelining registers between the BIST-ready core and each MISR. In this case, the maximum scan chain length for each clock domain,CD1 or CD2, is effectively increased by 2,not 4.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 129129
Fault Coverage Enhancing Logic and Fault Coverage Enhancing Logic and Diagnostic LogicDiagnostic Logic
In order to improve the circuit’s fault coverage, we recommend adding extra test points and additional logic for top-up ATPG support at the RTL.
We also recommend including diagnostic logic in the RTL BIST code tofacilitate debug and diagnosis.
Example test modes to be supported by the logic BIST system
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 130130
RTL BIST SynthesisRTL BIST Synthesis
At this stage, it is possible to either design the logic BIST system by handor generate the RTL code automatically using a (commercially available) RTL logic BIST tool.
In either case, the number of scan chains for each clock domain should be specified along with the names of their associated scan inputs (SIs) and scan outputs (SOs) without inserting the actual scan chains into the circuit.
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 131131
Design Verification and Fault Coverage Design Verification and Fault Coverage EnhancementEnhancement
Finally, the synthesized netlist needs to be verified with functional and/or Timing verification.
Next, fault simulation needs to be performed on the pseudo-random Patterns generated by the TPG in order to determine the circuit’s fault coverage.
Fault simulation and test point insertion flow
Test Point Selection at RTL Design
Logic/Scan Synthesis
Gate-Level Test Point Insertion
Yes
Done
No Coverage Acceptable ?
Fault Simulation
EE141VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 132132
Concluding RemarksConcluding Remarks STUMPS is an industry widely adopted logic
BIST architecture, but hits problems due to low fault coverage.
Some challenges ahead Whether the CBILBO-based architecture proposed by
Wang and McCluskey would perform as it always guarantee 100% single stuck-fault coverage.
Whether pseudo-exhaustive testing would become the preferred BIST technique.