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Electrical Architecture and Interfaces Pierre PRAT Progress Meeting @APC the 12.10.2012 Michel DUPIEUX

Electrical Architecture and Interfaces

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Electrical Architecture and Interfaces. Pierre PRAT Progress Meeting @APC the 12.10.2012 Michel DUPIEUX. Grounding. Grounding Design is now stable after Johan Panh’s Remarks. Grounding principles. In order to avoid ground loops: Use of galvanically isolated DC/DC converters - PowerPoint PPT Presentation

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Page 1: Electrical  Architecture and Interfaces

Electrical Architecture and Interfaces

Pierre PRAT Progress Meeting @APC the 12.10.2012 Michel DUPIEUX

Page 2: Electrical  Architecture and Interfaces

Grounding

Grounding Design is now stable after Johan Panh’s Remarks

Page 3: Electrical  Architecture and Interfaces

Grounding principlesIn order to avoid ground loops:

Use of galvanically isolated DC/DC convertersPrimary grounds (28V Battery) shall be

connected on Mechanical ground of PWP Secondary grounds of DC/DC converters shall

be connected on a single point on Mechanical ground of sub-equipments (DP, PDM)

Mechanical grounds connected togetherDifferential links (LVDS) between HK, CCB and

PDM_Board, HVPS-1

Page 4: Electrical  Architecture and Interfaces

Harness shieldingAccording to the recommendations of Johan Panh:

Primary power supplies : twisted pairs, not shielded Secondary power supplies :

LVPS-PDM <==> PDM_Board : twisted pairs, shielded, with shielding connected to mechanical ground (360°) on each sides (HF immunity)

HVPS-1 <==> HVPS-2 : twisted pairs, shielded, with shielding connected to mechanical ground on HVPS-1 side and open on load (BF immunity)

LVPS-HK, LVPS1-DP, LVPS2-DP <==> HK, CCB, CLKB, GPSR, CPU, DST: twisted pairs, not shielded (TBC: internal connection of DP)

Differential digital links: twisted pairs, shielded, with the shielding connected to mechanical ground (360°) on each side

Page 5: Electrical  Architecture and Interfaces

2 2 222 2 2222

HK

1

2

BAT_RET (P)28V_BAT (P)

GND_28V (S)

GND_3.3V (S)

28V (S)

3.3V (S)

GND_M HVPS-1 would have DC/DC

converters to isolate the powers

GND_M

0-2.44V

STATUS

ON/OFF

3 DAC

6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS-1

4 differential transmitters

2 differential receivers

CS_DAC

CS_IO

HVPS-1

MISOMOSISCK

MOSI

MOSI

6 bidirectional signals6 status signals

I/O expanders

4 differential receivers

MISO

Interrupt

SCK

SCK

Interrupt

HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : 1st flight version

D-Sub 15 F

D-Sub 15 F

D-Sub 15 M

D-Sub 15 M

6 C-W

D-Sub 9 FD-Sub 9M

BATTERY

3 C-W 6 x 14 HV lines

3 x 14 HV lines

9

9

3

3

STA

TU

S

3

ON

/OF

F

3 0

-2

.44

V

GND_M

HVPS-2CS_DAC

SCKMOSICS_OUT 6 DAC

6

D-S

UB

2

5 F

D-S

UB

2

5

M

D-Sub 9 FD-Sub 9M

24 wires

PDM_Board

Micro-D 9 F

Micro-D 9 M

4 differential receivers

4 differential transmitters

4 Differential signals (LVDS) ( x2 = 8 wires)between PDM_Board and HVPS-1

4 SWITCHCOMMANDS

4 SWITCHCOMMANDS

2 differential transmitters

Page 6: Electrical  Architecture and Interfaces

HVPSArchitecture and I/F are now stable:

2 HVPS boxes in PDM box: HVPS-1:

2 CV DC/DC (28V & 3.3V) for ground isolation SPI I/F with HK, LVDS I/F with PDM-Board (switch pulses), 3 DACs (HV tuning), 3 Cockcroft-Walton Converters.

HVPS-2: 6 DACs (HV tuning), 6 Cockcroft-Walton Converters.

Page 7: Electrical  Architecture and Interfaces

HK

Electrical Interfaces are clearly defined (connectors, pinout Ok)

Subd25 or 37?

Subd25 or µSubd9?

Page 8: Electrical  Architecture and Interfaces

DP Block Diagram28V

DPLVPS

vSpaceWire

5V

Ethernet

vSATAData

Storage

Visible cam(adv. opt.)

SpaceWire

to PCI

vPCI

GPS

v

HK system

v5V

5V

28V

CLKs, Sync, Trig, Busy

RS232

PDMbox

vRS422

12V, 5V, 3.3V

RS 422

Fast

par

alle

llin

k

SPI

PWP

V, T

mon

. SPI

12V

CCB

CPU

IR Camera(adv. opt.)

CLKboard

SIREN system

vSpaceWire

V, A Monitor

1PPS

TLS

Ana

log

( T)

Analog( T)

RelaysboardHL-CMD CC

Data Processor block diagram

Page 9: Electrical  Architecture and Interfaces

DP connectors ?

Pinout and connectors need to be checked and update very soon

CPU CCB CLKb GPSr HK LVPS1 LVPS2 LVPS3 PDLVPS PDM PWP SIREN TLSCPU - MDM

DB9MDM DB9

- DB9 +DB9

DB15 - - - - - RJ45 -

CCB MDM DB9

- MDM DB15

- DB15 - DB9 - - MDMDB51

- - -

CLKb MDM DB9

MDM DB15

- MDM DB9

DB15 - DB9 - - - - - -

GPSr - - MDM DB9

- DB15 - DB9 - - - - - -

HK DB9 + DB9

DB15 DB15 DB15 - DB15 DB15 DB15 DB15 MDM DB15

- DB9? 3 x DB9

LVPS1 DB15 - - - DB15 - - - - - DB9 - -LVPS2 - DB9 DB9 DB9 DB15 - - - - - DB9 - -LVPS3 - - - - DB15 - - - - - - - -PDLVPS - - - - DB15 - - - -PDM - MDM

DB51- - DB15 - - - DEMM9S

DB9+DB15- - - -

PWP - - - - - DB9 DB9 DB9 DB9 - - ? -SIREN RJ45 - - - DB9 - - - - - - -TLS 3 x DB9 -

Page 10: Electrical  Architecture and Interfaces

LVPS-PDM

PDM Power connections

Pinout and connectors between PDM_Board and EC_Asic are checked

GND_5V_EC (S)

5V_EC (S)

EC-ASIC

3.3Vd_EC (S)

1.5V_EC (S)

GND_1.5V_EC (S)

GND_3.3Vd_EC (S)

3.3Va_EC (S)GND_3.3Va_EC (S)

FPGA

GND_MConnector

PDM-LVPS

GND_5V_PDMB (S)

5V_PDMB (S)

PDM BOARDTES 1-0511V

Regulator

1.5V

GND_M

3.3V

EC_ASIC 1

FPGA ground should be linked to the GND_M

GND_1.5V_EC should be linked to the gnd of the FPGA1V

1.8V

Connector PDM_EC_ASIC

Page 11: Electrical  Architecture and Interfaces

PDM

Kapton cable

Fixation screw

MAPMT

ASIC B ASIC FASIC D

68 pins

ASIC A

68 pins

ASIC CASIC E

120 pins

A B C D E F68 pins

68 pins

68 pins

68 pins

EC_HV

Interfaces with:

CCB µSubd51 HVPS µSubd9

HK µSubd9? Subd25 on HK? POWER Subd9

Page 12: Electrical  Architecture and Interfaces

PWPPWP2-OutsidePower 22W??

Which dimensions

PWP1-InsidePower 250 W ??

All connectors on a single side

PWP-outside

PWP-Inside

9 pins Sub-Dconnector

To IR-CAM

ToLVPS-DP1LVPS-DP2LVPS-PDMLVPS-HKHVPS1

Plus two additional

Page 13: Electrical  Architecture and Interfaces

PWP ComponantBattery Cells, Connectors and Cables

•Cells

•Connectors

•Cables

Option I: In case of 90W power consumption it will be necessary 20 cells of Saft G62/1.2 Option II: In case of 250W power consumption it will be necessary 50 Cells of Saft G62/1.2

The Connectors we are going to use are 9 pins D-Sub connectors for all interfaces and subsystems.

The Cables we are going to use are THERMAX MIL-DTL-22759/91,92 for all interfaces and subsystems.

Page 14: Electrical  Architecture and Interfaces

PWP Power Budget ??

Interface Power ConsumptionIR Camera 22W

High Voltage Power Supply 2WLVPS DP1 7.2WLVPS DP2 7.2W

Housekeeping 6WLVPS-PDM 2.4W

CPU 14.4WCCB 5W

Data Storage 18WGPS 1.2WCLK 3.6W

Additional Spare 15WHeaters TBC

Total: 111.2W+20% of security Margin = 133.4W Additional Heaters and backup = 70W(150+60)+20% of security Margin = 243.6WThis version should be discussed

250W

Interface Power Consumption

IR Camera 22WHigh Voltage Power Supply + Switches

2W

Housekeeping 6WCCB 5W

LVPS DP1 7.2WLVPS DP2 7.2WLVPS-PDM 2.4W

Additional Spare 15WTotal Power Budget:

74W+20% of Security Margin = 90W

90W

- Which congiuration for Baseline?- Which power for Pack2 for IR Camera?

Page 15: Electrical  Architecture and Interfaces

PWP

Switch

- +

Battery Pack

Electrical Fuse

Thermal Fuse

External Pwr Supply

Main Power

Primary Return

Power

Splitter

2

1

3

4

D-Sub

9 Pi

n D

-Sub

Fem

ale

Where:

1) LVPS Connector/9 pins D-Sub Connector2) IR Camera Connector/ 9 pins D-Sub Connector3) Spare A / 9 pins D-Sub Connector4) Spare B/ 9 pins D-Sub Connector

Making Zoom in any D-Sub Connector

1 2 3 4 5

6 7 8 9

+28V Return

Battery Box Distributor Box

9 Pin D-Sub M

ale

Short circuit risk?

- Femeale connector on power side- PinOut of External Power- Common Ground or Ground Switching ?- Pinout Compatibility with LVPSs and HVPS1 ?- IR Camera the same way with separate Battery?- Who Provides Material and cables?

Femeale connector?

Page 16: Electrical  Architecture and Interfaces

SIREN

Electrical Interfaces are clearly defined (connectors, pinout Ok)

HK

DP

232/422

Page 17: Electrical  Architecture and Interfaces

CablesWho provide cables between:

HK and SIREN ? HK and DP ? PDM and DP ? DP and SIREN ? PWP_1 and LVPS (4)? PWP_1 and HVPS_1? LVPS_PDM and PDM? HK et HVPS_1? PDM_and HVPS_1? CCB and PDM_board? HK et PDM Board? IR Camera ?

Page 18: Electrical  Architecture and Interfaces

ToDo Which Power budget PWP_1 ?

Clarify Power Pack interfaces.

Who provides Batteries (PowerPack 1 and Power Pack 2 ?

Clarify internal and external interfaces for DP (update Synoptic).

Define cables, providers ?

Use in general Femeale connector on Fixed on boxes exept for power side to avoid short circuit risk!!!

Documentation