ELEN 468 Lecture 171 ELEN 468 Advanced Logic Design Lecture 17 Midterm1 Review

ELEN 468 Lecture 17 1

ELEN 468Advanced Logic DesignLecture 17Midterm1 Review


Description Styles Explicit structural Implicit structural Explicit continuous assignment Implicit continuous assignment Data flow/RTL Algorithm-based

Structural

Behavioral


Simulation without Delay

0 10 20 30 40 50

A = xB = xC = xD = x

A = 1B = 0

C = 0

D = 1

B = 1

C = 1

D = 0

A = 0

C = 0

D = 1

B = 0 tsim

B

A

C

D

B

AC D

X

X

X

X Y


Simulation with Delay

0 10 20 30 40 50

A = xB = xC = xD = x

A = 1B = 0

C = 0

D = 1

B = 1

C = 1

D = 0

A = 0

C = 0

D = 1

B = 0

tsim

B

A

C

D B

A CD

X

X

X

X

3 2

13

15


Inertial DelayDelay is caused by charging and discharging node capacitors in circuit

Gate delay and wire delayPulse rejection If pulse with is less than delay, the pulse

is ignored

B

AC D


Example of De-scheduling

A=xB=xC=xD=x

A=1B=0

C=1

D=0

B=1

A=0

C=0

C=1

D=1

A

B

C

D0 10 20 30 40 50

B

A CD

3 2

T_sim

33 3515


Variables Represent values of signals in physical circuit in a digital format Nets – Represent physical connectivity Registers – Abstractions of storage elements Nets and registers may be either scalars or vectors


Direct Substitution of Parameters

module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y =

a~^b;endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2);endmodule

Value of a constant can be changed during compliationDon’t confuse with assigning delay to primitives Module

instantiation do not have delay

Primitives do not have parameters


UDP: Combinational Behavior

primitive mux_prim ( out, select, a, b ); output out; input select, a, b; table// select a b : out

0 0 0 : 0; // Each column -> a port0 0 1 : 0; // Last column -> single output0 0 x : 0; // Input port column order = port list order0 1 0 : 1; // No inout port0 1 1 : 1; // Only 0, 1, x on input and output0 1 x : 1; // A “z” input is treated as “x”1 0 0 : 0; // If an input vector is not in table, output -> “x”1 1 0 : 0;1 x 0 : 0;1 0 1 : 1;1 1 1 : 1;1 x 1 : 1;x 0 0 : 0; // Reduce pessimismx 1 1 : 1; // Without these 2 rows, output “x” for select = “x”

endtableendprimitive

mux_prim

select

out

a

b


Edge-sensitive Behaviorprimitive d_flop( q, clock, d );

output q;input clock, d;reg q;table

// clock d state q/next_state(01) 0 : ? : 0; // Parentheses indicate signal transition(01) 1 : ? : 1; // Rising clock edge(0?) 1 : 1 : 1;(0?) 0 : 0 : 0;(?0) ? : ? : -; // Falling clock edge? (??) : ? : -; // Steady clockendtable

endprimitive

clock

d qd_flop


Delay Models Gate delay Intrinsic delay Layout-induced delay due to capacitive load Waveform slope-induced delay

Net delay/transport delay Signal propagation delay along interconnect

wires Module path delay Delay between input port and output port


Gate Delayand (yout, x1, x2); // default, zero gate delayand #3 (yout, x1, x2); // 3 units delay for all transitionsand #(2,3) G1(yout, x1, x2); // rising, falling delayand #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4);// Multiple instancesa_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoffbufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable);// min:typ:max / rise, fall, turnoff

•Simulators simulate with only one of min, typ and max delay values •Selection is made through compiler directives or user interfaces•Default delay is typ delay


Example of Time Scale`timescale 1 ns / 10 psmodule modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1,

x2 );endmodule`timescale 10 ns / 10 nsmodule modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin

#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;

endendmodule

$t $real_t x1 x2 y-------------------------------------------------0 0.000000 x1=x x2=x y=x5 5.000000 x1=0 x2=0 y=x5 5.323000 x1=0 x2=0 y=110 10.000000 x1=0 x2=1 y=115 15.000000 x1=1 x2=1 y=115 15.424000 x1=1 x2=1 y=020 20.000000 x1=1 x2=0 y=020 20.323000 x1=1 x2=0 y=1


Simple Module Path

Source of path must be a net declared as input or outputDestination of path must be a net or reg declared as output or inout

Parallel paths, “=>”

Full connection paths, “*>”


Example of Simple Module Path Delaymodule nand1( out, A, B );

output out;input A, B;nand ( out, A, B );

specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 );// 0->1, 1->0, 0->z, z->1, 1->z, z->0endspecify

endmodule

A

B

out

•Specify blocks declare paths•Its path can override structural delays


Combinational Logic Delay

Combinational logic delay <= clock period

Combinational Logic

Register

Primary Input

Register

Primary

Outputclock


Example of Static Timing Analysis

Arrival time: input -> output, take max Required arrival time: output -> input, take minSlack = required arrival time – arrival time

2

3

43

7

11

2

3

7/4/-35/3/-2

4/7/38/8/0

9/6/-3

20/17/-3

11/11/018/18/0

23/20/-3


AssignmentContinuous assignment Values are assigned to net variables due to

some input variable changes “assign …=… “

Procedural assignment Values are assigned to register variables when

certain statement is executed in a behavior Procedural assignment, “=“ Procedural continuous assignment, “assign …

=… [deassign] “ Non-blocking assignment, “<=“


Blocking and Non-blocking Assignmentinitial begin

a = 1;b = 0;a = b; // a = 0;b = a; // b = 0;

end initial begin

a = 1;b = 0;a <= b; // a = 0;b <= a; // b = 1;

end

Blocking assignment “=“ Statement order matters A statement has to be executed

before next statementNon-blocking assignment “<=“

Concurrent assignment Normally the last assignment at

certain simulation time step If it triggers other blocking

assignments, it is executed before the blocking assignment it triggers

If there are multiple non-blocking assignments to same variable in same behavior, latter overwrites previous


Procedural Continuous Assignment

Continuous assignment establishes static binding for net variablesProcedural continuous assignment (PCA) establishes dynamic binding for variables “assign … deassign” for register

variables only “force … release” for both register

and net variables


“assign … deassign” PCA

Binding takes effect when PCA statement is executedCan be overridden by another PCA statement“deassign” is optional“assign” takes control, “deassign” release control

module flop ( q, qbar, preset, clear, clock, data );…assign qbar = q;initial

q = 0;always @ ( negedge clk )

q = data;always @ ( clear or preset )

begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q;end

endmodule


Example of assign module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out;

always @(select) begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1’bx; end

endmodule

y_out changes with a;


Alternative module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out;

always @(select or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end

endmodule

Value of ‘a’ is assigned to y_out at this time


Exampleinitial begin a = #10 1; b = #2 0; c = #3 1; end

initial begin d <= #10 1; e <= #2 0; f <= #3 1; end

t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x 0 110 1 x x 1 0 112 1 0 x 1 0 115 1 0 1 1 0 1


Tell the Differencesalways @ (a or b) y = a|b; always @ (a or b) #5 y = a|b;

always @ (a or b) y = #5 a|b;

always @ (a or b) y <= #5 a|b;

Event control is blocked

Which one describes or gate?


Parallel Activity Flow…fork // t_sim = 0 #50 wave = 1;

#100 wave = 0;#150 wave = 1;#300 wave = 0;// executes at t_sim = 300

join…

module race ( … );…fork #150 a = b; #150 c = a;join

endmodule

module fix_race ( … );…fork a = #150 b; c = #150 a;join

endmodule

Not supported by synthesisFor simulation in testbench


Tasks and FunctionsSub-programs that encapsulate and organize a description Tasks – create a hierarchical

organization of the procedural statements

Functions – substitute for an expression


SetupHold$setuphold(data, posedge clock, 5, 2);

5 5clock

data

2 2


Finite State MachinesNext state and outputCombinational logic

Register

clock

input output

Next state Combinational

logicRegister

OutputCombinational

logic

inputoutput

clock

Mealy Machine

Moore Machine


Explicit Finite State Machines 1

module FSM_style1 ( … );input …;output …;parameter size = …;reg [size-1:0] state, next_state;

assign outputs = …; // function of state and inputsassign next_state = …; // function of state and inputs

always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state;

endmodule




assign outputs = …; // function of state and inputs

always @ ( state or inputs ) begin

// decode for next_state with case or if statement end

always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state;

endmodule




always @ ( state or inputs ) begin

// decode for next_state with case or if statement endalways @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin

state <= next_state;outputs <= some_value ( inputs, next_state );

end endmodule


FSM Example: Speed Machine

speedaccelerator brake

clock

medium

low stopped

high

a: acceleratorb: brake

a = 1, b = 0

b = 1b = 1

b =

1

b = 1

a =

1, b

=

0

a = 1, b = 0

a = 1, b = 0


Implicit Finite State Machinemodule speed_machine2 ( clock,

accelerator, brake, speed );

input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed;

`define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11

always @ ( posedge clock ) if ( brake == 1`b1 ) case ( speed )

`stopped: speed <= `stopped;`low: speed <= `stopped;`medium: speed <= `low;`high: speed <= `medium;default: speed <= `stopped;

endcase else if ( accelerator == 1`b1 ) case ( speed )

`stopped: speed <= `low;`low: speed <= `medium;`medium: speed <= `high;`high: speed <= `high;default: speed <= `stopped;

endcaseendmodule


Pull Gatesmodule nmos_nand_2 ( Y, A,

B );output Y;input A, B;supply0 GND;tri w;

pullup ( Y );nmos ( Y, w, A );nmos ( w, GND, B );

endmodule

Y

Vdd

A

B


Assign Drive Strengthsnand ( pull1, strong0 ) G1( Y, A, B );wire ( pull0, weak1 ) A_wire = net1 || net2;assign ( pull1, weak0 ) A_net = reg_b;

Drive strength is specified through an unordered pair one value from { supply0, strong0, pull0, weak0 , highz0 } the other from { supply1, strong1, pull1, weak1, highz1 }

Only scalar nets may receive strength assignmentWhen a tri0 or tri1 net is not driven , it is pulled to indicated logic value with strength of pull0 or pull1The trireg net models capacitance holds a charge after the drivers are removed, the net has a charge strength of small, medium(default) or large capacitor


StL

PuH

Ambiguous ControlSu0 St0 Pu0 La0 We0 Me0 Sm0

HiZ0

Su1

St1 Pu1 La1 We1 Me1 Sm1HiZ1

x

bufif0

St0

x

bufif0

Pu1


Strength ReductionDependence of output strength on input strength Combinational and pull gate – NO,

except 3-state gates Transistor switch and bi-directional

gates – YESIn general, output strength <= input strength


Signal Contention: Known Strength and Known Value

Signal with greater strength dominatesSame strength, different logic values wand -> and, wor -> or Otherwise -> x

driver1

driver2

We0

Pu1

Pu1


Example of Rule 1

Su1 St1 Pu1 La1 We1 Me1 Sm1HiZ1


Su0 St0 Pu0 La0 We0 Me0 Sm0

HiZ0

Su1



HiZ0

signal1

signal2

result

Rule 1: Include strengths of ambiguous signal that greater than strength of unambiguous signal


Example of Rule 2

Su1



HiZ0

Su1



HiZ0

signal1

signal2

result


HiZ0

Rule 2: Omit strengths of ambiguous signal <= strength of unambiguous signal, except Rule 3


Example of Rule 3




HiZ0

signal2

result

signal1


HiZ0

Rule 3: If unambiguous and ambiguous signals have different values, take strengths range from Rule1 to strength of unambiguous signal


Logic Synthesis

Translation

Engine

Optimization Engine

Mapping Engine

Behavioral Descriptio

ns

Technology Libraries

Two-level Logic

Functions

Optimized Multi-level

Logic Functions

Technology Implementatio

n


Objective of Synthesis

Area

Delay


General Rules for Combinational Logic

Avoid to model specific technology Synthesis functionality Ignore timingAvoid feedback loops Feedback loop may result in

sequential circuit


Simulation Efficiency and PCA

module orNand1(y, en, a, b, c, d );input en, a, b, c, d;output y;reg y;

always @ (en or a or b or c or d ) y = ~( en & (a | b) & (c | d) );

endmodule

module orNand1(y, en, a, b, c, d );input en, a, b, c, d;output y;reg y;

always @ ( en ) if ( en ) assign y = ~((a|b) & (c|d)); else assign y = 1;

endmoduleLess efficient

Generally, PCA is efficient on implementing combinational logic in behavioral descriptionsKeyword deassign is only used in sequential circuits.


Example of Unwanted Latch

module myMux( y, selA, selB, a, b );input selA, selB, a, b;output y;reg y;

always @ ( selA or selB or a or b ) case ( {selA, selB} )

2’b10: y = a;2’b01: y = b;

endcaseendmodule

b

a

selA’selB

selAselB’

latch

yen

Documents

ELEN 468 Lecture 171 ELEN 468 Advanced Logic Design Lecture 17 Midterm1 Review